CN114582831A - Packaging structure - Google Patents

Abstract

A package structure includes a carrier board, a redistribution layer and a positioning layer. The redistribution layer is located on the carrier board and includes a dielectric layer, a conductive pattern and a pad. The conductive pattern is in the dielectric layer. The pads are located on the dielectric layer and are electrically connected to the conductive patterns. The positioning layer is located on the redistribution layer and has an opening. The orthographic projection of the opening on the carrier overlaps the orthographic projection of the pads on the carrier, and the height of the positioning layer is greater than the height of the pads.

Description

Package structure

technical field

The present invention relates to a packaging structure.

Background technique

With the development of integrated circuits in the direction of high performance, high density, low power consumption and small size, the development of forward-looking packaging has also accelerated. Currently, Fan-out wafer level package (FOWLP) can be applied to high-end products. In order to reduce prices and improve productivity, related companies are also actively developing a fan-out panel level package (Fan-out panel level package, FOPLP) technology.

However, due to the mechanical pick and place (Pick&Place) error and the thermal expansion and contraction of the dielectric layer material, the FOPLP technology still has the problem of die shift, which makes the die cannot be accurately bonded to the redistribution layer (RDL). Moreover, when the area of the carrier board is larger, the magnitude of the chip offset is larger, which makes it difficult to improve the packaging yield.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a packaging structure with improved packaging yield.

An embodiment of the present invention provides a package structure, including: a carrier board; a redistribution layer, located on the carrier board, and comprising: a dielectric layer; a conductive pattern, located in the dielectric layer; and pads, located in the dielectric layer and the positioning layer is located on the redistribution layer and has an opening, wherein the orthographic projection of the opening on the carrier overlaps the orthographic projection of the pad on the carrier, and the height of the positioning layer is greater than that of the pad the height of.

In an embodiment of the present invention, the thermal expansion coefficient of the positioning layer is smaller than the thermal expansion coefficient of the dielectric layer.

In an embodiment of the present invention, the thermal expansion coefficient of the positioning layer is less than 40 ppm/°C.

In an embodiment of the present invention, the thickness of the positioning layer is greater than the thickness of the dielectric layer.

In an embodiment of the present invention, the thickness of the positioning layer is between 10 μm and 100 μm.

In an embodiment of the present invention, the height of the top surface of the positioning layer is higher than the height of the top surface of the pad.

In an embodiment of the present invention, the material of the positioning layer is polyimide (PI), polybenzoxazole (PBO), epoxy resin or siloxane.

In an embodiment of the present invention, the above-mentioned package structure further includes a chip, which is located in the opening of the positioning layer and is electrically connected to the pads.

In an embodiment of the present invention, the chip has a width Y, the pads have a width X, and the aperture of the opening is between (Y+1/2X) to (Y+2X).

In an embodiment of the present invention, the height of the top surface of the positioning layer is lower than the height of the top surface of the chip.

The beneficial effect of the present invention is that, in the packaging structure of the present invention, by arranging a positioning layer with an opening on the redistribution layer, the offset amplitude and orientation of the chip can be adjusted during the subsequent chip bonding process, so that the pins of the chip can be accurately connected. pads on the redistribution layer, thereby improving the yield of the package structure.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a package structure according to an embodiment of the present invention.

FIG. 2A is a partial top plan view of a package structure according to an embodiment of the present invention.

Fig. 2B is a schematic cross-sectional view taken along the section line A-A' of Fig. 2A.

The reference numbers are as follows:

10, 20: Package structure

110: carrier board

120: Redistribution layer

130: Positioning layer

130T: top surface

140: Chip

140T: top surface

141: pin

A-A': Hatch line

C1, C2, C3: Conductive pattern

CL: connecting material

G: Gap

H1: Thickness/Height

H2, H4: height

H3: Thickness

HI1, HI2, HI3: Thickness

I1, I2, I3: Dielectric layers

OP: open mouth

PD: pad

PT: Top surface

SW: Sidewall

V1, V2, V3: Through holes

W: Caliber

X: width

Y: width

Detailed ways

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. The same reference numerals refer to the same elements throughout the specification. It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to a physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may refer to the existence of other elements between the two elements.

The terminology used herein is for the purpose of describing particular embodiments only and is not limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms including "at least one" or mean "and/or" unless the content clearly dictates otherwise. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will also be understood that when used in this specification, the terms "comprising" and/or "comprising" designate the presence of stated features, regions, integers, steps, operations, elements and/or parts, but do not exclude one or more The presence or addition of other features, regions, integers, steps, operations, elements, parts and/or combinations thereof.

Furthermore, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe one element's relationship to another element, as shown in the figures. It should be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "lower" may include an orientation of "lower" and "upper", depending on the particular orientation of the drawings. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "below" can encompass both an orientation of above and below.

"About," "approximately," or "substantially" as used herein includes the stated value and those of ordinary skill in the art, given the measurement in question and the particular amount of error associated with the measurement (ie, the limitations of the measurement system). The average within an acceptable deviation range for a specific value determined by a person. For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, "about", "approximately", or "substantially" as used herein may select a more acceptable range of variation or standard deviation depending on optical properties, etching properties, or other properties, and may not apply to all nature.

FIG. 1 is a schematic cross-sectional view of a package structure 10 according to an embodiment of the present invention. The package structure 10 includes: a carrier board 110; a redistribution layer 120 located on the carrier board 110 and including: a dielectric layer I1; a conductive pattern C1 located in the dielectric layer I1; and a pad PD located on the dielectric layer I1 , and is electrically connected to the conductive pattern C1; and the positioning layer 130 is located on the redistribution layer 120 and has an opening OP, wherein the orthographic projection of the opening OP on the carrier board 110 overlaps the orthographic projection of the pad PD on the carrier board 110, and The height H1 of the positioning layer 130 is greater than the height H2 of the pad PD.

In the package structure 10 of an embodiment of the present invention, by providing the positioning layer 130 with the opening OP, the magnitude of chip offset can be reduced in the subsequent chip bonding process, thereby helping to improve the packaging yield.

Hereinafter, with reference to FIG. 1 , the embodiment of each element of the package structure 10 will be described continuously, but the present invention is not limited thereto.

In this embodiment, the carrier board 110 is, for example, a carrier for carrying the redistribution layer 120 and the positioning layer 130 . In some embodiments, the thermal expansion coefficient of the carrier plate 110 may be between 3 and 10 ppm/°C. The material of the carrier plate 110 may be glass, wafer, or other applicable materials. For example, in this embodiment, the material of the carrier plate 110 is glass with a thermal expansion coefficient of about 8.5 ppm/°C, but the invention is not limited to this. In other embodiments, the carrier 110 may be a wafer, and the wafer may have a coefficient of thermal expansion of about 3 ppm/°C.

In this embodiment, the dielectric layer I1 is located on the carrier board 110 and covers the conductive pattern C1. The dielectric layer I1 may also have a through hole V1, so that the pad PD can be electrically connected to the conductive pattern C1 through the through hole V1. In some embodiments, in addition to the dielectric layer I1, the redistribution layer 120 may further include dielectric layers I2 and I3, and the pad PD may be located on the dielectric layer I3, but not limited thereto. In other embodiments, the redistribution layer 120 may include fewer or more dielectric layers, eg, two, four, or more dielectric layers, as desired.

In this embodiment, the dielectric layers I1 , I2 , and I3 of the redistribution layer 120 can be stacked on the carrier board 110 in sequence, and the thermal expansion coefficients of the dielectric layers I1 , I2 , and I3 can be respectively 30 to 80 ppm/ °C, but not limited thereto. The materials of the dielectric layers I1, I2, and I3 can be selected from polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB) and other suitable materials, respectively. Material. In addition, the dielectric layers I1, I2, and I3 may also have a single-layer structure or a multi-layer structure, respectively. The multi-layer structure, such as a stack of any two or more layers of the above materials, can be combined and changed as needed.

In this embodiment, in addition to the conductive pattern C1, the redistribution layer 120 may further include conductive patterns C2, C3, and the conductive patterns C1, C2, C3 may be located in the dielectric layers I1, I2, I3, respectively, but not This is limited. In other embodiments, the redistribution layer 120 may include fewer or more layers of conductive patterns, such as two, four or more layers of conductive patterns, as needed or in accordance with the number of dielectric layers. The redistribution layer 120 can form required electrical connections in the dielectric layers I1, I2, and I3 through the conductive patterns C1, C2, and C3, and the redistribution layer 120 can be electrically connected to external components or traces through the pads PD. Wire.

For example, in this embodiment, the dielectric layers I1, I2, and I3 may have vias V1, V2, and V3, respectively, and the pads PD may pass through the vias V3 to connect to the conductive pattern C3, and the conductive pattern C3 may pass through the vias V3. The conductive pattern C2 is connected through the via hole V2, and the conductive pattern C2 can be connected to the conductive pattern C1 through the via hole V1, so that the pad PD can be electrically connected to the conductive pattern C1. The number of pads PD is not particularly limited, and the required number of pads PD can be set as required.

The materials of the conductive patterns C1 , C2 , C3 and the pads PD may include metals or alloys with good conductivity, such as aluminum, molybdenum, titanium, copper, nickel, gold, tin, silver and other metals, alloys thereof, or combinations thereof. For example, in one embodiment, the conductive patterns C1 , C2 , C3 and the pads PD may each independently be a single-layer structure or a multi-layer structure, and the multi-layer structure includes, for example, sequentially stacked titanium layers, aluminum layers, and titanium layers , but not limited to this.

The positioning layer 130 may expose all the pads PD. For example, in this embodiment, the positioning layer 130 may not cover the pad PD at all. However, in some embodiments, the positioning layer 130 may also partially cover each pad PD and expose a portion of each pad PD.

In some embodiments, the thermal expansion coefficient of the alignment layer 130 may be smaller than the thermal expansion coefficient of any of the dielectric layers I1 , I2 , and I3 . In this way, it can also help to suppress or eliminate the warpage of the package structure 10 . For example, in some embodiments, the thermal expansion coefficient of the positioning layer 130 may be between the thermal expansion coefficient of the carrier board 110 and the thermal expansion coefficient of any of the dielectric layers I1, I2, and I3, and the thickness of the positioning layer 130 H1 may be greater than the thickness H3 of the carrier board 110 , so that the stress exerted by the positioning layer 130 and the carrier board 110 on the redistribution layer 120 can cancel each other. In some embodiments, the thermal expansion coefficient of the alignment layer 130 may be less than 40 ppm/°C, for example, the thermal expansion coefficient of the alignment layer 130 may be about 30 ppm/°C or 15 ppm/°C. For example, the material of the positioning layer 130 may be polyimide (PI), polybenzoxazole (PBO), epoxy resin or siloxane, but not limited thereto.

In some embodiments, the thickness H1 of the positioning layer 130 may be greater than the thickness of any one of the dielectric layers I1 , I2 , and I3 . For example, the thickness H1 of the positioning layer 130 may be greater than the thickness HI1 of the dielectric layer I1; alternatively, the thickness H1 of the positioning layer 130 may be greater than the thickness HI2 of the dielectric layer I2; or the thickness H1 of the positioning layer 130 may be greater than the dielectric layer I3 Alternatively, the thickness H1 of the positioning layer 130 may be greater than the maximum thickness of the dielectric layers I1, I2, and I3. In some embodiments, the thickness H1 of the positioning layer 130 may range from 10 μm to 100 μm, for example, about 20 μm, 50 μm or 80 μm. In some embodiments, the height H1 of the top surface 130T of the positioning layer 130 from the redistribution layer 120 may also be greater than the height H2 of the top surface PT of the pad PD from the redistribution layer 120 .

The method of forming the opening OP of the positioning layer 130 is not particularly limited. For example, in some embodiments, the opening OP may be formed by a photolithography process. In other embodiments, the opening OP may be formed by means of laser drilling.

2A to 2B continue to describe other embodiments of the present invention, and the element numbers and related contents of the embodiment in FIG. 1 are followed, wherein the same numbers are used to represent the same or similar elements, and the same elements are omitted. Description of technical content. For the description of the omitted part, reference may be made to the embodiment of FIG. 1 , which will not be repeated in the following description.

FIG. 2A is a partial top schematic view of a package structure 20 according to an embodiment of the present invention. Fig. 2B is a schematic cross-sectional view taken along the section line A-A' of Fig. 2A. The package structure 20 includes a carrier board 110 , a redistribution layer 120 and an alignment layer 130 . The redistribution layer 120 may include dielectric layers I1, I2, I3, conductive patterns C1, C2, C3, and a plurality of pads PD. The positioning layer 130 may have a plurality of openings OP, and the plurality of openings OP may be distributed in the positioning layer 130 in an array manner.

Compared with the package structure 10 shown in FIG. 1 , the package structure 20 shown in FIGS. 2A to 2B is different in that the package structure 20 further includes a plurality of chips 140 , and the chips 140 are respectively located in the openings OP of the positioning layer 130 . , and is electrically connected to pad PD.

For example, in this embodiment, the chip 140 may further include a plurality of pins 141 , and the pins 141 may be electrically connected to the pads PD through connecting materials CL, respectively. The connecting material CL is, for example, solder, conductive glue or other materials. In some embodiments, other conductive materials or conductive glue may be further included between the connecting material CL and the pins 141 or the pads PD.

In this embodiment, assuming that the chip 140 has a width Y and the pad PD has a width X, the aperture W of the opening OP can be between (Y+1/2X) to (Y+2X). That is, the gap G between the sidewall SW of the chip 140 and the positioning layer 130 may be between 1/4X to X, that is, the gap G is preferably smaller than the width X of the pad PD. In this way, when the chip 140 is placed in the opening OP by mechanical pick and place to connect the pins 141 and the pads PD, the offset range and orientation of the chip 140 can be adjusted, which helps the pins 141 to be accurately connected to the pads. The PD enables the chip 140 to be precisely bonded to the redistribution layer 120 .

In some embodiments, the height H1 of the top surface 130T of the positioning layer 130 from the redistribution layer 120 may be lower than the height H4 of the top surface 140T of the chip 140 from the redistribution layer 120 , but not limited thereto. In some embodiments, the height H1 of the top surface 130T of the positioning layer 130 from the redistribution layer 120 may still be higher than the height H4 of the top surface 140T of the chip 140 from the redistribution layer 120 .

To sum up, in the package structure of the present invention, by disposing the positioning layer with openings on the redistribution layer, the offset range and orientation of the chip can be adjusted during the subsequent chip bonding process, so that the pins of the chip can be accurately docked to the redistribution layer. The pads of the wiring layer, thereby improving the yield of the package structure.

Although the present invention has been disclosed by the above examples, it is not intended to limit the present invention. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention as defined by the appended claims.

Claims (10)

1. A package structure, comprising: carrier board; A redistribution layer, located on the carrier board, and comprising: dielectric layer; a conductive pattern in the dielectric layer; and a pad on the dielectric layer and electrically connected to the conductive pattern; and a positioning layer located on the redistribution layer and having an opening, Wherein, the orthographic projection of the opening on the carrier plate overlaps the orthographic projection of the pad on the carrier plate, and the height of the positioning layer is greater than the height of the pad. 2. The package structure of claim 1, wherein a thermal expansion coefficient of the alignment layer is smaller than a thermal expansion coefficient of the dielectric layer. 3. The package structure of claim 1, wherein the thermal expansion coefficient of the alignment layer is less than 40 ppm/°C. 4. The package structure of claim 1, wherein a thickness of the alignment layer is greater than a thickness of the dielectric layer. 5 . The package structure of claim 1 , wherein the positioning layer has a thickness ranging from 10 μm to 100 μm. 6 . 6 . The package structure of claim 1 , wherein a top surface height of the positioning layer is higher than a top surface height of the pads. 7 . 7. The package structure according to claim 1, wherein the material of the positioning layer is polyimide, polybenzoxazole, epoxy resin or siloxane. 8 . The package structure of claim 1 , further comprising a chip located in the opening of the positioning layer and electrically connected to the pad. 9 . 9. The package structure of claim 8, wherein the chip has a width Y, the pad has a width X, and the aperture of the opening is between (Y+1/2X) to (Y+2X). between. 10. The package structure of claim 8, wherein a top surface height of the positioning layer is lower than a top surface height of the chip.

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