CN114582832B - Semiconductor device with a semiconductor layer having a plurality of semiconductor layers - Google Patents
Semiconductor device with a semiconductor layer having a plurality of semiconductor layersInfo
- Publication number
- CN114582832B CN114582832B CN202210207403.8A CN202210207403A CN114582832B CN 114582832 B CN114582832 B CN 114582832B CN 202210207403 A CN202210207403 A CN 202210207403A CN 114582832 B CN114582832 B CN 114582832B
- Authority
- CN
- China
- Prior art keywords
- layer
- spiral
- dummy
- virtual
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention relates to a semiconductor device. The semiconductor device includes a substrate having a first region and a second region, a device layer formed on the first region, and a dummy structure formed on the second region, wherein the dummy structure includes a first spiral dummy layer and a second spiral dummy layer nested with each other. In this way, the dummy structure formed on the semiconductor device can be used not only to uniformize the chip layout density but also as a storage capacitor.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor device having a dummy structure.
Background
In integrated circuit processes, pattern effects, i.e., micro-loading effects, occur due to differences in pattern density in the wafer. Microloading effects are related to phenomena that occur when exposure, etching, and/or polishing is performed on both higher density and lower density patterns. The amount of reaction generated by exposure/etching/polishing becomes locally dense or sparse due to the difference in the exposure/etching/polishing rate between different positions on the film, and causes unevenness in the etching/polishing rate or pattern size after exposure. Too large a density difference of the effective pattern may cause a significant and bad effect. For example, in performing a Chemical Mechanical Polishing (CMP) process, the polishing rate of the low pattern density region is higher than that of the high pattern density region. Thus, regions of different pattern density may be subjected to different thicknesses after a Chemical Mechanical Polishing (CMP) process, i.e., uneven surfaces may be obtained. In addition to the different thickness, uneven substrate surface further causes serious problems such as pattern dimension errors and poor uniformity of critical dimensions.
To counteract this effect, a layout design called dummy fill has been developed during which the circuit layout is adjusted and dummy patterns are filled to locations with low pattern density. The filling of the dummy pattern helps to achieve a uniform effective pattern density on the wafer, thus avoiding pattern effect problems. The prior art generally employs a rectangular dummy pattern and places it in a floating state for electrical characteristics, but such an approach makes it difficult to efficiently utilize valuable space on a semiconductor chip.
Accordingly, there is still a need in the semiconductor process for a semiconductor device having a new dummy structure that can more efficiently utilize space to reduce the size of the semiconductor device.
Disclosure of Invention
The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.
The present invention has been made to overcome the above-mentioned and/or other problems occurring in the prior art, and more particularly, to provide a dummy structure formed on a semiconductor device, which can be used not only for uniformizing the chip layout density but also as a storage capacitor, thereby obtaining additional capacitance and efficiently utilizing space.
Accordingly, an exemplary embodiment of the present invention provides a semiconductor device including a substrate having a first region and a second region, a device layer formed on the first region, and a dummy structure formed on the second region, wherein the dummy structure includes a first spiral dummy layer and a second spiral dummy layer nested with each other.
Preferably, the first spiral virtual layer and the second spiral virtual layer are positioned adjacent to each other at a predetermined interval.
Preferably, the first spiral virtual layer is applied with a first direct voltage, and the second spiral virtual layer is applied with a second direct voltage, and the first direct voltage is greater than the second direct voltage. Preferably, one of the first direct current voltage and the second direct current voltage is a ground voltage. In this way, the storage capacitor is realized by making two nodes of power and ground into a spiral shape instead of a virtual structure having a rectangular floating level, which can reduce the chip size by effectively using space, and help stabilize the entire chip by the shielding effect formed by replacing the floating node with the power node.
Preferably, the first spiral virtual layer and the second spiral virtual layer are formed of polysilicon and/or metal.
Preferably, the first spiral virtual layer and the second spiral virtual layer have square spiral patterns, and the square spiral patterns are broken lines formed by line segments connected end to end.
Preferably, in the square spiral pattern, the included angle between two line segments connected end to end is 90 °.
Preferably, each of the first spiral dummy layer and the second spiral dummy layer includes a first sub-layer extending along all line segments of the square spiral pattern, an insulating layer formed on a side of the first sub-layer facing in the same direction, and a second sub-layer formed on a side of the insulating layer opposite to the first sub-layer, wherein the insulating layer electrically isolates the first sub-layer from the second sub-layer.
Preferably, at least a portion of the first spiral virtual layer and the second spiral virtual layer are centered with respect to each other in the virtual structure.
Preferably, the semiconductor device further includes a MOS transistor formed on the second region, wherein the dummy structure is adjacent to a gate of the MOS transistor.
Other features and aspects will become apparent from the following detailed description, the accompanying drawings, and the claims.
Drawings
The invention may be better understood by describing exemplary embodiments thereof in conjunction with the accompanying drawings, in which:
fig. 1 shows a schematic diagram showing a semiconductor device;
fig. 2 shows a schematic diagram of the semiconductor device of fig. 1 filled with dummy structures;
FIG. 3 shows an example of a virtual structure according to an embodiment of the invention;
fig. 4A and 4B illustrate exploded views of a first spiral virtual layer and a second spiral virtual layer of a virtual structure, respectively, according to an exemplary embodiment of the present invention;
FIG. 5 shows an exemplary schematic of a virtual structure in which a first spiral virtual layer and a second spiral virtual layer are respectively applied with different voltages;
Fig. 6 shows a schematic diagram of a virtual structure according to another exemplary embodiment of the present invention;
fig. 7 shows an example of a high voltage MOS capacitor under the same process, and
Fig. 8 shows a schematic diagram of combining a spiral dummy structure with a MOS transistor to increase capacitance.
Detailed Description
In the following, specific embodiments of the present invention will be described, and it should be noted that in the course of the detailed description of these embodiments, it is not possible in the present specification to describe all features of an actual embodiment in detail for the sake of brevity. It should be appreciated that in the actual implementation of any of the implementations, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that while such a development effort might be complex and lengthy, it would nevertheless be a routine undertaking of design, fabrication, or manufacture for those of ordinary skill having the benefit of this disclosure, and thus should not be construed as having the benefit of this disclosure.
Unless defined otherwise, technical or scientific terms used in the claims and specification should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The terms "first," "second," and the like in the description and in the claims, are not used for any order, quantity, or importance, but are used for distinguishing between different elements. The terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, is intended to mean that elements or items that are immediately preceding the word "comprising" or "comprising", are included in the word "comprising" or "comprising", and equivalents thereof, without excluding other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, nor to direct or indirect connections. The phrase "a is substantially equal to B" is intended to take into account tolerances in the process manufacturing, i.e., the values of a and B may be within ±10% of each other. The phrase "X and Y are substantially perpendicular" is intended to take into account tolerances in the process manufacturing, i.e., the angle between X and Y may be between 80 DEG and 100 deg.
In the present application, all the embodiments mentioned herein and the preferred embodiments may be combined with each other to form new technical solutions, if not specifically described. In the present application, all technical features mentioned herein and preferred features may be combined with each other to form new technical solutions, if not specifically stated.
In the description of the embodiment of the present application, the term "and/or" is merely an association relationship describing the association object, and indicates that three relationships may exist, for example, a and/or B, and may indicate that a exists alone, while a and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
Fig. 1 shows a schematic diagram of a semiconductor device 10 according to an embodiment of the invention. Referring to fig. 1, a semiconductor device 10 may include a substrate 100 and one or more device layers 110 formed on a device region of the substrate 100. One or more of the device layers 110 may be a stack of materials, such as are used to form an effective circuit pattern for the semiconductor device 10. As shown in fig. 1, the pattern distribution of the device layer 10 on the substrate 100 is not uniform, and there are distinct areas of low density (e.g., blank areas). Therefore, for uniformity of subsequent semiconductor processes (e.g., CMP), dummy structures need to be filled in these low density regions, thereby making the pattern distribution on the substrate 100 more uniform.
Referring to fig. 2, a schematic diagram of the semiconductor device 10 of fig. 1 filled with dummy structures 120 is shown. As shown in fig. 2, semiconductor device 10 includes one or more dummy structures 120 formed on a blank area of substrate 100. The virtual structure 120 may include a first spiral virtual layer and a second spiral virtual layer nested with each other. The first spiral virtual layer and the second spiral virtual layer are independent of each other and do not intersect each other. For example, the first spiral virtual layer and the second spiral virtual layer may be positioned adjacent to each other at a predetermined interval.
Referring to FIG. 3, an exemplary embodiment of a virtual structure 120 is shown. The virtual structure 120 includes a first spiral virtual layer 121 and a second spiral virtual layer 122 nested with each other. In this example, the first spiral virtual layer 121 and the second spiral virtual layer 122 may have square spiral patterns, and the square spiral patterns are broken lines composed of line segments connected end to end. The two line segments in the square spiral pattern that are connected end to end may be substantially perpendicular, or may have other angles. An advantageous aspect of using polylines is that pattern layout is facilitated, e.g. the pattern layout computational complexity is simplified compared to curves. However, the present invention is not limited to square spiral patterns, for example, circular spiral patterns may be employed.
Fig. 4A and 4B show exploded views of a first spiral virtual layer 121 and a second spiral virtual layer 122 of a virtual structure 120, respectively, according to an exemplary embodiment of the present application. As shown in fig. 4A, the first spiral virtual layer 121 of the virtual structure 120 may be formed of a plurality of line segments (a 1, b1, c1, d1, e1, f1, g1, h1, i1, j1, and k 1) connected end to end. As shown in fig. 4B, the first spiral virtual layer 122 of the virtual structure 120 may be formed of a plurality of line segments (a 2, B2, c2, d2, e2, f2, g2, h2, i2, and j 2) connected end to end. At least a portion of the first spiral virtual layer 121 (e.g., a portion other than the line segment k 1) may be centered with respect to the second spiral virtual layer 122 in the virtual structure 120. Note that the length and number of line segments constituting the first spiral virtual layer 121 and the second spiral virtual layer 122 may be determined according to need and the morphology of the low density region on the semiconductor device, and the present application is not intended to be limited thereto.
In the exemplary embodiment shown in fig. 4A and 4B, the angle between two line segments end to end in the square spiral pattern of the first spiral virtual layer 121 and the second spiral virtual layer 122 is 90 °. The first spiral virtual layer 121 and the second spiral virtual layer 122 may be positioned adjacent to each other at a predetermined interval in the virtual structure 120. Referring back to fig. 3, if the intervals between the first spiral dummy layer 121 and the second spiral dummy layer 122 are uniform and each have a uniform width, the formed dummy structures 120 may take on a rectangular shape on the substrate surface.
In this manner, the dummy structure 120 on the semiconductor device 10 can be used not only to uniformize layout density but also as a storage capacitor, thereby obtaining additional capacitance and efficiently utilizing space.
In use as a storage capacitor, the first spiral virtual layer 121 may be applied with a first direct voltage (e.g., connected to a first power source) and the second spiral virtual layer 122 may be applied with a second direct voltage (e.g., connected to a second power source). The first DC voltage is different from the second DC voltage. The first spiral dummy layer 121 and the second spiral dummy layer 122 may contain the same metal material or may contain different metal materials. Or the first spiral dummy layer 121 and the second spiral dummy layer 122 may also include polysilicon.
Referring to fig. 5, there is shown an exemplary schematic diagram in which the first spiral dummy layer 121 and the second spiral dummy layer 122 of the dummy structure 120 are respectively applied with different voltages. In this example, the first spiral virtual layer 121 may be grounded, and the second spiral virtual layer 122 may have a high level VDD. In this way, a larger capacitance may be generated between the first spiral virtual layer 121 and the second spiral virtual layer 122 due to the repeated spiral structures of the adjacent power supply node (VDD) and Ground Node (GND).
Fig. 6 shows a schematic diagram of a virtual structure 120 according to another exemplary embodiment of the invention. In this example, the first spiral virtual layer 121 and the second spiral virtual layer 122 may each include a first sub-layer 131, an insulating layer 132, and a second sub-layer 133. As shown in fig. 6, the first sub-layer 131 may extend along all line segments of the square spiral pattern of the spiral-shaped dummy layer thereof, and the insulating layer 132 may be formed on one side of the first sub-layer 131 facing in the same direction (e.g., toward the left in fig. 6). The second sub-layer 133 may be formed on a side of the insulating layer 132 opposite to the first sub-layer 131. The insulating layer 132 may electrically isolate the first sub-layer 131 and the second sub-layer 133. The first and second sub-layers 131 and 133 may be formed of polysilicon or metal. In this way, the first sub-layer 131 of one of the first spiral virtual layer 121 and the second spiral virtual layer 122 can be used to form a capacitance together with the second sub-layer 133 of the other of the first spiral virtual layer 121 and the second spiral virtual layer 122 facing the first sub-layer 131.
For example, the insulating layer 132 may extend along the same side of the line segment having the same orientation (the line segments B1, B2, d1, d2, f1, f2, h1, h2, and j2 shown in fig. 4A and 4B) among all the line segments of the square spiral pattern, and be disposed on the end toward the same direction in the first spiral dummy layer 121 and the second spiral dummy layer 122, for example, on the end of the line segment a2 shown in fig. 4B, thereby allowing the formation of a capacitance with the first sub-layer 131 located at the line segment B1. As shown in fig. 6, for example, the first sub-layer 131 may be connected to a first power source (e.g., having a ground voltage GND), and the second sub-layer 133 may be connected to a second power source (having a level VDD) to form a capacitance between the first sub-layer 131 and the second sub-layer 133.
Table 1 shows a test of capacitance results produced by the virtual structure 120 according to an example of the invention. The capacitance is extracted by creating three samples 1-3 using the current process. The virtual structures of sample 1, sample 2 and sample 3 have the same area (10 μm×10 μm), wherein the first spiral virtual layer 121 and the second spiral virtual layer 122 of the virtual structure 120 have a width w=0.18 μm, and a space s=0.12 μm between the first spiral virtual layer 121 and the second spiral virtual layer 122. The dummy structure 120 of sample 1 is shown in fig. 5, in which the first spiral dummy layer 121 and the second spiral dummy layer 122 are each made of metallic aluminum, and capacitance at one of them is measured. The dummy structure 120 of sample 2 is shown in fig. 5, in which the first spiral dummy layer 121 and the second spiral dummy layer 122 are each made of metallic copper, and capacitance at one of them is measured. The dummy structure 120 of sample 3 is shown in fig. 6, wherein the first sub-layer 131 comprises metallic copper (VDD), and the second sub-layer 133 comprises metallic aluminum (ground), and the capacitance at one location is measured.
TABLE 1 capacitance of each sample
Note that the above samples 1 to 3 only show examples of the dummy structures 120 according to the present invention, and are not intended to limit the materials, widths, and pitches of the first spiral dummy layer 121 and the second spiral dummy layer 122. Where the process allows, it is desirable that the widths and spacings of the first spiral-shaped virtual layer 121 and the second spiral-shaped virtual layer 122 be as small as possible to obtain the maximum capacitance value.
For comparison, fig. 7 shows an example of a high voltage MOS capacitor under the same process. Assuming the example high voltage transistor condition that the gate is formed of tungsten and the electrode is formed of metallic aluminum, thickness = 40nm, width = 10 μm, length = 10 μm, then
C＝εrεoA/d＝3.9×(8.854×10-12F/m)×100×10-12m2/(40×10-9m)＝86fF.
By simple comparison, it can be seen that the additional capacitance available to the spiral virtual layer is not small.
Alternatively, as shown in fig. 8, the capacitance may be increased by combining a spiral dummy structure with a MOS transistor used as a capacitor, for example, dummy structure 120 is disposed adjacent to the gate of the MOS transistor. In one example, a dummy structure may be formed on the gate of the MOS transistor, between the source and the drain, i.e., the black box region in fig. 8. In this way, a further coupling capacitance can be formed between the gate and the adjacent spiral virtual layer.
The semiconductor device according to the exemplary embodiment of the present invention is described above in detail. The present invention has advantages in that 1) a space which is used only as a dummy structure to increase a density ratio in the prior art can be used as a storage capacitor, so that an additional capacitance can be obtained and the space can be effectively utilized, 2) replacement of the dummy structure from a floating level to a direct current level helps to stabilize the entire chip due to a shielding effect, and 3) a combination of a spiral-type dummy structure and a MOS capacitor can additionally obtain a large amount of capacitance.
It is to be understood that the above description is intended to be illustrative, and not restrictive. For example, the above-described embodiments (and/or aspects thereof) may be used in combination with one another. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the various embodiments of the invention without departing from the scope thereof. While the dimensions and types of materials described herein are intended to define the parameters of the various embodiments of the invention, the various embodiments are not meant to be limiting and are exemplary embodiments. Many other embodiments will be apparent to those of skill in the art upon reading the above description. The scope of the various embodiments of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
Claims (7)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210207403.8A CN114582832B (en) | 2022-03-04 | 2022-03-04 | Semiconductor device with a semiconductor layer having a plurality of semiconductor layers |
| PCT/CN2022/124766 WO2023165138A1 (en) | 2022-03-04 | 2022-10-12 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210207403.8A CN114582832B (en) | 2022-03-04 | 2022-03-04 | Semiconductor device with a semiconductor layer having a plurality of semiconductor layers |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114582832A CN114582832A (en) | 2022-06-03 |
| CN114582832B true CN114582832B (en) | 2025-07-29 |
Family
ID=81777052
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210207403.8A Active CN114582832B (en) | 2022-03-04 | 2022-03-04 | Semiconductor device with a semiconductor layer having a plurality of semiconductor layers |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN114582832B (en) |
| WO (1) | WO2023165138A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114582832B (en) * | 2022-03-04 | 2025-07-29 | 东芯半导体股份有限公司 | Semiconductor device with a semiconductor layer having a plurality of semiconductor layers |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101128921A (en) * | 2005-03-11 | 2008-02-20 | 松下电器产业株式会社 | Semiconductor integrated circuit having a plurality of transistors |
| CN204407323U (en) * | 2015-02-25 | 2015-06-17 | 中芯国际集成电路制造(北京)有限公司 | The dummy pattern of integrated circuit and semiconductor integrated circuit |
| CN106601712A (en) * | 2015-10-20 | 2017-04-26 | 力成科技股份有限公司 | Carrier substrate |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005136135A (en) * | 2003-10-30 | 2005-05-26 | Oki Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
| US8344443B2 (en) * | 2008-04-25 | 2013-01-01 | Freescale Semiconductor, Inc. | Single poly NVM devices and arrays |
| JP2019140260A (en) * | 2018-02-12 | 2019-08-22 | 株式会社デンソー | Magnetic cell, semiconductor device and manufacturing method of semiconductor device |
| CN114582832B (en) * | 2022-03-04 | 2025-07-29 | 东芯半导体股份有限公司 | Semiconductor device with a semiconductor layer having a plurality of semiconductor layers |
-
2022
- 2022-03-04 CN CN202210207403.8A patent/CN114582832B/en active Active
- 2022-10-12 WO PCT/CN2022/124766 patent/WO2023165138A1/en not_active Ceased
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101128921A (en) * | 2005-03-11 | 2008-02-20 | 松下电器产业株式会社 | Semiconductor integrated circuit having a plurality of transistors |
| CN204407323U (en) * | 2015-02-25 | 2015-06-17 | 中芯国际集成电路制造(北京)有限公司 | The dummy pattern of integrated circuit and semiconductor integrated circuit |
| CN106601712A (en) * | 2015-10-20 | 2017-04-26 | 力成科技股份有限公司 | Carrier substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2023165138A1 (en) | 2023-09-07 |
| CN114582832A (en) | 2022-06-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110957422B (en) | Methods and integrated circuits for manufacturing memory devices | |
| TWI751851B (en) | Integrated circuit, semiconductor structure and method for forming trench capacitor | |
| US7825437B2 (en) | Unity beta ratio tri-gate transistor static random access memory (SRAM) | |
| US6982476B2 (en) | Integrated circuit feature layout for improved chemical mechanical polishing | |
| TWI646646B (en) | Semiconductor component and method of manufacturing same | |
| JP5292005B2 (en) | Semiconductor integrated circuit | |
| TW448561B (en) | Vertical fuse and method of fabrication | |
| CN100403518C (en) | Semiconductor device and manufacturing method thereof, device and method for generating patterns of the device | |
| CN1581475B (en) | Fabrication method of interconnect structure | |
| JP7422168B2 (en) | semiconductor device | |
| CN115020374B (en) | Method for forming microelectronic device and related microelectronic device, memory device and electronic system | |
| CN110349964B (en) | Three-dimensional memory device and manufacturing method thereof | |
| US11721627B2 (en) | Graphene layer for reduced contact resistance | |
| CN114582832B (en) | Semiconductor device with a semiconductor layer having a plurality of semiconductor layers | |
| TW201436104A (en) | Methods of forming barrier layers for conductive copper structures | |
| CN110518016B (en) | Pitch Scalable Stereo NAND Memory | |
| US8053370B2 (en) | Semiconductor device and fabrications thereof | |
| JPH10294367A (en) | Manufacture of semiconductor device | |
| TWI681537B (en) | Semiconductor structure and method of fabricating wiring structure | |
| JP4191110B2 (en) | Semiconductor device | |
| CN110379814A (en) | The production method of three-dimensional storage part and three-dimensional storage part | |
| CN101996930B (en) | Method for making contact joint gasket and semiconductor device | |
| JP2002198435A (en) | Semiconductor integrated circuit device and method of manufacturing the same | |
| CN115020344A (en) | Method for forming semiconductor structure and semiconductor structure | |
| CN101236921A (en) | Method for manufacturing semiconductor element with capacitor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |