CN114598304A - PWM signal generation method and device - Google Patents

Abstract

The invention provides a PWM signal generation method and a device, which are applied to the technical field of power electronics, wherein the method comprises the steps of firstly controlling a clock device to output a first clock signal and a second clock signal, and then respectively counting the first clock signal and the second clock signal according to a preset counting mode; controlling a phase adjusting device to adjust the phase of the second clock signal according to a preset phase difference in the counting process; and finally, controlling the signal generation device to output the PWM signal of the current period according to the count value of the second clock signal or the count values of the first clock signal and the second clock signal. Due to the fact that the phase of the second clock signal changes, the corresponding signal width changes under the condition that the same count value is adopted, and further due to the fact that the preset phase difference is smaller than the clock period, the change of the signal width can be correspondingly smaller than the clock period, namely the PWM signal with the resolution smaller than the clock period and higher precision is achieved, and the actual application requirements are met.

Description

Method and device for generating a PWM signal

technical field

The present invention relates to the technical field of power electronics, and in particular, to a method and device for generating a PWM signal.

Background technique

In some application scenarios in the field of power electronics, a high-precision PWM signal is required for power electronic switching devices to achieve more precise motion control for power electronic switching devices. Specifically, the resolution of the PWM signal is required to reach about 200ps. The performance of the PWM signal is the duration of the high and low levels. By adjusting the duration of the high and low levels, the on-off time of the power electronic switching device can be controlled. Therefore, the adjustment resolution of the PWM signal level width must be finer. Easier to achieve fine output adjustment.

For the PWM signal generation method based on FPGA (Field Programmable Gate Array, programmable logic device), it is mostly realized by counting the clock signal output by the clock device inside the FPGA, and the signal period of the clock signal is fixed. , on this basis, the clock signal is counted, and the product of the signal period and the count value is the corresponding time, and then the control of the high and low level duration of the PWM signal can be realized by adjusting the required count value of the clock signal, that is to say , this technology can realize the minimum adjustment resolution of the PWM signal, that is, the minimum adjustment amount of the pulse width, which corresponds to the signal period of the clock signal.

However, in the prior art, the clock period of the clock signal is basically fixed, with a minimum of 10ns or 5ns, resulting in a minimum resolution of 5ns for the width adjustment of the PWM signal, which makes it difficult to output high-precision PWM signals and cannot meet practical application requirements. .

SUMMARY OF THE INVENTION

The invention provides a method and device for generating a PWM signal, which can adjust the phase of a clock signal, thereby realizing more fine adjustment of the level duration under the same count value, realizing the output of a high-precision PWM signal, and satisfying practical applications. need.

To achieve the above purpose, the technical solutions provided by the application are as follows:

One aspect of the present application provides a method for generating a PWM signal, including:

controlling the clock device to output the first clock signal and the second clock signal;

respectively counting the first clock signal and the second clock signal according to a preset counting manner;

Controlling the phase adjusting device to adjust the phase of the second clock signal according to a preset phase difference during the counting process;

Wherein, the preset phase difference is less than the clock period of the second clock signal;

According to the count value of the second clock signal, or the count value of the first clock signal and the second clock signal, the signal generating means is controlled to output the PWM signal of the current cycle.

Optionally, the controlling the phase adjustment device to adjust the phase of the second clock signal according to a preset phase difference during the counting process includes:

In the case that the count value of the second clock signal is smaller than the preset half-cycle count value, controlling the phase adjustment device to adjust the phase of the second clock signal according to the first preset phase difference;

Wherein, the preset half-cycle count value is set based on the duty cycle of the PWM signal.

Optionally, the process of controlling the signal generating device to output the PWM signal of the current cycle according to the count value of the first clock signal and the second clock signal includes:

Control the signal generating device to perform level switching of the PWM signal of the current cycle according to the count value of the second clock signal;

The signal generating means is controlled to stop the output of the PWM signal of the current cycle according to the count value of the first clock signal.

Optionally, the control of the signal generation device to perform level switching of the PWM signal of the current cycle according to the count value of the second clock signal includes:

Before the count value of the second clock signal reaches the preset half-cycle count value, the control signal generating device outputs the first level of the PWM signal of the current cycle;

When the count value of the second clock signal reaches the preset half-cycle count value, controlling the signal generating device to switch the first level to the second level of the PWM signal of the current cycle;

When the count value of the second clock signal is greater than or equal to the preset half-cycle count value, and the count value of the first clock signal is less than the preset full-cycle count value, control the signal generating device to maintain the output the second level.

Optionally, the controlling the signal generating device to stop the output of the PWM signal of the current cycle according to the count value of the first clock signal includes:

When the count value of the first clock signal reaches a preset full cycle count value, the signal generating device is controlled to stop outputting the second level.

Optionally, it also includes: when the count value of the first clock signal is equal to the preset full cycle count value, clearing the count value of the first clock signal and the count value of the second clock signal to zero .

Optionally, the controlling the phase adjustment device to adjust the phase of the second clock signal according to a preset phase difference during the counting process includes:

When the count value of the second clock signal is greater than or equal to a preset half-cycle count value and less than a preset full-cycle count value, control the phase adjustment device to adjust the phase of the second clock signal according to the second preset phase difference .

Optionally, the process of outputting the PWM signal of the current cycle according to the count value of the second clock signal includes:

Control the signal generating device to perform level switching of the PWM signal of the current cycle according to the count value of the second clock signal;

The signal generating means is controlled to stop the output of the PWM signal of the current cycle according to the count value of the second clock signal.

Optionally, the control of the signal generation device to perform level switching of the PWM signal of the current cycle according to the count value of the second clock signal includes:

Before the count value of the second clock signal reaches the preset half-cycle count value, the control signal generating device outputs the first level of the PWM signal of the current cycle;

When the count value of the second clock signal is equal to the preset half-cycle count value, controlling the signal generating device to switch the first level to the second level of the PWM signal of the current cycle;

When the count value of the second clock signal is greater than or equal to the preset half-cycle count value and less than a preset full-cycle count value, the signal generating device is controlled to maintain outputting the second level.

Optionally, the controlling the signal generating device to stop the output of the PWM signal of the current cycle according to the count value of the second clock signal includes:

When the count value of the second clock signal reaches the preset full cycle count value, the signal generating device is controlled to stop outputting the second level.

Optionally, the method further includes: when the count value of the second clock signal reaches the preset full cycle count value, clearing the count value of the second clock signal to zero.

Optionally, in the process of controlling the signal generating device to output the first level of the PWM signal of the current cycle, the phase adjusting device is controlled to adjust the phase of the second clock signal according to a third preset phase difference.

Optionally, the preset counting manner includes one of counting up, counting down, counting up and down, and counting down.

A second aspect of the present application provides a PWM signal generation device, including: a clock device, a phase adjustment device, a signal generation device, and a main controller, wherein,

The first output end of the clock device is connected to the signal generating device;

The second output end of the clock device is connected to the signal generating device via the phase adjusting device;

The main controller is respectively connected with the clock device, the phase adjustment device and the signal generation device;

The main controller executes the PWM signal generation method according to any one of the above aspects of the present application.

The PWM signal generation method provided by the present invention firstly controls the clock device to output the first clock signal and the second clock signal, and then counts the first clock signal and the second clock signal respectively according to a preset counting method; The phase adjusting device adjusts the phase of the second clock signal according to the preset phase difference; finally, according to the count value of the second clock signal, or the count value of the first clock signal and the second clock signal, the signal generating device is controlled to output the PWM signal of the current cycle . Because the phase of the second clock signal changes, the corresponding signal width changes when the same count value is used. Furthermore, since the preset phase difference is smaller than the clock period, the change in the signal width will be correspondingly smaller than the clock period, that is, the realization of A PWM signal with a resolution smaller than the clock period and a higher precision is obtained to meet practical application requirements.

Description of drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the accompanying drawings that are used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained according to these drawings without creative effort.

1 is a flowchart of a method for generating a PWM signal provided by an embodiment of the present invention;

2a-2d are schematic waveform diagrams of a first PWM signal generation process provided by an embodiment of the present invention;

3a-3d are schematic waveform diagrams of a second PWM signal generation process provided by an embodiment of the present invention;

4a-4d are schematic waveform diagrams of a third PWM signal generation process provided by an embodiment of the present invention;

5a-5d are schematic waveform diagrams of a fourth PWM signal generation process provided by an embodiment of the present invention;

6a-6d are schematic waveform diagrams of a fifth PWM signal generation process provided by an embodiment of the present invention;

7a-7d are schematic waveform diagrams of a sixth PWM signal generation process provided by an embodiment of the present invention;

8a-8d are schematic waveform diagrams of a seventh PWM signal generation process provided by an embodiment of the present invention;

9a-9d are schematic waveform diagrams of an eighth PWM signal generation process provided by an embodiment of the present invention;

10a-10d are schematic waveform diagrams of a ninth PWM signal generation process provided by an embodiment of the present invention;

11a-11d are schematic waveform diagrams of a tenth PWM signal generation process provided by an embodiment of the present invention;

12a-12d are schematic waveform diagrams of an eleventh PWM signal generation process provided by an embodiment of the present invention;

13a-13d are schematic waveform diagrams of a twelfth PWM signal generation process provided by an embodiment of the present invention;

FIG. 14 is a schematic structural diagram of an apparatus for generating a PWM signal according to an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

The PWM signal generation method provided by the present invention is applied to electronic equipment. In the case of implementing a PWM signal generation device based on FPGA, it can be specifically applied to the main controller of the signal generation device. Of course, in practical applications, it can also be Applied to other controllers capable of controlling the PWM generation process. Referring to FIG. 1, FIG. 1 is a flowchart of a method for generating a PWM signal provided by an embodiment of the present invention. The flowchart of the method for generating a PWM signal provided by this embodiment may include:

S100. Control the clock device to output the first clock signal and the second clock signal.

In existing applications, the clock device can output a clock signal according to a preset signal period, and the corresponding duration can be determined by counting the clock signal. In the PWM signal generation method provided by the embodiment of the present invention, the clock device is controlled to output the first clock signal and the second clock signal. In practical applications, in order to simplify the counting process in the subsequent steps, the frequencies of the first clock signal and the second clock signal are the same , that is, the signal period is the same, and the phases of the first clock signal and the second clock signal are also the same before the phase adjustment of the second clock signal is performed.

It should be noted that the functions of the first clock signal and the second clock signal in the present invention are different, and the details will be described in detail in the subsequent content, and will not be described in detail here.

S110. Count the first clock signal and the second clock signal respectively according to a preset counting manner.

Optionally, the preset counting method mentioned in this embodiment may be any one of up counting, down counting, up and down counting, and down counting. Selection of application requirements, the present invention does not limit the specific selection of the preset counting mode. As for the specific counting implementation process of various counting methods, it will be explained in the following content by way of specific examples, and will not be described in detail here.

S120: Control the phase adjustment device to adjust the phase of the second clock signal according to a preset phase difference during the counting process.

Combined with the basic knowledge of PWM signals, it can be seen that PWM signals are square wave signals that repeat according to a fixed period. The PWM signal of any period includes a high level for a certain period of time and a low level for a certain period of time. The signal generation process of each period is consistent. In this embodiment, the generation process of the PWM signal of the current cycle is introduced. As for the PWM signal of the subsequent cycle after the current cycle, the PWM signal generation method provided by the embodiment of the present invention can be repeatedly executed. and the counting process, that is, the counting process corresponding to the generation of the PWM signal of the current cycle.

It can be understood that if the phase of the clock signal is adjusted before starting counting, and the counting is started after the phase adjustment is completed, this has no effect on the counting process. Since the signal period of a single clock signal is not changed, the difference between the clock signal and the count value is The product does not change, that is, it does not change the corresponding statistical duration, but changing the phase of the clock signal during the counting process will cause the count value to change in advance or delay. Therefore, in the case of the same count value, the corresponding statistical duration is different, so as to realize the adjustment of the level width of the PWM signal.

The phase adjustment device in the existing application can achieve high-resolution phase adjustment. Generally, it can achieve a phase change of less than 100ps, which is far lower than the high-precision resolution requirement of 200ps in the existing application. Therefore, as long as the preset When the phase difference is smaller than the clock period of the second clock signal, a PWM signal adjustment higher than the resolution of the existing application can be realized.

Further, the requirements for the realization of high-precision PWM signals mainly include two aspects. One is the high-precision PWM signal edge, that is, the timing of high-low level flips and jumps in the PWM signal is adjusted more accurately and meticulously. In this case, the period of the PWM signal is unchanged, so it can also be understood as a more precise adjustment of the duty cycle of the PWM signal; the second is the high-precision PWM signal period adjustment. Based on the composition of the PWM signal, this In this case, it can be realized by adjusting the width of the high level of the PWM signal, or it can be realized by adjusting the width of the low level of the PWM signal. Currently, in the case of only periodic adjustment, the level of the PWM signal is required to be reversed. The time cannot be changed, that is to say, the process of period adjustment can only occur in the second half period of the PWM signal. Based on this, under different application requirements, the timing of performing phase adjustment on the second clock signal and the selection of the preset phase difference are also different. In order to distinguish, the present invention defines the preset phase difference during edge adjustment as For the first preset phase difference, correspondingly, the preset phase difference during period adjustment is defined as the second preset phase difference. Of course, whether it is the time length corresponding to the first preset phase difference or the second preset phase difference, All are less than the period length of the clock signal.

Based on the foregoing, for the application requirements of the high-precision PWM signal period, when the count value of the second clock signal is greater than or equal to the preset half-cycle count value and less than the preset full-cycle count value, the phase adjustment device should be controlled according to the second The preset phase difference adjusts the phase of the second clock signal, wherein the preset full cycle count value is the clock signal count value corresponding to the complete PWM signal.

For the application requirements of high-precision PWM signal edges, when the count value of the second clock signal is less than the preset half-cycle count value, the phase adjustment device should be controlled to adjust the phase of the second clock signal according to the first preset phase difference, wherein , the preset half-cycle count value is set based on the duty cycle of the PWM signal. As mentioned above, the signal count value corresponding to a complete PWM signal is the preset full-cycle count value, then the preset full-cycle count value and the duty cycle The product of the duty ratio, that is, the preset half-cycle count value. It can be seen from this that the preset half-cycle count value can also be understood as the count value of the clock signal corresponding to the level inversion of the PWM signal during the cycle.

In addition to the above two typical implementation requirements, it can also be required to adjust the edge and period of the PWM signal at the same time. In this case, it is necessary to integrate the above conditions to achieve, which will be developed in subsequent embodiments, which will not be detailed here. described.

S130. Control the signal generating device to output the PWM signal of the current cycle according to the count value of the second clock signal, or the count value of the first clock signal and the second clock signal.

As mentioned above, the realization requirements of high-precision PWM signal include two aspects: high-precision PWM signal edge and high-precision PWM signal period adjustment. Edge adjustment needs to be implemented by combining the count value of the first clock signal and the count value of the second clock signal. Of course, in practical applications, it may also be necessary to adjust the edge and period of the PWM signal at the same time, and the present invention can also complete this adjustment process.

It should be noted that the counting of the clock signal and the level output of the PWM signal are performed simultaneously, that is, when the clock signal starts to be counted, the signal generating device synchronously outputs the first level of the PWM signal, and in the subsequent counting process , according to the specific counting situation, the first level is switched to the second level, or the generation of the PWM signal of the current cycle is ended, and the output of the PWM signal of the next cycle is further started. Therefore, the control signal generating device according to the specific count value mentioned in this step to output the PWM signal actually runs through the entire PWM signal generating process.

It can be understood that the first level mentioned in the foregoing content may be a high level or a low level. Correspondingly, in the case where the first level is a high level, the second level is Low level, when the first level is a low level, the second level is a high level.

To sum up, in the PWM signal generation method provided by the embodiment of the present invention, the phase of the second clock signal is adjusted during the counting process. Since the phase of the second clock signal changes, when the same count value is used, The corresponding signal width changes, and further because the preset phase difference is smaller than the clock period, the change in the signal width is correspondingly smaller than the clock period, that is, a PWM signal with a resolution smaller than the clock period and higher precision is realized.

Further, through the selection of the phase adjustment timing, at least one of edge adjustment and period adjustment can be specifically implemented, which fully meets practical application requirements.

The following describes the process of applying the PWM signal generating method provided by the present invention to output the PWM signal with reference to the specific waveform diagrams. It should be noted in advance that, as mentioned above, there are many ways to count the clock signal, and there are different types of PWM signals. In addition, the various high-precision adjustment requirements of PWM signals can be combined in various specific implementations. , and the subsequent content summarizes similar types of adjustment processes and focuses on them. Among them, the first type of PWM signal refers to outputting a low level in the first half cycle, and outputting a high level in the second half cycle; correspondingly, the second type of PWM signal refers to outputting a high level in the first half cycle and outputting a low level in the second half cycle. flat.

In the following embodiments, clk1 represents the first clock signal, clk2 represents the second clock signal; counter represents the count value of the clock signal. The count of the second clock signal will be specifically described with respect to specific embodiments; both PWM_1 and PWM_1' are reference waveform diagrams given to facilitate the understanding of the scheme, not the waveform diagram of the actual output PWM signal, only the corresponding waveforms under the word Final output The waveform represents the actual output PWM signal.

Based on the above description, referring to FIG. 2a, FIG. 2a shows a generation process of a first type PWM signal that adopts incremental counting and realizes high-precision edge adjustment.

As shown in FIG. 2 , while the clock device is controlled to output the first clock signal and the second clock signal simultaneously, the number of the clock signals is counted by means of incremental counting. It can be understood that, when the frequencies of the first clock signal and the second clock signal are the same, since the first preset phase difference is smaller than the clock period of the second clock signal, the preset half-cycle count value corresponding to the first clock signal and The preset half-cycle count value corresponding to the second clock signal is actually the same, but the time when the two actually reach the preset half-cycle count value will be different. Of course, this is also the method of the present invention to achieve high-precision signal edge adjustment The essential. Therefore, the counter in FIG. 2 can represent the counting requirements of the first clock signal and the second clock signal at the same time, wherein N represents the preset half-cycle count value, and pe and 0 respectively represent the preset full-cycle count value under different circumstances. It can be understood that in the case of counting up the clock signal, pe represents the preset full cycle count value, on the contrary, in the case of counting down the clock signal, 0 represents the preset full cycle count value.

During the high-precision PWM signal edge adjustment process, the signal generating device is controlled to stop the output of the PWM signal of the current cycle according to the count value of the first clock signal, that is, the total pulses of the PWM signal of the current cycle are determined according to the count value of the first clock signal The width (including the width of the high level and the width of the low level), and at the same time, the timing of level switching in the current cycle is determined according to the count value of the second clock signal.

As shown in FIG. 2a, before the count value of the second clock signal reaches the preset half-cycle count value N, the control signal generating device outputs the first level of the PWM signal of the current cycle, that is, the low level, and at the second clock When the count value of the signal reaches the preset half-cycle count value N, the phase of the second clock signal is controlled to be shifted backward by the first preset phase difference T _PS1 . Due to the backward shift of the phase of the clock signal, the time when the count value reaches the preset half-cycle count value is shifted backward, so that the corresponding duration of the first level becomes longer, and the level width changes from _TL before the phase shift to the final output _{Of course} , since the phase of the first clock signal is not adjusted, it will not have any effect on the total width of the PWM signal in the current cycle.

When the count value of the second clock signal is equal to the preset half-cycle count value, it indicates that the expected width of the first level has been reached, and the control signal generating device switches the first level to the second level of the PWM signal of the current cycle, That is, the high level shown in Figure 2a is output. Further, when the count value of the second clock signal is greater than or equal to the preset half-cycle count value and the count value of the first clock signal is less than the preset full-cycle count value, the control signal generating device maintains the output of the second level, that is, A high-level continuous output is achieved.

Finally, when the count value of the first clock signal reaches the preset full cycle count value, the control signal generating device stops outputting the second level. 2 and the foregoing content, in this embodiment, the period of the PWM signal of the current cycle is controlled by the count value of the first clock signal. Since the first clock signal is not phase-shifted, the period of the final output PWM signal does not change. However, compared with the reference PWM waveform shown in PWM_1 in Figure 2, the width of the high level of the final output PWM signal is reduced to T _H -T _PS1 , and the edge timing of the inversion of the transmission level of the PWM signal is adjusted. _Compared with the edge adjustment in which the minimum change of one clock cycle is performed in the prior art, the resolution is obviously smaller and the precision of the edge adjustment is higher.

For the specific adjustment process of FIG. 2b-FIG. 2d, please refer to the above-mentioned FIG. 2a for implementation, and will not be expanded here. Wherein, Fig. 2b shows the process of performing edge forwarding on the PWM signal of the first type, Fig. 2c shows the process of performing edge-backward shifting on the PWM signal of the second type, and Fig. 2d shows the process of performing the edge shifting on the PWM signal of the second type The process of moving the edge forward.

Optionally, referring to Fig. 3a-Fig. 3d , a process of implementing high-precision PWM edge adjustment in a down-counting manner is shown.

The period control of the PWM signal is completed by the first clock signal by means of down counting, and the level of the PWM signal is controlled to be inverted when the count of the second clock signal is the preset half-cycle count value N. For Fig. 3a and Fig. 3b, before time N, it is assumed that the second clock signal has been phase-shifted forward or backward T _PS1 according to the high-precision pulse width T _PS1 to be realized, then the equivalent current cycle of the PWM signal The width of the high or low level of is adjusted to ( _TH / _TL ±T _PS1 ).

For Figure 3c and Figure 3d, before time 1, it is assumed that the second clock signal has been phase-shifted forward or backward TPS2 according to the high-precision pulse width TPS2 to be achieved, then the equivalent PWM signal is high or low level width is adjusted to (TH/TL±TPS2). The first type means that when the counter is greater than N, a high level is output, and the second type means that when the counter is greater than N, a low level is output.

Optionally, FIGS. 4 a to 4 d illustrate the process of outputting the PWM signal by adopting an increment and decrement count, that is, a counting manner in which the PWM signal is outputted firstly and then decremented. Similar to the previous embodiment, the first clock signal is used to complete the full cycle of the PWM signal by increasing and decreasing the counting method, that is, the counting of the preset full cycle count value, and the second clock signal is used to complete the counting of level inversions in the PWM signal cycle, The PWM signal level inversion is performed when the up-count is the preset half-cycle count value N, and correspondingly, the PWM signal level is inverted when the down-count is the preset half-cycle count value N.

Before the count-up is N, it is assumed that the second clock signal has been phase-shifted forward or backward T _PS1 according to the high-precision pulse width T _PS1 to be realized, then the high or low level width of the equivalent PWM signal is adjusted is ( _TH / _TL ±T _PS1 ).

Before the countdown is N, it is assumed that the second clock signal has been phase-shifted forward or backward T _PS2 according to the high-precision pulse width T _PS2 to be realized, then the equivalent PWM signal high or low level width is adjusted to (T _H / _TL ±T _PS2 ). The first type means that when the counter is greater than N, a high level is output, and the second type means that when the counter is greater than N, a low level is output.

Optionally, FIGS. 5 a to 5 d illustrate the process of outputting the PWM signal by adopting the counting down and up counting, that is, in the counting manner of first decreasing and then increasing. Similar to the previous embodiment, the first clock signal is used to complete the full cycle of the PWM signal by counting down, that is, the counting of the preset full cycle count value, and the second clock signal is used to complete the counting of level inversions in the PWM signal cycle, The PWM signal level inversion is performed when the countdown is the preset half-cycle count value N, and correspondingly, the PWM signal level is inverted when the count-up is the preset half-cycle count value N.

Before the countdown is N, it is assumed that the second clock signal has been phase-shifted forward or backward T _PS1 according to the high-precision pulse width T _PS1 to be realized, then the high or low level width of the equivalent PWM signal is adjusted is ( _TH / _TL ±T _PS1 ).

Before the count-up is N time, it is assumed that the second clock signal has been phase-shifted forward or backward T _PS2 according to the high-precision pulse width T _PS2 to be realized, then the equivalent PWM signal high or low level width is adjusted to (T _H / _TL ±T _PS2 ). The first type means that when the counter is greater than N, a high level is output, and the second type means that when the counter is greater than N, a low level is output.

Optionally, each of the above-mentioned embodiments of FIG. 2 to FIG. 5 respectively shows the implementation process of performing high-precision adjustment of the edge of the PWM signal. For any embodiment, when the count value of the first clock signal is equal to the preset full cycle count value, The count value of the first clock signal and the count value of the second clock signal can be cleared to further output the PWM signal of the next cycle.

The following is an introduction to the high-precision adjustment process of the PWM signal period:

Referring to Figures 6a-6d, as mentioned above, the PWM_1 shown in any waveform diagram is not the actual output PWM signal, and PWM_1' is the actual output PWM signal. By comparing PWM_1 and PWM_1', it can be clearly shown that The period change of the output PWM signal. In this embodiment, counter represents a counting method for the second clock signal. It should be noted that, since the process of adjusting the period of the PWM signal can be implemented solely by relying on the second clock signal, in order to reduce the overall energy consumption, the clock device may be controlled to output only the second clock signal. Of course, from the perspective of simplifying the control logic, the difference may not be distinguished, and the first clock signal and the second clock signal are simultaneously output according to the foregoing content, and both are counted at the same time.

Taking Fig. 6a as an example, when the clock device is controlled to output the second clock signal, the number of clock signals is counted by means of incremental counting, and the signal generating device is controlled to perform the PWM signal generation of the current cycle according to the count value of the second clock signal. Level switching, and, stop the output of the PWM signal of the current cycle.

Specifically, as shown in FIG. 6a, before the count value of the second clock signal reaches the preset half-cycle count value N, the control signal generating device outputs the first level of the PWM signal of the current cycle, that is, the low level; When the count value of the two clock signals is equal to the preset half-cycle count value N, the control signal generating device switches the first level to the second level of the PWM signal of the current cycle, that is, from low level to high level.

Further, when the count value of the second clock signal is greater than or equal to the preset half-cycle count value N and less than the preset full-cycle count value pe, the control signal generating device maintains outputting the second level, and maintains outputting the second level. In the process of leveling, the second clock signal is controlled to shift the phase backward, the distance is the second preset phase difference T _PS , and when the count value of the second clock signal reaches the preset full cycle count value, the control signal generation device Stop outputting the second level, and end the output of the PWM signal of the current cycle.

It can be understood that since the phase of the second clock signal moves backward, the duration corresponding to the count value of the second clock signal changes, which in turn changes relative to the period of PWM_1 shown in FIG. 6a , that is, the PWM signal is extended. period, and the variation of the period is the duration corresponding to T _PS . As mentioned above, since the second preset phase difference is smaller than the signal period of the second clock signal, the PWM signal period adjustment smaller than the clock signal period is realized.

Further, when the count value of the second clock signal reaches the preset full cycle count value, the output of the PWM signal of the current cycle is completed, and the count value of the second clock signal can be cleared to output the PWM signal of the next cycle. signal ready.

For the specific adjustment process in FIGS. 6b to 6d, it can be realized by referring to the above-mentioned FIG. 6a, and will not be expanded here. 6b shows the process of extending the period of the PWM signal of the second type, FIG. 6c shows the process of shortening the period of the PWM signal of the first type, and FIG. 6d shows the process of shortening the period of the PWM signal of the second type the process of. Among them, T _PR represents the period of the PWM signal before the period adjustment is performed, and T _PR ±T _PS represents the period of the PWM signal after the period adjustment is performed.

Optionally, based on the above content, referring to FIGS. 7 a to 7 d , a process of implementing high-precision PWM period adjustment in a down-counting manner is shown.

The counting of the PWM signal period adjustment process is completed by counting down. When the count value of the second clock signal reaches the preset half-cycle count value N, the PWM signal is controlled to perform level inversion, and when the count value is reduced to 0, the control The signal generating device stops outputting the second level to realize period adjustment of the PWM signal of the current period. When the next cycle starts, that is, when the count is pe, the next PWM signal starts to be output. By shifting the phase of the second clock signal forward or backward by T _PS , the equivalent PWM signal period achieves a highly accurate period adjustment (T _PR ±T _PS ). The first type means that when the counter is greater than or equal to N, it outputs a high level, and the second type means that when the counter is greater than or equal to N, it outputs a low level.

Optionally, referring to FIGS. 8 a to 8 d , a process of realizing high-precision PWM signal period adjustment by means of counting up and down is shown.

The high-precision adjustment of the PWM signal cycle is accomplished by counting up and down. As shown in the figure, the PWM signal flips to high/low level when the up-count is N, and the PWM signal flips to low/high when the down-count is N. level, at any time other than 0 in the entire counting cycle, the FPGA internal clock is phase-shifted forward or backward by T _PS , then the equivalent PWM signal cycle achieves high-precision period adjustment (T _PR ±T _PS ) . The first type means that when the counter is greater than N, a high level is output, and the second type means that when the counter is greater than N, a low level is output.

Optionally, referring to Fig. 9a-Fig. 9d , a process of realizing high-precision PWM signal period adjustment in the manner of counting down and up is shown.

The high-precision adjustment of the PWM signal cycle is accomplished by down-counting. As shown in the figure, the PWM signal flips to high/low level when the down-count is N, and the PWM signal flips to low/high when the up-count is N. level, at any time other than 0 in the entire counting cycle, the FPGA internal clock is phase-shifted forward or backward by T _PS , then the equivalent PWM signal cycle achieves high-precision period adjustment (T _PR ±T _PS ) . The first type means that when the counter is greater than N, a high level is output, and the second type means that when the counter is greater than N, a low level is output.

Further, the embodiment of the present invention also provides a signal generation method capable of adjusting the edge and period of the PWM signal at the same time.

Based on the foregoing, it can be seen that when performing edge adjustment of the PWM signal, it is necessary to adjust the phase of the second clock signal in the first half cycle corresponding to the PWM signal, and rely on the count value of the first clock signal to ensure that the period of the PWM signal does not change, Correspondingly, if the edge and period adjustments are performed at the same time, the first clock signal is no longer needed to ensure that the period of the PWM signal remains unchanged. Therefore, the edge and period adjustments of the PWM signal are performed at the same time, only relying on the second clock signal. Can.

As mentioned above, the edge adjustment must be completed in the first half cycle of the PWM signal, that is, when the count value of the second clock signal is less than the preset half cycle count value, that is, the PWM signal of the current cycle is at the first level. The phase adjustment device is controlled to adjust the phase of the second clock signal according to the third preset phase difference. Of course, the third preset phase difference is already smaller than the signal period of the second clock signal.

Through the above adjustment, the duration of the second clock signal count value reaching the preset half-cycle count value can be changed, thereby realizing high-precision adjustment of the PWM signal edge.

When the count value of the second clock signal reaches the preset half-cycle count value, the control signal generating device switches the level of the PWM signal, that is, from the first level to the second level.

When the count value of the second clock signal is greater than or equal to the preset half-cycle count value and less than the full-cycle count value, the control signal generating device maintains outputting the second level, and when the count value of the second clock signal reaches the preset full cycle count value In the case of the period count value, the control signal generation device stops outputting the second level, and completes the simultaneous adjustment of the edge and the period of the PWM signal.

Based on the above content, referring to FIGS. 10a-10d, the first clock signal is used to illustrate the generation process of the reference waveform of the PWM signal before adjustment by counting up, and the PWM signal is turned to high/low level when the count is N , when the count reaches the preset full-cycle count value, stop outputting the PWM signal of the current cycle, and the obtained PWM signal of the current cycle has a high level width _TH and a low level width _TL . Based on the description of the aforementioned phase-shifting moment, the second clock signal is phase-shifted forward or backward by T _PS , so that the period of the equivalent PWM signal can be adjusted with high precision (T _PR ±T _PS ).

Before reaching the preset full-cycle count value, assuming that the second clock signal has been phase-shifted forward or backward T _PS1 according to the high-precision pulse width T _PS1 to be achieved, the equivalent PWM signal is high or low level width is adjusted to (T _H / _TL ±T _PS1 (±T _PS )), at the beginning of the next cycle, the second clock signal is shifted right by T _c -T _ps1 to restore alignment with the first clock signal (of course, it can also be controlled by The clock device re-outputs the first clock signal and the second clock signal), and T _c is the period of the first clock clk1.

Before the count value of the second clock signal reaches the preset half-cycle count value, it is assumed that the second clock signal has been phase-shifted forward or backward T _PS2 according to the high-precision pulse width T _PS2 to be realized, then the equivalent PWM The signal high or low level width is adjusted to (T _H / _TL ±T _PS2 (±T _PS )), at the beginning of a new cycle, the second clock signal is shifted to the right by T _c -T _ps2 to restore the first clock signal alignment. The change of the duty cycle here needs to consider the influence of T _PS during the period adjustment process. Adjust the size of T _PS1 and T _PS2 according to this value to achieve the final PWM signal edge adjustment effect. The first type represents that when the counter is greater than N, the output High level, the second type means that when the counter is greater than N, the output is low level.

Optionally, referring to FIGS. 11 a to 11 d , the first clock signal is used to show the generation process of the reference waveform of the PWM signal before adjustment by counting down, and the PWM signal is turned to high/low level when the count is N. , when the count reaches the preset full-cycle count value, stop outputting the PWM signal of the current cycle, and the obtained PWM signal of the current cycle has a high level width _TH and a low level width _TL . Based on the description of the aforementioned phase-shifting moment, the second clock signal is phase-shifted forward or backward by T _PS , so that the period of the equivalent PWM signal realizes a high-precision period adjustment (T _PR ±T _PS ).

Before reaching the preset full-cycle count value, assuming that the second clock signal has been phase-shifted forward or backward T _PS1 according to the high-precision pulse width T _PS1 to be achieved, the equivalent PWM signal is high or low level width is adjusted to (T _H /T _L ±T _PS1 (±T _PS )), at the beginning of a new cycle, the second clock signal is shifted to the right by T _c -T _ps1 to restore alignment with the first clock signal, and T _c is the first clock signal. One cycle of clock clk1.

Before reaching the preset half-cycle count value, it is assumed that the second clock signal has been phase-shifted forward or backward T _PS2 according to the high-precision pulse width T _PS2 to be realized, then the equivalent PWM signal high or low level width is adjusted to ( _TH / _TL ±T _PS2 (±T _PS )), and at the beginning of the next cycle, the second clock signal is shifted right by T _c −T _ps2 to restore alignment with the first clock signal. Here, the change of high-level width and low-level width needs to consider the influence of T _PS during the period adjustment process, and adjust the size of T _PS1 and T _PS2 according to this value to achieve the final PWM signal edge adjustment effect. The first type represents when When the counter is greater than N, it outputs a high level. The second type represents that when the counter is greater than N, it outputs a low level.

Optionally, referring to FIGS. 12a to 12d , the first clock signal is used to show the generation process of the reference waveform of the PWM signal before adjustment by counting up first and then down. The width of the high level is _TH and the width of the low level is _TL . Based on the description of the aforementioned phase-shifting moment, the second clock signal is phase-shifted forward or backward by T _PS , so that the period of the equivalent PWM signal can be adjusted with high precision (T _PR ±T _PS ).

Before the countdown N time, it is assumed that the second clock signal has been phase-shifted forward or backward T _PS1 according to the high-precision pulse width T _PS1 to be realized, then the equivalent PWM signal high or low level width is adjusted to (T _H /T _L ±T _PS1 (±T _PS )), at the beginning of a new cycle, shift the second clock signal to the right by T _c -T _ps1 to restore alignment with the first clock signal, where T _c is the first clock Period of clk1.

Before counting up the time N, assuming that the second clock signal has been phase-shifted forward or backward T _PS2 according to the high-precision pulse width T _PS2 to be realized, the equivalent PWM signal high or low level width is adjusted to (T _H / _TL ±T _PS2 (±T _PS )), at the beginning of a new cycle, shift the second clock signal to the right by T _c -T _ps2 to restore alignment with the first clock signal, where T _c is the first clock Period of clk1. The change of the duty cycle here needs to consider the influence of T _PS during the period adjustment process. Adjust the size of T _PS1 and T _PS2 according to this value to achieve the final PWM signal edge adjustment effect. The first type represents that when the counter is greater than N, the output High level, the second type means that when the counter is greater than N, the output is low level.

Optionally, referring to FIGS. 13 a to 13 d , the first clock signal is used to show the generation process of the reference waveform of the PWM signal before adjustment by first counting down and then increasing the count. In the case of no adjustment, the PWM signal is The width of the high level is _TH and the width of the low level is _TL . Based on the description of the aforementioned phase-shifting moment, the second clock signal is phase-shifted forward or backward by T _PS , so that the period of the equivalent PWM signal can be adjusted with high precision (T _PR ±T _PS ).

Before the count-up is N, it is assumed that the second clock signal has been phase-shifted to the left or right T _PS1 according to the high-precision pulse width T _PS1 to be realized, then the high or low level width of the equivalent PWM signal is adjusted is (T _H /T _L ±T _PS1 (±T _PS )), at the beginning of the next cycle, the second clock signal is shifted to the right by T _c -T _ps2 to restore alignment with the first clock signal, and T _c is the first clock Period of clk1.

Before the countdown N time, it is assumed that the second clock signal has been shifted to the left or right T _PS2 according to the high-precision pulse width T _PS2 to be realized, the equivalent PWM signal high or low level width is adjusted to (T _H / _TL ±T _PS2 (±T _PS )), at the beginning of the next cycle, shift the second clock signal to the right by T _c -T _ps2 to restore alignment with the first clock signal, where T _c is the first clock clk1 cycle. The change of the duty cycle here needs to consider the influence of T _PS during the period adjustment process. Adjust the size of T _PS1 and T _PS2 according to this value to achieve the final PWM signal edge adjustment effect. The first type represents that when the counter is greater than N, the output High level, the second type means that when the counter is greater than N, the output is low level.

It should be noted that, in any of the above embodiments, the frequencies of the first clock signal and the second clock signal are the same, and the phases of the two are also the same before the phase shift of the second clock signal is performed. However, as an optional implementation manner, the frequencies of the first clock signal and the second clock signal may be different. For the same PWM signal expected to be output, it is only necessary to set the corresponding frequency for the first clock signal and the second clock signal respectively. Pre-designed values are sufficient.

Optionally, referring to FIG. 14 , FIG. 14 is a structural block diagram of a PWM signal generation device provided by an embodiment of the present invention. The PWM signal generation device provided by this embodiment includes: a clock device, a phase adjustment device, a signal generation device, and a main controller, which,

the first output end of the clock device is connected to the signal generating device;

The second output end of the clock device is connected to the signal generating device through the phase adjusting device;

The main controller is respectively connected with the clock device, the phase adjusting device and the signal generating device;

The main controller executes the PWM signal generating method provided by any one of the above embodiments.

The various embodiments of the present invention are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments may be referred to each other. As for the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant part can be referred to the description of the method.

The above descriptions are only preferred embodiments of the present invention, and do not limit the present invention in any form. Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art, without departing from the scope of the technical solution of the present invention, can make many possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above, or modify them into equivalents of equivalent changes. Example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solutions of the present invention still fall within the protection scope of the technical solutions of the present invention.

Claims (14)

1. a PWM signal generation method, is characterized in that, comprises: controlling the clock device to output the first clock signal and the second clock signal; respectively counting the first clock signal and the second clock signal according to a preset counting manner; Controlling the phase adjusting device to adjust the phase of the second clock signal according to a preset phase difference during the counting process; Wherein, the preset phase difference is less than the clock period of the second clock signal; According to the count value of the second clock signal, or the count value of the first clock signal and the second clock signal, the signal generating means is controlled to output the PWM signal of the current cycle. 2. The method for generating a PWM signal according to claim 1, wherein the controlling the phase adjustment device in the counting process to adjust the phase of the second clock signal according to a preset phase difference, comprising: In the case that the count value of the second clock signal is smaller than the preset half-cycle count value, controlling the phase adjustment device to adjust the phase of the second clock signal according to the first preset phase difference; Wherein, the preset half-cycle count value is set based on the duty cycle of the PWM signal. 3. The method for generating a PWM signal according to claim 2, wherein the process of controlling the signal generating device to output the PWM signal of the current cycle according to the count value of the first clock signal and the second clock signal comprises: Control the signal generating device to perform level switching of the PWM signal of the current cycle according to the count value of the second clock signal; The signal generating means is controlled to stop the output of the PWM signal of the current cycle according to the count value of the first clock signal. 4. The method for generating a PWM signal according to claim 3, wherein the controlling the signal generating device to perform the level switching of the PWM signal of the current cycle according to the count value of the second clock signal comprises: Before the count value of the second clock signal reaches the preset half-cycle count value, the control signal generating device outputs the first level of the PWM signal of the current cycle; When the count value of the second clock signal reaches the preset half-cycle count value, controlling the signal generating device to switch the first level to the second level of the PWM signal of the current cycle; When the count value of the second clock signal is greater than or equal to the preset half-cycle count value, and the count value of the first clock signal is less than the preset full-cycle count value, control the signal generating device to maintain the output the second level. 5. The method for generating a PWM signal according to claim 3, wherein the controlling the signal generating device to stop the output of the PWM signal of the current cycle according to the count value of the first clock signal comprises: When the count value of the first clock signal reaches a preset full cycle count value, the signal generating device is controlled to stop outputting the second level. 6 . The PWM signal generating method according to claim 5 , further comprising: when the count value of the first clock signal is equal to the preset full cycle count value, converting the count value of the first clock signal The count value and the count value of the second clock signal are cleared. 7. The method for generating a PWM signal according to claim 1, wherein the controlling the phase adjusting device to adjust the phase of the second clock signal according to a preset phase difference during the counting process, comprising: When the count value of the second clock signal is greater than or equal to the preset half-cycle count value and less than the preset full-cycle count value, control the phase adjustment device to adjust the phase of the second clock signal according to the second preset phase difference . 8. The method for generating a PWM signal according to claim 7, wherein the process of outputting the PWM signal of the current cycle according to the count value of the second clock signal comprises: Control the signal generating device to perform level switching of the PWM signal of the current cycle according to the count value of the second clock signal; The signal generating means is controlled to stop the output of the PWM signal of the current cycle according to the count value of the second clock signal. 9. The method for generating a PWM signal according to claim 8, wherein the controlling the signal generating device to perform the level switching of the PWM signal of the current cycle according to the count value of the second clock signal comprises: Before the count value of the second clock signal reaches the preset half-cycle count value, the control signal generating device outputs the first level of the PWM signal of the current cycle; When the count value of the second clock signal is equal to the preset half-cycle count value, controlling the signal generating device to switch the first level to the second level of the PWM signal of the current cycle; When the count value of the second clock signal is greater than or equal to the preset half-cycle count value and less than a preset full-cycle count value, the signal generating device is controlled to maintain outputting the second level. 10. The method for generating a PWM signal according to claim 8, wherein the controlling the signal generating device to stop the output of the PWM signal of the current cycle according to the count value of the second clock signal comprises: When the count value of the second clock signal reaches the preset full cycle count value, the signal generating device is controlled to stop outputting the second level. 11 . The method for generating a PWM signal according to claim 10 , further comprising: when the count value of the second clock signal reaches the preset full cycle count value, converting the second clock signal to the second clock signal. 12 . The count value of the signal is cleared. 12 . The PWM signal generating method according to claim 9 , wherein, in the process of controlling the signal generating device to output the first level of the PWM signal of the current cycle, the phase adjusting device is controlled according to the third preset phase. 13 . The difference adjusts the phase of the second clock signal. 13. The PWM signal generating method according to any one of claims 1-12, wherein the preset counting manner comprises one of up counting, down counting, up and down counting and down counting. 14. A PWM signal generating device, comprising: a clock device, a phase adjusting device, a signal generating device and a main controller, wherein, The first output end of the clock device is connected to the signal generating device; The second output end of the clock device is connected to the signal generating device via the phase adjusting device; The main controller is respectively connected with the clock device, the phase adjustment device and the signal generation device; The main controller executes the PWM signal generation method described in any one of claims 1-13.

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