CN114610391A - Data loading method and related device of RISC-V vector processor - Google Patents

Abstract

The present application discloses a data loading method for a RISC-V vector processor, comprising: executing a data preloading instruction to load target data from a first memory into a second memory; wherein the data preloading instruction and running in Ordinary instructions before the data load instruction run in parallel; the data load instruction is executed to load the target data from the second memory to the RISC-V vector processor. The method can improve the data processing speed of the RISC-V vector processor and improve the performance of the RISC-V vector processor. The present application also discloses a data loading device, device and computer-readable storage medium for a RISC-V vector processor, all of which have the above technical effects.

Description

A data loading method and related device of a RISC-V vector processor

technical field

The present application relates to the technical field of RISC-V vector processors, in particular to a data loading method of a RISC-V vector processor; and also relates to a data loading apparatus, device and computer-readable storage medium of a RISC-V vector processor.

Background technique

Different from traditional Intel processors and ARM processors, RISC-V, the fifth-generation reduced instruction processor, is a brand-new instruction set architecture, and open source can be used freely, with the advantage of being autonomous and controllable. Among them, RISC-V can support vector processing by extending the Vector instruction set, so that it can be used as a vector processor, that is, efficient computing can be achieved through the Vector instruction set extension, which can effectively deal with applications such as machine learning, computer vision, and multimedia. Wait.

As a vector processor, RISC-V needs to involve a large number of data access operations. Under the traditional data cache mechanism, when data needs to be loaded, the RISC-V vector processor must first determine whether the data to be loaded is in the Cache, if not. If it is not all there, first move the corresponding data from DDR to Cache, and then load it from Cache to RISC-V vector processor. Loading a large amount of data from DDR to Cache requires a lot of clock cycles, which will greatly affect the data processing speed of the RISC-V vector processor, thus seriously affecting the performance of the RISC-V vector processor.

Therefore, how to improve the data processing speed of the RISC-V vector processor and improve the performance of the RISC-V vector processor has become an urgent technical problem to be solved by those skilled in the art.

SUMMARY OF THE INVENTION

The purpose of this application is to provide a data loading method for a RISC-V vector processor, which can improve the data processing speed of the RISC-V vector processor and improve the performance of the RISC-V vector processor. Another object of the present application is to provide a data loading device, device and computer-readable storage medium for a RISC-V vector processor, all of which have the above technical effects.

In order to solve the above technical problems, the present application provides a data loading method for a RISC-V vector processor, including:

Execute the data preloading instruction to load the target data from the first memory into the second memory; wherein, the data preloading instruction and the ordinary instruction running before the data loading instruction are run in parallel;

The data load instruction is executed to load the target data from the second memory to the RISC-V vector processor.

Optionally, the executing the data preloading instruction to load the target data from the first memory into the second memory includes:

querying the second memory according to the data preload instruction;

If the second memory misses the target data, loading the target data from the first memory to the second memory;

If the second memory hits the partial data of the target data, loading the partial data of the target data that the second memory misses into the second memory from the first memory;

If the second memory hits the target data, the target data is not loaded from the first memory into the second memory.

Optionally, the loading of the target data from the second memory to the RISC-V vector processor includes:

Loading the target data from the second memory into the target register group specified by the data loading instruction in the RISC-V vector processor.

Optionally, executing a data load instruction to load the target data from the second memory to the RISC-V vector processor includes:

query the second memory according to the data loading instruction;

If the second memory misses the target data, after loading the target data from the first memory to the second memory, load the target data from the second memory to RISC-V vector processor;

If the second memory hits the partial data of the target data, after the partial data of the target data that the second memory misses is loaded from the first memory into the second memory, all the data are loaded into the second memory. The target data is loaded into the RISC-V vector processor from the second memory;

If the second memory hits the target data, the target data is loaded from the second memory to the RISC-V vector processor.

Optionally, before executing the data preloading instruction, it further includes:

The data preload instruction is loaded from the third memory to the RISC-V vector processor.

Optionally, before executing the data loading instruction, it further includes:

The data load instruction is loaded from the third memory to the RISC-V vector processor.

In order to solve the above technical problems, the present application also provides a data loading device for a RISC-V vector processor, including:

The first instruction execution module is used to execute the data preloading instruction, and load the target data from the first memory into the second memory; wherein, the data preloading instruction and the ordinary instruction running before the data loading instruction are run in parallel;

The second instruction execution module is configured to execute the data loading instruction to load the target data from the second memory to the RISC-V vector processor.

Optionally, the first instruction execution module includes:

a first query unit, configured to query the second memory according to the data preloading instruction;

a first loading unit, configured to load the target data from the first memory to the second memory if the second memory misses the target data; if the second memory hits the target If the second memory misses the partial data of the target data, load the partial data of the target data from the first memory into the second memory; if the second memory hits the target data, then The target data is not loaded from the first memory into the second memory.

In order to solve the above technical problems, the present application also provides a data loading device for a RISC-V vector processor, including:

memory for storing computer programs;

The processor is configured to implement the steps of the data loading method of the RISC-V vector processor described in any one of the above when executing the computer program.

In order to solve the above technical problems, the present application also provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the RISC described in any one of the above is implemented. -V Steps of the vector processor's data loading method.

The data loading method for a RISC-V vector processor provided by the present application includes: executing a data preloading instruction, and loading target data from a first memory into a second memory; wherein the data preloading instruction and running on the data Ordinary instructions before the load instruction are run in parallel; the data load instruction is executed to load the target data from the second memory to the RISC-V vector processor.

It can be seen that the data loading method of the RISC-V vector processor provided by this application adds a data preloading instruction on the basis of the traditional data loading instruction, and the data preloading instruction is the same as the ordinary instruction that runs before the data loading instruction. run in parallel. Before executing the data loading instruction, by executing the data preloading instruction, data can be loaded from the first memory into the second memory in advance without affecting the operation of other instructions before the data loading instruction. When the data loading instruction is executed, the time for loading data from the first memory to the second memory can be reduced or even avoided, thereby improving the data processing speed of the RISC-V vector processor and improving the performance of the RISC-V vector processor.

The data loading apparatus, device, and computer-readable storage medium of the RISC-V vector processor provided by the present application all have the above technical effects.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the prior art and the drawings required in the embodiments. Obviously, the drawings in the following description are only some of the drawings in the present application. In the embodiments, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without any creative effort.

1 is a schematic flowchart of a data loading method for a RISC-V vector processor provided by an embodiment of the present application;

FIG. 2 is a schematic diagram of a data loading process provided by an embodiment of the present application;

3 is a schematic diagram of another data loading process provided by an embodiment of the present application;

4 is a schematic diagram of a data loading device of a RISC-V vector processor provided by an embodiment of the present application;

FIG. 5 is a schematic diagram of a data loading device of a RISC-V vector processor according to an embodiment of the present application.

Detailed ways

The core of the present application is to provide a data loading method for a RISC-V vector processor, which can improve the data processing speed of the RISC-V vector processor and improve the performance of the RISC-V vector processor. Another core of the present application is to provide a data loading apparatus, device and computer-readable storage medium for a RISC-V vector processor, all of which have the above technical effects.

In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments It is a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

Please refer to FIG. 1. FIG. 1 is a schematic flowchart of a data loading method for a RISC-V vector processor provided by an embodiment of the application. Referring to FIG. 1, the method mainly includes:

S101: Execute a data preloading instruction to load target data from a first memory into a second memory; wherein, the data preloading instruction is run in parallel with a common instruction that runs before the data loading instruction;

Based on the open-source and easy-to-modify features of the RISC-V vector processor, the embodiments of the present application add data preloading instructions by modifying the compiler. Data preload instructions are executed before data load instructions. The data preload instruction has the same load source address, load length, and load width as the data load instruction. Load length and load width determine the amount of data to be loaded. Load refers to reading data from memory. Executing the data preload instruction only needs to load the data from the first memory (DDR) into the second memory (data cache), therefore, the data preload instruction does not include the destination register set.

Importantly, in this embodiment of the present application, the data preloading instruction and the common instructions other than the vector store instruction that are executed before the data loading instruction may be executed in parallel. During the time between the data preload instruction and the data load instruction, the RISC-V vector processor will not access the second memory (except for the vector store instruction), and the ordinary instructions running before the data load instruction will not be loaded from the second memory during this period. The second memory is loaded with data, but the data is read from general-purpose registers. Therefore, the execution process of the data preloading instruction does not affect the execution of the ordinary instruction, and can be executed in parallel with the ordinary instruction.

In some embodiments, executing a data preload instruction to load target data from the first memory into the second memory may include:

querying the second memory according to the data preload instruction;

If the second memory misses the target data, loading the target data from the first memory to the second memory;

If the second memory hits the partial data of the target data, loading the partial data of the target data that the second memory misses into the second memory from the first memory;

If the second memory hits the target data, the target data is not loaded from the first memory into the second memory.

Referring to FIG. 2, in FIG. 2, the full name of IF is Instruction Fench, which refers to reading the instruction from the memory. Before executing the data preload instruction, the data preload instruction is first loaded into the RISC-V vector processor from the third memory (instruction cache). The full name of ID is Instruction Decode, which refers to the translation of the instruction fetched from the memory. After decoding, the operand register index required by the instruction is obtained. This index can be used to read the operand from the general register group. The full name of EX is Instruction Execute, which refers to the process of performing real operations on instructions. For example, if the instruction is an addition instruction, the operand is added, and if it is a multiply instruction, the operand is subtracted.

MEM stands for Memory Access. Memory access instructions are often one of the most important types of instructions in the instruction set. Memory access refers to the process in which memory access instructions read data from or write to memory.

MMU refers to the memory management unit inside the RISC-V processor.

The full name of TLB is Translation Lookaside Buffer. When the MMU needs to translate the virtual address, it first looks up from the TLB, and if it hits, it returns the physical address directly. If there is a miss, the MMU looks in the page table.

The full name of WB is Write-Back, which refers to writing the execution result of the instruction back to the general-purpose register group.

In order to implement the data preloading instruction to load the data from the first memory to the second memory in advance, for the ID module, that is, the decoding module, it is necessary to add the identification and judgment of the data preloading instruction (specifically, it can be determined according to the instruction fields such as Opcode). identification and judgment), so that the ID module can identify that the current instruction is a data preload instruction. For the MEM module, it is also necessary to add the identification and judgment of the data preloading instruction. The MEM module determines the address and data amount to be loaded according to the Load source address, Load length, and Load width in the data preloading instruction.

The address sent by the MEM module is a virtual address, and it is necessary to query the TLB through the MMU to obtain the corresponding physical address. Wherein, if the TLB hits, that is, the corresponding physical address exists in the TLB, the physical address is directly obtained. If the TLB misses, that is, the corresponding physical address does not exist in the TLB, a page table lookup is performed to obtain the physical address.

On the basis of obtaining the obtained physical address, the second memory is further inquired according to the physical address. For the data that is not hit by the second memory, it is further read from the first memory, and the read data is returned to the second memory. Conversely, if the second memory is all hit, no further reads from the first memory are required.

S102: Execute the data load instruction to load the target data from the second memory to the RISC-V vector processor.

In addition to the load source address, the load length and the load width, the data load instruction also has a destination register group. Thus, in some embodiments, loading the target data from the second memory to the RISC-V vector processor comprises: loading the target data from the second memory to the RISC-V vector processor in the destination register bank specified by the data load instruction described in .

Additionally, in some embodiments, executing a data load instruction to load the target data from the second memory to the RISC-V vector processor includes:

query the second memory according to the data loading instruction;

If the second memory misses the target data, after loading the target data from the first memory to the second memory, load the target data from the second memory to RISC-V vector processor;

If the second memory hits the partial data of the target data, after the partial data of the target data that the second memory misses is loaded from the first memory into the second memory, all the data are loaded into the second memory. The target data is loaded into the RISC-V vector processor from the second memory;

If the second memory hits the target data, the target data is loaded from the second memory to the RISC-V vector processor.

Referring to FIG. 3 , the meanings of abbreviations such as IF, ID, and EX in FIG. 3 can be referred to the explanations for FIG. 2 above, which will not be repeated here. Before executing the data preload instruction, the data preload instruction is first loaded into the RISC-V vector processor from the third memory, that is, the I-cache shown in FIG. 3 . The MEM module determines the address and data volume to be loaded according to the Load source address, Load length, and Load width in the data load instruction. The address sent by the MEM module is a virtual address, and it is necessary to query the TLB through the MMU to obtain the corresponding physical address. If the TLB hits, that is, the corresponding physical address exists in the TLB, the physical address is directly obtained. If the TLB misses, that is, the corresponding physical address does not exist in the TLB, a page table lookup is performed to obtain the physical address.

On the basis of obtaining the obtained physical address, the second memory, that is, the D-cache shown in FIG. 3 , is further queried according to the physical address. If the second memory misses the target data, that is, the target data does not exist in the second memory, the target data is first loaded from the first memory to the second memory, and then the target data is loaded from the second memory. The second memory is loaded into the RISC-V vector processor. If the second memory hits the partial data of the target data, that is, the partial data of the target data exists in the second memory, the partial data of the target data that does not exist in the second memory may first be removed from the second memory. After the first memory is loaded into the second memory, the target data is loaded into the RISC-V vector processor from the second memory.

If the second memory hits the target data, that is, all data of the target data exists in the second memory, the target data is directly loaded from the second memory to the RISC-V vector processor.

Ideally, after the data preload instruction is executed, when the data load instruction is executed and the second memory is queried, all the data of the target data will be hit by the second memory, which can avoid loading data from the first memory when the data load instruction is executed. time to the second memory. Even if there is a short interval between the data preloading instruction and the data loading instruction, the target data cannot be fully loaded into the second memory, since a part of the data has been loaded from the first memory to the second memory, it will be Reduce the time to load data from the first memory to the second memory when executing the data load instruction.

To sum up, the data loading method of the RISC-V vector processor provided by this application includes: executing a data preloading instruction to load target data from the first memory into the second memory; wherein, the data preloading The instruction runs in parallel with the common instruction running before the data load instruction; the data load instruction is executed to load the target data from the second memory to the RISC-V vector processor. It can be seen that the data loading method of the RISC-V vector processor provided by this application adds a data preloading instruction on the basis of the traditional data loading instruction, and the data preloading instruction is the same as the ordinary instruction that runs before the data loading instruction. run in parallel. Before executing the data loading instruction, by executing the data preloading instruction, data can be loaded from the first memory into the second memory in advance without affecting the operation of other instructions before the data loading instruction. When the data loading instruction is executed, the time for loading data from the first memory to the second memory can be reduced or even avoided, thereby improving the data processing speed of the RISC-V vector processor and improving the performance of the RISC-V vector processor.

The present application also provides a data loading device for a RISC-V vector processor, and the device described below can be referred to in correspondence with the method described above. Please refer to FIG. 4. FIG. 4 is a schematic diagram of a data loading apparatus for a RISC-V vector processor provided by an embodiment of the application. In conjunction with FIG. 4, the apparatus includes:

The first instruction execution module 10 is used to execute the data preloading instruction, and load the target data from the first memory into the second memory; wherein, the data preloading instruction and the ordinary instruction running before the data loading instruction are run in parallel;

The second instruction execution module 20 is configured to execute the data loading instruction to load the target data from the second memory to the RISC-V vector processor.

On the basis of the foregoing embodiment, optionally, the first instruction execution module 10 includes:

a first query unit, configured to query the second memory according to the data preloading instruction;

a first loading unit, configured to load the target data from the first memory to the second memory if the second memory misses the target data; if the second memory hits the target If the second memory misses the partial data of the target data, load the partial data of the target data from the first memory into the second memory; if the second memory hits the target data, then The target data is not loaded from the first memory into the second memory.

On the basis of the foregoing embodiment, optionally, the second instruction execution module 20 is configured to load the target data from the second memory into the RISC-V vector processor specified by the data load instruction in the destination register bank.

On the basis of the foregoing embodiment, optionally, the second instruction execution module 20 includes:

a second query unit, configured to query the second memory according to the data loading instruction;

A second loading unit, configured to load the target data from the first memory into the second memory if the second memory misses the target data, and then load the target data from the first memory into the second memory. The second memory is loaded into the RISC-V vector processor; if the second memory hits the partial data of the target data, the partial data of the target data that the second memory misses is loaded from the first memory After entering the second memory, load the target data from the second memory to the RISC-V vector processor; if the second memory hits the target data, load the target data from the second memory. The second memory is loaded into the RISC-V vector processor.

On the basis of the above-mentioned embodiment, optional, also includes:

A first instruction loading unit, configured to load the data preloading instruction from the third memory to the RISC-V vector processor.

On the basis of the above-mentioned embodiment, optional, also includes:

A second instruction loading unit, configured to load the data loading instruction from the third memory to the RISC-V vector processor.

The data loading device of the RISC-V vector processor provided by the present application adds a data preloading instruction on the basis of the traditional data loading instruction, and the data preloading instruction runs in parallel with the ordinary instruction running before the data loading instruction . Before executing the data loading instruction, by executing the data preloading instruction, data can be loaded from the first memory into the second memory in advance without affecting the operation of other instructions before the data loading instruction. When the data loading instruction is executed, the time for loading data from the first memory to the second memory can be reduced or even avoided, thereby improving the data processing speed of the RISC-V vector processor and improving the performance of the RISC-V vector processor.

The present application also provides a data loading device for a RISC-V vector processor. Referring to FIG. 5 , the device includes a memory 1 and a processor 2 .

Memory 1, used to store computer programs;

The processor 2 is used for executing the computer program to realize the following steps:

Execute the data preloading instruction to load the target data from the first memory into the second memory; wherein, the data preloading instruction is run in parallel with the ordinary instruction running before the data loading instruction; The target data is loaded into the RISC-V vector processor from the second memory.

For the introduction of the equipment provided in the present application, please refer to the above method embodiments, which will not be repeated in this application.

The present application also provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the following steps can be implemented:

Execute the data preloading instruction to load the target data from the first memory into the second memory; wherein, the data preloading instruction is run in parallel with the ordinary instruction running before the data loading instruction; The target data is loaded into the RISC-V vector processor from the second memory.

The computer-readable storage medium may include: a USB flash drive, a removable hard disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, etc., which can store program codes. medium.

For the introduction of the computer-readable storage medium provided by the present application, please refer to the above method embodiments, which will not be repeated in the present application.

The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments can be referred to each other. For the apparatuses, devices, and computer-readable storage media disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and reference may be made to the descriptions of the methods for related parts.

Professionals may further realize that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two, in order to clearly illustrate the possibilities of hardware and software. Interchangeability, the above description has generally described the components and steps of each example in terms of function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each particular application, but such implementations should not be considered beyond the scope of this application.

The steps of a method or algorithm described in conjunction with the embodiments disclosed herein may be directly implemented in hardware, a software module executed by a processor, or a combination of the two. A software module can be placed in random access memory (RAM), internal memory, read only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other in the technical field. in any other known form of storage medium.

The data loading method, apparatus, device, and computer-readable storage medium of the RISC-V vector processor provided in this application have been described in detail above. Specific examples are used herein to illustrate the principles and implementations of the present application, and the descriptions of the above embodiments are only used to help understand the methods and core ideas of the present application. It should be pointed out that for those of ordinary skill in the art, without departing from the principles of the present application, several improvements and modifications can also be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims (10)

1. a data loading method of a RISC-V vector processor, is characterized in that, comprises: Execute the data preloading instruction to load the target data from the first memory into the second memory; wherein, the data preloading instruction and the ordinary instruction running before the data loading instruction are run in parallel; The data load instruction is executed to load the target data from the second memory to the RISC-V vector processor. 2. The data loading method according to claim 1, wherein the executing the data preloading instruction to load the target data from the first memory into the second memory comprises: querying the second memory according to the data preload instruction; If the second memory misses the target data, loading the target data from the first memory to the second memory; If the second memory hits the partial data of the target data, loading the partial data of the target data that the second memory misses into the second memory from the first memory; If the second memory hits the target data, the target data is not loaded from the first memory into the second memory. 3. The data loading method according to claim 1, wherein the loading of the target data from the second memory to a RISC-V vector processor comprises: Loading the target data from the second memory into the target register group specified by the data loading instruction in the RISC-V vector processor. 4. The data loading method according to claim 1, wherein executing a data loading instruction to load the target data from the second memory to the RISC-V vector processor comprises: query the second memory according to the data loading instruction; If the second memory misses the target data, after loading the target data from the first memory to the second memory, load the target data from the second memory to RISC-V vector processor; If the second memory hits the partial data of the target data, after the partial data of the target data that the second memory misses is loaded from the first memory into the second memory, all the data are loaded into the second memory. The target data is loaded into the RISC-V vector processor from the second memory; If the second memory hits the target data, the target data is loaded from the second memory to the RISC-V vector processor. 5. The data loading method according to claim 1, wherein before the execution of the data preloading instruction, the method further comprises: The data preload instruction is loaded from the third memory to the RISC-V vector processor. 6. The data loading method according to claim 1, wherein before executing the data loading instruction, it further comprises: The data load instruction is loaded from the third memory to the RISC-V vector processor. 7. a data loading device of a RISC-V vector processor, is characterized in that, comprises: The first instruction execution module is used to execute the data preloading instruction, and load the target data from the first memory into the second memory; wherein, the data preloading instruction and the ordinary instruction running before the data loading instruction are run in parallel; The second instruction execution module is configured to execute the data loading instruction to load the target data from the second memory to the RISC-V vector processor. 8. The data loading apparatus according to claim 7, wherein the first instruction execution module comprises: a first query unit, configured to query the second memory according to the data preloading instruction; a first loading unit, configured to load the target data from the first memory to the second memory if the second memory misses the target data; if the second memory hits the target If the second memory misses the partial data of the target data, load the partial data of the target data from the first memory into the second memory; if the second memory hits the target data, then The target data is not loaded from the first memory into the second memory. 9. A data loading device of a RISC-V vector processor, characterized in that, comprising: memory for storing computer programs; The processor is configured to implement the steps of the data loading method of the RISC-V vector processor according to any one of claims 1 to 6 when executing the computer program. 10. A computer-readable storage medium, wherein a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the RISC according to any one of claims 1 to 6 is implemented -V Steps of the vector processor's data loading method.

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