CN114627835A

CN114627835A - Time sequence control method, time sequence controller and display device

Info

Publication number: CN114627835A
Application number: CN202210263231.6A
Authority: CN
Inventors: 周满城; 郑浩旋
Original assignee: HKC Co Ltd
Current assignee: HKC Co Ltd
Priority date: 2022-03-17
Filing date: 2022-03-17
Publication date: 2022-06-14

Abstract

The application belongs to the field of display, and particularly relates to a time sequence control method, a time sequence controller and a display device, wherein the time sequence control method comprises the following steps: the method comprises the steps of obtaining the gray level of a current frame and the gray level of a previous frame of a sub-pixel, comparing the gray level of the current frame with the gray level of the previous frame, and selecting and outputting a polarity holding control signal or a polarity inversion control signal based on the relation between the difference value between the gray level of the current frame and the gray level of the previous frame and a first preset value. The output polarity holding control signal or the polarity inversion control signal is determined according to the gray scale change condition of the sub-pixel display picture, when the polarity holding control signal is output, the polarity inversion does not occur to the data, the voltage of the data line and the voltage of the pixel electrode do not have a voltage difference, and the liquid crystal capacitor and the storage capacitor are not charged and discharged, so that the power consumption is reduced.

Description

Time sequence control method, time sequence controller and display device

Technical Field

The application belongs to the field of display, and particularly relates to a time sequence control method, a time sequence controller and a display device.

Background

When a thin film transistor liquid crystal display (namely TFT-LCD) is driven, the driving mode is line-by-line scanning, when scanning line signals in the row direction are high level, the thin film transistor of the control switch is turned on, data line signals in the column direction are written into sub-pixels, voltage difference exists at two ends of a liquid crystal electrode in the sub-pixels, and the light transmittance of liquid crystal is adjusted by rotation of the liquid crystal due to the voltage difference. When the voltage is removed, the residual charges exist at the two ends of the capacitor, and the display panel can generate residual images, so that the time schedule controller is required to provide a polarity inversion control signal to invert the polarity of the control voltage of the liquid crystal. That is, even when the display panel displays a still image, the voltage on the liquid crystal electrode is always inverted, and the liquid crystal electrode is continuously charged and discharged, resulting in power consumption.

Disclosure of Invention

The present disclosure provides a timing control method, a timing controller and a display device to reduce charging and discharging of liquid crystal electrodes and reduce power consumption of a display panel.

In order to achieve the above object, the present application provides a timing control method, including:

acquiring the gray level of a current frame and the gray level of a previous frame of the sub-pixels;

comparing the gray level of the current frame with the gray level of the previous frame;

and selecting and outputting a polarity maintaining control signal or a polarity reversing control signal based on the relation between the difference value between the gray level of the current frame and the gray level of the previous frame and a first preset value.

Optionally, the selecting and outputting the polarity maintaining control signal or the polarity inverting control signal based on the relationship between the difference between the gray scale of the current frame and the gray scale of the previous frame and the first preset value includes:

outputting a polarity holding control signal when the difference value between the gray level of the current frame and the gray level of the previous frame is smaller than the first preset value;

and outputting a polarity inversion control signal when the difference value between the gray level of the current frame and the gray level of the previous frame is greater than or equal to the first preset value.

Optionally, the timing control method further includes:

recording the continuous frame number of which the difference value between the gray scale of the current frame and the gray scale of the previous frame is smaller than the first preset value;

and outputting the polarity inversion control signal when the continuous frame number is confirmed to be larger than a second preset value.

Optionally, the first preset value is 1, and/or the second preset value is 24 frames to 30 frames.

Optionally, the output of the polarity holding control signal or the polarity inversion control signal is performed simultaneously with the output of the time control signal, so as to control the output time of the polarity holding control signal or the polarity inversion control signal.

The present application further provides a timing controller, comprising:

the table look-up unit is used for acquiring and comparing the gray scale of the current frame of the sub-pixels with the gray scale of the previous frame, and is also used for outputting a first selection signal when the difference value between the gray scale of the current frame and the gray scale of the previous frame is smaller than a first preset value, and outputting a second selection signal when the difference value between the gray scale of the current frame and the gray scale of the previous frame is larger than or equal to the first preset value;

a selection unit for outputting a polarity holding control signal based on the first selection signal and outputting a polarity inversion control signal based on the second selection signal;

and the time control unit outputs a time control signal to control the output time of the polarity maintaining control signal or the polarity reversing control signal.

Optionally, the timing controller further includes a counting unit, the counting unit records a number of consecutive frames in which a difference between the gray level of the current frame and the gray level of the previous frame is smaller than the first preset value, and when it is determined that the number of consecutive frames is greater than a second preset value, the selecting unit outputs the polarity inversion control signal.

The present application also provides a display device, including:

the timing controller of any of the above;

the source driving chip is connected with the selection unit and the time control unit of the time schedule controller, the source driving chip comprises at least one group of driving units, the driving units comprise a first data channel and a second data channel, the first data channel comprises a first input register, a first data latch, a first signal amplifier, a positive digital-to-analog converter and a first output register which are sequentially connected, the second data channel comprises a second input register, a second data latch, a second signal amplifier, a negative digital-to-analog converter and a second output register which are sequentially connected, the time schedule controller outputs a polarity inversion control signal or a polarity retention control signal to control the polarity of a data signal, the source driving chip further comprises an input data selector and an output data selector, and the input data selector changes the input data signal into the first data channel or the second data channel to perform data inversion according to the polarity of the output data signal D/A conversion, the said output data selector changes the data signal after D/A conversion back to the original data channel;

the two data lines are respectively connected with the first data channel and the second data channel;

and a plurality of sub-pixels connected to each of the data lines.

Optionally, the timing controller includes an output line and a control line, and the output line outputs the polarity inversion control signal or the polarity holding control signal;

the time control unit outputs the time control signal through the control line, and controls the polarity inversion control signal or the polarity maintaining control signal to be output to different driving units.

Optionally, the timing controller includes a plurality of groups of connection lines, each group of connection lines includes one output line and one control line, each group of connection lines is connected to at least one source driver chip, and the number of the connection lines connected to the source driver chips is the same or different;

the time control unit outputs the time control signal through the control line, and controls the polarity inversion control signal or the polarity holding control signal to be output to different source driving chips.

The time sequence control method, the time sequence controller and the display device disclosed by the application have the following beneficial effects:

in the application, before outputting the polarity holding control signal or the polarity inversion control signal, the relationship between the difference value of the gray levels of the current frame and the previous frame of the sub-pixel and the first preset value is compared, so as to judge that the sub-pixel displays a static picture, the gray level change of a display picture is small or the gray level change of the display picture is large, the polarity holding control signal or the polarity inversion control signal is determined to be output according to the gray level change condition of the display picture of the sub-pixel, when the polarity holding control signal is output, the polarity inversion does not occur to data, the voltage of a data line and the voltage of a pixel electrode do not have a voltage difference, and the liquid crystal capacitor and the storage capacitor are not charged or discharged, so that the power consumption is reduced.

Other features and advantages of the present application will be apparent from the following detailed description, or may be learned by practice of the application.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.

Fig. 1 is a flowchart illustrating a timing control method according to an embodiment of the present application.

Fig. 2 is a detailed flowchart of step S300 in fig. 1.

Fig. 3 is a schematic structural diagram of a sub-pixel according to an embodiment of the present application.

Fig. 4 is a schematic voltage waveform diagram of the data line and the common electrode in the first embodiment of the present application.

Fig. 5 is a schematic structural diagram of a timing controller in the second embodiment of the present application.

Fig. 6 is a schematic structural diagram of a display device according to a third embodiment of the present application.

Fig. 7 is a schematic structural diagram of a source driver chip in the third embodiment of the present application.

Fig. 8 is a schematic diagram illustrating a connection between a timing controller and a source driver chip in the third embodiment of the present application.

Fig. 9 is a graph of the gray scale of the screen display in the third embodiment of the present application.

Fig. 10 is a schematic waveform diagram of output data of output lines and control lines in the third embodiment of the present application.

Fig. 11 is a flowchart of a data signal polarity inversion control in the third embodiment of the present application.

Fig. 12 is a schematic connection diagram of a timing controller for multiple groups of connection lines in the third embodiment of the present application.

Description of reference numerals:

100. a sub-pixel; 101. scanning a line; 102. a data line; 103. a thin film transistor; 104. a pixel electrode; 105. a liquid crystal capacitor; 106. a storage capacitor; 107. a common electrode;

200. a time schedule controller; 201. a table look-up unit; 202. a time control unit; 203. a selection unit; 204. a counting unit; 205. an output line; 206. a control line;

300. a source driver chip; 301. an input data selector, 302, an output data selector; 311. a first input register; 312. a first data latch; 313. a first signal amplifier; 314. a positive digital-to-analog converter; 315. a first output register; 321. a second input register; 322. latching the second data; 323. a second signal amplifier; 324. a negative digital-to-analog converter; 325. a second output register;

400. a printed circuit board.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the subject matter of the present application can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and so forth. In other instances, well-known methods, devices, implementations, or operations have not been shown or described in detail to avoid obscuring aspects of the application.

The present application will be described in further detail with reference to the following drawings and specific examples. It should be noted that the technical features mentioned in the embodiments of the present application described below may be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present application and should not be construed as limiting the present application.

Example one

Fig. 1 is a schematic flow chart of a timing control method according to an embodiment of the present disclosure, and referring to fig. 1, the timing control method is used for a timing controller, and the timing control method according to the embodiment includes:

s100: acquiring the gray level of a current frame and the gray level of a previous frame of the sub-pixels;

s200: comparing the gray level of the current frame with the gray level of the previous frame;

s310: based on the relationship between the difference between the gray scale of the current frame and the gray scale of the previous frame and the first preset value, the polarity maintaining control signal or the polarity inverting control signal is selected and output.

Fig. 3 is a schematic structural diagram of a sub-pixel according to an embodiment of the present disclosure, and referring to fig. 3, the sub-pixel includes a thin film transistor 103 for controlling a switch, the thin film transistor 103 includes a source, a drain, and a gate, the gate is connected to a scan line 101, the source is connected to a data line 102, and the drain is connected to a pixel electrode 104. When the scan line 101 outputs a switching signal, the data line 102 outputs a data signal, and when the scan line 101 is at a high level, the data signal of the data line 102 can be written into the sub-pixel. The sub-pixel further comprises a common electrode 107, a liquid crystal capacitor 105 and a storage capacitor 106 are arranged between the pixel electrode 104 and the common electrode 107, and the liquid crystal capacitor 105 is an equivalent capacitor of liquid crystal.

According to the structure of the tft lcd, liquid crystal is sandwiched between the upper and lower glass layers, the liquid crystal is a capacitive material, and the equivalent liquid crystal capacitor 105 is about 0.1pF, and this capacitor cannot keep the voltage until the next picture data update, so that a storage capacitor 106 is needed to keep the charged voltage until the next picture update. Under the action of the electric field, the liquid crystal molecules change in arrangement, thereby affecting the incident light beam to transmit through the liquid crystal to generate intensity change, and the intensity change is represented as the change of the display gray scale of the picture in the display picture. For example, the gray scale of the screen display with continuous black-gray-white variation is quantized to 256 gray levels, and the gray scale range is 0 to 255.

Fig. 4 is a schematic voltage waveform diagram of the data line and the common electrode in the first embodiment of the present application, see fig. 4, Vcom is the voltage of the common electrode 107, S-out is the voltage of the data line 102, the voltage of the common electrode 107 is not changed, the voltage of the data line 102 is higher than the voltage of the common electrode 107, i.e., positive polarity, and the voltage of the data line 102 is lower than the voltage of the common electrode 107, i.e., negative polarity. The timing controller outputs a polarity inversion control signal, which periodically changes the polarity of the data signal (i.e., S-out) output by the data line 102 to charge and discharge the liquid crystal capacitor 105 and the storage capacitor 106, thereby eliminating the remaining charges at the two ends of the liquid crystal capacitor 105 and the storage capacitor 106 and preventing the display image from having residual images.

The timing controller outputs a polarity maintaining control signal to keep the polarity of the data signal output by the data line 102 unchanged, when the scanning line 101 is at a high level, the thin film transistor 103 of the control switch is turned on, the data signal output by the data line 102 is written into the sub-pixel, the polarity of the data is not inverted, the voltage difference between the voltage of the data line 102 and the voltage of the pixel electrode 104 does not exist, and the liquid crystal capacitor 105 and the storage capacitor 106 are not charged and discharged, thereby reducing the power consumption.

In the application, before outputting the polarity holding control signal or the polarity inversion control signal, the relationship between the difference between the gray levels of the current frame and the previous frame of the sub-pixel and the first preset value is compared, so as to determine whether the sub-pixel displays a static picture, the gray level change of the display picture is small or the gray level change of the display picture is large, the polarity holding control signal or the polarity inversion control signal is determined to be output according to the gray level change condition of the display picture of the sub-pixel, when the polarity holding control signal is output, the polarity inversion does not occur to the data, the voltage of the data line 102 and the voltage of the pixel electrode 104 do not have a voltage difference, and the liquid crystal capacitor 105 and the storage capacitor 106 are not charged or discharged, so as to reduce the power consumption.

For example, fig. 2 is a specific flowchart of step S300 in fig. 1, and referring to fig. 2, step S300 of the timing control method includes step S310: when the difference value between the gray scale of the current frame and the gray scale of the previous frame is larger than or equal to a first preset value, a polarity inversion control signal is output.

The first preset value can be set as 1 gray value, the difference value between the gray level of the previous frame and the gray level of the previous frame is greater than or equal to 1 gray value, which indicates that the gray levels of the two frames of pictures are different, and the time schedule controller periodically changes the polarity of the data signals output by the data lines 102 by outputting the polarity inversion control signal, so as to avoid the occurrence of ghost in the displayed picture.

It should be noted that the first preset value may also be greater than 1, for example, the first preset value is 2, 3, and the like, which may be set as the case may be.

Referring to fig. 2, step S300 of the timing control method further includes S320: when the difference between the gray scale of the current frame and the gray scale of the previous frame is less than a first preset value, a polarity holding signal is output.

The first preset value can be set as 1 gray value, the difference between the gray value of the previous frame and the gray value of the previous frame is less than 1 gray value, which indicates that the gray values of the two frames are the same, the time-schedule controller outputs the polarity maintaining control signal, the data line 102 outputs the data signal to be written into the sub-pixel, the polarity of the data is not reversed, the voltage of the data line 102 and the voltage of the pixel electrode 104 have no voltage difference, and the liquid crystal capacitor 105 and the storage capacitor 106 are not charged and discharged, thereby reducing the power consumption.

It should be noted that the first preset value may also be greater than 1, for example, the first preset value is 2, 3, and the like, which may be set as the case may be. The first preset value can also be larger than 1, and the difference value between the gray level of the previous frame and the gray level of the previous frame is smaller than the first preset value, which indicates that the gray level difference between the two frames is not large, and the polarity maintaining control signal can also be output when the gray level difference between the two frames is not large, so as to reduce the power consumption.

Referring to fig. 2, the timing control method further includes:

s330: recording the continuous frame number of which the difference value between the gray scale of the current frame and the gray scale of the previous frame is smaller than a first preset value;

s340: when the number of consecutive frames is larger than the second predetermined value, the polarity inversion control signal is outputted.

If the voltage of the data line 102 is constant, the voltage of the pixel electrode 104 is also constant, and when the voltage is removed, the liquid crystal is difficult to restore. Meanwhile, the voltage of the data line 102 is kept constant, and the voltage between the pixel electrode 104 and the common electrode 107 is difficult to maintain, which affects the image display.

In this embodiment, when the number of consecutive frames is greater than the second predetermined value, the timing controller outputs the polarity inversion control signal to invert the polarity of the data signal output by the data line 102, that is, even though the still picture is always displayed, when the number of consecutive frames of the still picture is greater than the second predetermined value, the polarity of the data signal output by the data line 102 is periodically inverted, and the liquid crystal capacitor 105 and the storage capacitor 106 are charged and discharged once, thereby ensuring that the display device can normally display.

For example, the second preset value is 24 frames to 30 frames, and for example, the second preset value may be 24 frames, 26 frames, 28 frames, 30 frames, and the like.

It should be noted that the second preset value can be 24 frames to 30 frames, but is not limited thereto, and the specific range of the second preset value can be set as appropriate.

The second preset value can be set to 24 frames to 30 frames, that is, when the display picture is a static picture, the liquid crystal capacitor 105 and the storage capacitor 106 are charged and discharged once every 24 frames to 30 frames, so that the design can reduce the frequency of charging and discharging the liquid crystal capacitor 105 and the storage capacitor 106 on one hand, thereby reducing the power consumption of the display device, and on the other hand, the display device can be ensured to display normally.

In some embodiments, the timing controller outputs the timing control signal to control the output timing of the polarity holding control signal or the polarity inversion control signal at the same time as the polarity holding control signal or the polarity inversion control signal is output.

The time sequence controller outputs the time control signal, and the controllable signal controls the polarity inversion control signal or the polarity maintaining control signal to be output to different driving units and different source driving chips.

Example two

The second embodiment provides a timing controller 200 for implementing the timing control method of the first embodiment. Fig. 5 is a schematic structural diagram of a timing controller in a second embodiment of the present application, and referring to fig. 5, the timing controller 200 includes a table look-up unit 201, a time control unit 202, and a selection unit 203, where the table look-up unit 201 is configured to obtain and compare the gray scale of the current frame and the gray scale of the previous frame of the sub-pixel, and output the comparison result to the selection unit 203. And outputting a first selection signal when the difference between the gray scale of the current frame and the gray scale of the previous frame is smaller than a first preset value, and outputting a second selection signal when the difference between the gray scale of the current frame and the gray scale of the previous frame is larger than or equal to the first preset value. The selection unit 203 outputs a comparison result, when the difference between the gray scale of the current frame and the gray scale of the previous frame is smaller than a first preset value, the table look-up unit 201 outputs a first selection signal, and the selection unit 203 outputs a polarity holding control signal

When the difference between the gray level of the current frame and the gray level of the previous frame is greater than or equal to the first preset value, the table look-up unit 201 outputs a second selection signal and outputs a polarity inversion control signal POL. The time control unit 202 outputs a time control signal to control the polarity holding control signal POL or the polarity inversion control signal

The output time of (2).

The timing controller executes the timing control method of the first embodiment, the lookup unit 201 obtains and compares the gray level of the current frame and the gray level of the previous frame of the sub-pixel, and the selection unit 203 outputs the polarity holding control signal when the difference between the gray level of the current frame and the gray level of the previous frame is smaller than the first preset value

The polarity of the data signal output by the data line 102 is kept unchanged, when the scanning line 101 is at a high level, the thin film transistor 103 for controlling the switch is turned on, the data signal output by the data line 102 is written into the sub-pixel, the polarity of the data is not inverted, the voltage difference between the data line 102 and the pixel electrode 104 is not generated, and the liquid crystal capacitor 105 and the storage capacitor 106 are not charged and discharged, thereby reducing the power consumption.

Referring to fig. 5, the timing controller 200 includes a counting unit 204, the counting unit 204 records a number of consecutive frames in which a difference between a gray level of a current frame and a gray level of a previous frame is less than a first preset value, and the selecting unit 203 outputs a polarity inversion control signal when it is determined that the number of consecutive frames is greater than a second preset value.

In this embodiment, the counting unit 204 records the number of consecutive frames in which the difference between the gray level of the current frame and the gray level of the previous frame is smaller than the first predetermined value, and when the number of consecutive frames is greater than the second predetermined value, the selecting unit 203 outputs the polarity inversion control signal to charge and discharge the liquid crystal capacitor 105 and the storage capacitor 106 once, so as to ensure that the display device can display normally.

EXAMPLE III

Fig. 6 is a schematic structural diagram of a display device according to a third embodiment of the present application, and referring to fig. 6, the display device includes a timing controller 200, a source driving chip 300, a data line 102, and a sub-pixel 100, wherein the source driving chip 300 is connected to the data line 102 and the sub-pixel 100. The timing controller 200 includes the timing controller 200 of the second embodiment, and the selection unit 203 and the timing control unit 202 of the timing controller 200 are connected to the source driving chip 300.

It should be noted that the display device may further include a display panel, a flexible circuit board, and a printed circuit board 400, besides the timing controller 200, the source driving chip 300, the data line 102, and the sub-pixel 100, the timing controller 200 is disposed on the printed circuit board 400, the flexible circuit board connects the display panel and the printed circuit board 400, and the source driving chip 300 is disposed on the flexible circuit board. The display panel may include an array substrate, an opposite substrate, and liquid crystals between the array substrate and the opposite substrate, to which the scan lines 101, the data lines 102, and the sub-pixels 100 are disposed, and a common electrode 107 disposed on the opposite substrate.

The display device comprises the timing controller 200 of the second embodiment, the lookup unit 201 of the timing controller 200 obtains and compares the gray scale of the current frame and the gray scale of the previous frame of the sub-pixel 100, when the difference between the gray scale of the current frame and the gray scale of the previous frame is less than the first predetermined value, the selection unit 203 outputs the polarity holding control signal

The polarity of the data signal output by the data line 102 is kept unchanged, when the scanning line 101 is at a high level, the thin film transistor 103 for controlling the switch is turned on, the data signal output by the data line 102 is written into the sub-pixel 100, the polarity of the data is not inverted, the voltage difference between the voltage of the data line 102 and the voltage of the pixel electrode 104 does not exist, and the liquid crystal capacitor 105 and the storage capacitor 106 are not charged and discharged, so that the power consumption of the display device is reduced.

Fig. 7 is a schematic structural diagram of a source driver chip according to a third embodiment of the present invention, and referring to fig. 7, the source driver chip 300 includes at least one set of driving units, each of the driving units includes an input register (i.e., input register), a data latch (i.e., data latch), a signal amplifier (i.e., L/S), a positive digital-to-analog converter (i.e., P-DAC), a negative digital-to-analog converter (i.e., N-DAC), an output register (i.e., output register), an input selector (i.e., input mux), and an output selector (i.e., output mux), the input register is used for processing a data signal sent from the timing controller 200 and converting the data signal into a data form recognizable inside the source driver chip 300, the data latch controls the time for digital-to-analog conversion of data, the positive digital-to-analog converter and the negative digital to-analog converter are both used for digital-to-analog conversion of the data signal, the signal amplifier is used for converting a pulse low-voltage signal into a pulse high-voltage signal, for example, the high level is 3.3V and the low level is 0V before the signal amplifier is switched, and the high level is 16.5V and the low level is 0V after the signal amplifier is switched.

The source driver chip 300 further includes a decoder (not shown), the selection unit 203 is connected to the decoder through the output line 205 (i.e., SDA), the timing control unit 202 is connected to the decoder through the control line 206 (i.e., SCL), and the decoder generates the polarity inversion control signal POL or the polarity holding control signal POL

Decoded into a data form that the source driving chip 300 can recognize.

The driving unit has a first data path including a first input register 311, a first data latch 312, a first signal amplifier 313, a positive digital-to-analog converter 314, and a first output register 315, which are connected in sequence, and a second data path including a second input register 321, a second data latch 322, a second signal amplifier 323, a negative digital-to-analog converter 324, and a second output register 325, which are connected in sequence. The timing controller 200 outputs a polarity inversion control signal POL or a polarity holding control signal

Control the polarity of the data signal, the polarity inversion control signal POL inverts the polarity of the data signal, and the polarity holding control signal

The polarity of the data signal is left unchanged.

The source driver chip 300 further includes an input data selector 301 and an output data selector 302, wherein the input data selector 301 converts the input data signal into the first data channel or the second data channel for digital-to-analog conversion according to the polarity of the output data signal, and the output data selector 302 converts the digital-to-analog converted data signal back into the original data channel. For example, when the first data channel of the previous frame outputs a positive polarity data signal and the difference between the gray level of the current frame and the gray level of the previous frame is smaller than the first predetermined value, the selection unit 203 outputs a polarity holding control signal

A data signal of the first input register 311 is output to the data line 102 via the first data latch 312, the first signal amplifier 313, the positive digital-to-analog converter 314, and the first output register 315; when the difference between the gray scale of the current frame and the gray scale of the previous frame is greater than or equal to the first predetermined value, the selection unit 203 outputs the polarity inversion control signal POL, the data signal of the first input register 311 is converted into the second data latch 322, the second signal amplifier 323, the negative digital-to-analog converter 324 by the input data selector 301, and the data signal is converted back into the first output register 315 of the first data channel by the output data selector 302.

In the source driver chip 300, the positive polarity data signal is converted into digital-analog signals by the positive digital-analog converter 314, the negative polarity data signal is converted into digital-analog signals by the negative digital-analog converter 324, and each data channel only needs one of the positive digital-analog converter 314 and the negative digital-analog converter 324, so that the circuit structure of the source driver chip 300 can be simplified.

Fig. 8 is a schematic diagram illustrating a connection between a timing controller and a source driver chip according to a third embodiment of the present invention, and referring to fig. 8, the timing controller 200 includes an output line 205 (i.e., SDA) and a control line 206 (i.e., SCL), the output line 205 outputs a polarity inversion control signal POL or a polarity holding control signal SCL

The timing control unit 202 outputs a timing control signal to control the polarity inversion control signal POL or the polarity holding control signal through the control line 206

Output to different drive units. When the timing controller 200 is connected to the plurality of source driver chips 300, the timing control unit 202 outputs a timing control signal through the control line 206 to controlControl signal POL for controlling polarity inversion or control signal for maintaining polarity

Output to different source driver chips 300.

For example, fig. 9 is a graph of the gray scale of the display screen in the third embodiment of the present application, and as shown in fig. 9, the horizontal row S₁Sn denotes a data line 102, columns 1 st row to m th row denote a scan line 101, and n and m are integers greater than 0. When the difference between the gray level of the current frame and the gray level of the previous frame is smaller than the first preset value, it indicates that the gray levels of the two frames are the same, the table look-up unit 201 outputs 0, and when the difference between the gray level of the current frame and the gray level of the previous frame is greater than or equal to the first preset value, it indicates that the gray levels of the two frames are different, and the table look-up unit 201 outputs 1. The output line 205 of the timing controller 200 outputs a polarity inversion control signal POL when the selection unit 203 receives a 1 output from the lookup unit 201, and the output line 205 of the timing controller 200 outputs a polarity holding control signal POL when the selection unit 203 receives a 0 output from the lookup unit 201

Fig. 10 is a schematic waveform diagram of output data of output lines and control lines in the third embodiment of the present application, and as shown in fig. 10, a rising edge and a falling edge of the control line 206 capture the output data of the output line 205, if the output line 205 is at a high level, the captured data is 1, and if the output line 205 is at a low level, the captured data is 0. Wherein, each data is output to a driving unit, i.e. from the first driving unit to the last driving unit, and the polarity inversion control signal POL or the polarity holding control signal is output from the output line 205 to each driving unit

And (4) controlling independently.

Fig. 11 is a flowchart of a polarity inversion control of a data signal according to a third embodiment of the present application, and referring to fig. 11, when a difference between a gray level of a current frame and a gray level of a previous frame is greater than or equal to a first preset value, it indicates that gray levels of two frames before and after are different, and the output line 205 outputs a polarity inversion control signal POL. When the source driver chip 300 receives such data, if the previous frame S1 outputs a negative polarity and the previous frame S2 outputs a positive polarity, the current frame S1 outputs a positive polarity, the current frame S2 outputs a negative polarity, and the data lines 102 output a signal with a reversed polarity.

When the difference between the gray scale of the current frame and the gray scale of the previous frame is smaller than the first predetermined value, it indicates that the gray scales of the two frames are the same, and the output line 205 outputs a polarity holding control signal

After the source driver chip 300 receives such data, if the last frame S1 outputs a negative polarity and the last frame S2 outputs a positive polarity, the current frame S1 outputs a negative polarity and the current frame S2 outputs a positive polarity, the polarity of the output signal of the data line 102 remains unchanged, the polarity of the data is not inverted, the voltage of the data line 102 and the voltage of the pixel electrode 104 do not have a voltage difference, and the liquid crystal capacitor 105 and the storage capacitor 106 are not charged and discharged, thereby reducing the power consumption of the display device.

The first data channel and the second data channel are respectively connected with two data lines 102, the positive and negative polarities of which are circulated by taking the adjacent data lines 102 as a minimum unit, and the polarity inversion control signal POL or the polarity holding control signal POL

The amount of data of (a) is enormous, for example, a display device having a resolution of 1920 × 1080, and the total amount of data is 186.624 MHz.

Fig. 12 is a schematic diagram illustrating connection of a timing controller with a plurality of groups of connection lines according to a third embodiment of the present invention, and referring to fig. 12, the timing controller 200 includes a plurality of groups of connection lines, each group of connection lines includes an output line 205 and a control line 206, each group of connection lines is connected to at least one source driver chip 300, and the number of different connection lines connected to the source driver chips is the same or different. The time control unit 202 outputs a time control signal via the control line 206 to control the polarity inversion control signal POL or the polarity holding control signal

Output to different source driver chips 300.

Control polarity inversion control signal POL or polarity holding control signal

The output to the different source driver chips 300, each group of connection lines including one control line 206, the data amount transmitted by the single control line 206 is reduced, so that the transmission rate of the control line 206 can be reduced.

The terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In this application, unless expressly stated or limited otherwise, the terms "mounted," "connected," and the like are to be construed broadly and include, for example, fixed connections, removable connections, or integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

In the description herein, references to the description of the terms "some embodiments," "exemplary," etc. mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or exemplary is included in at least one embodiment or exemplary of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Although embodiments of the present application have been shown and described, it is understood that the above embodiments are illustrative and should not be construed as limiting the present application and that various changes, modifications, substitutions and alterations can be made therein by those skilled in the art within the scope of the present application, and therefore all changes and modifications that come within the meaning of the claims and the description of the invention are to be embraced therein.

Claims

1. A timing control method, comprising:

2. The timing control method of claim 1, wherein the selecting the output of the polarity holding control signal or the polarity inverting control signal based on the relationship between the difference between the gray level of the current frame and the gray level of the previous frame and a first predetermined value comprises:

3. The timing control method according to claim 2, further comprising:

4. The timing control method according to claim 3, wherein the first preset value is 1, and/or the second preset value is 24-30 frames.

5. The timing control method according to claim 1, wherein a timing control signal is output to control an output timing of the polarity holding control signal or the polarity inversion control signal while the polarity holding control signal or the polarity inversion control signal is output.

6. A timing controller, comprising:

and the time control unit outputs a time control signal to control the output time of the polarity holding control signal or the polarity inversion control signal.

7. The timing controller of claim 6, further comprising a counting unit, wherein the counting unit records a number of consecutive frames in which a difference between the gray level of the current frame and the gray level of the previous frame is less than the first preset value, and the selecting unit outputs the polarity inversion control signal when the number of consecutive frames is confirmed to be greater than a second preset value.

8. A display device, comprising:

the timing controller of claim 6 or 7;

and a plurality of sub-pixels connected to each of the data lines.

9. The display device according to claim 8, wherein the timing controller includes an output line that outputs the polarity inversion control signal or the polarity holding control signal, and a control line;

10. The display device according to claim 8, wherein the timing controller comprises a plurality of sets of connection lines, each set of connection lines comprises one of the output lines and one of the control lines, each set of connection lines is connected to at least one of the source driver chips, and the number of connection lines connected to the source driver chips is the same or different;