CN114627930B - Single-bit differential SRAM (static random Access memory) storage integrated array and device - Google Patents
Single-bit differential SRAM (static random Access memory) storage integrated array and device Download PDFInfo
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- G—PHYSICS
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
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- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
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Abstract
The invention relates to a single-bit differential SRAM (static random Access memory) storage integrated array and a device, wherein the array comprises a plurality of storage integrated units, a first capacitor and a second capacitor, each storage integrated unit comprises a 6T-SRAM storage unit, a first inverter, a second inverter, a transistor TL3 and a transistor TR3, the first inverter is respectively connected with drains of the storage unit and the TL3, a grid electrode of the TL3 is used for inputting data IN, a source electrode of the TL3 is connected with one end of the first capacitor, the other end of the first capacitor is grounded, the second inverter is respectively connected with drains of the storage unit and the TR3, a grid electrode of the TR3 is used for inputting data IN, a source electrode of the TR3 is connected with one end of the second capacitor, and the other end of the second capacitor is grounded. The integrated memory-calculation array calculates an integrated array of memory-calculation units simultaneously in the calculation process, has no influence on the weight value, and completely eliminates the read-write interference in the decoupling operation.
Description
Technical Field
The invention relates to the technical field of memory computation, in particular to a single-bit differential SRAM memory computation integrated array and a device.
Background
The unprecedented growth in Deep Neural Network (DNN) size has led to the need for large amounts of data in modern Machine Learning (ML) accelerators to be moved from off-chip memory to on-chip processing cores. The industry is currently exploring designs for performing analog DNN computations in memory arrays, and memory Computing (CIM) and memory Processing (PIM) methods have been developed to reduce the power consumption of DNN processors by implementing parallel data processing in memory, CIM allowing MAC operations to be performed in each column by activating multiple rows, rather than accessing raw data row by row as in conventional memory. This greatly reduces the amount of intermediate data generated and facilitates highly parallel computing.
The traditional calculation mode of single bit input multiplied by single bit weight has lower efficiency, and the weight value is interfered when the bit line voltage swing is overlarge in the calculation process because the weight is connected to the source and drain electrodes of the transistors, and in addition, the analog-to-digital conversion is realized by using a very accurate quantization comparator because the bit line voltage quantization range is too small in the multi-unit calculation, otherwise, quantization errors are caused, and meanwhile, the high-speed and high-accuracy ADC can bring considerable energy consumption with a large duty ratio, so that the optimization of energy efficiency parameters is not facilitated. Meanwhile, in the multiplication and accumulation calculation process, the multiplication calculation with the input of 0 has no influence on the calculation result in practice, but if the input multiplication weight is asymmetric operation, the calculation result can generate unexpected influence.
Disclosure of Invention
The invention aims to provide a single-bit differential SRAM (static random Access memory) integrated array and a device, so as to enlarge quantization margin and avoid read-write interference.
To achieve the above object, the present invention provides a single-bit differential SRAM integrated array, the array comprising:
m memory and calculation integrated units, a first capacitor and a second capacitor, wherein M is a positive integer greater than or equal to 1;
The integrated memory unit comprises a 6T-SRAM memory unit, a first inverter, a second inverter, a transistor TL3 and a transistor TR3, wherein the input end of the first inverter is connected with the Q point of the 6T-SRAM memory unit, the output end of the first inverter is connected with the drain electrode of the transistor TL3, the grid electrode of the transistor TL3 is used for inputting data IN, the source electrode of the transistor TL3 is connected with one end of a first capacitor, the other end of the first capacitor is grounded, the input end of the second inverter is connected with the QB point of the 6T-SRAM memory unit, the output end of the second inverter is connected with the drain electrode of the transistor TR3, the grid electrode of the transistor TR3 is used for inputting data IN, the source electrode of the transistor TR3 is connected with one end of a second capacitor, the other end of the second capacitor is grounded, and differential weight values are respectively stored at the Q point and the QB point;
The array further comprises:
And the differential quantizer is respectively connected with one end of the first capacitor and one end of the second capacitor and is used for outputting a voltage difference.
Optionally, the 6T-SRAM memory cell includes:
Transistors TP1, TP2, TN1, TN2, TN3, and TN4;
The source of the transistor TP1 and the source of the transistor TP2 are connected to the power supply VDD, the gate of the transistor TP1, the gate of the transistor TN1, the drain of the transistor TP2 and the drain of the transistor TN2 are all connected, the connection point is referred to as a QB point, the gate of the transistor TP2, the gate of the transistor TN2, the drain of the transistor TP1 and the drain of the transistor TN1 are all connected, the connection point is referred to as a Q point, the source of the transistor TN1 and the source of the transistor TN2 are both connected to the common terminal VSS, the gate of the transistor TN3 and the gate of the transistor TN4 are both connected to the word line, the drain of the transistor TN3 is connected to the Q point, the source of the transistor TN3 is connected to the bit line, the drain of the transistor TN4 is connected to the bit bar line, and the source of the transistor TN4 is connected to the QB point.
Optionally, the first inverter includes a transistor TL1 and a transistor TL2, wherein a source of the transistor TL1 is connected to the power supply VDD, a gate of the transistor TL1 and a gate of the transistor TL2 are both connected to the Q point, a drain of the transistor TL1 and a drain of the transistor TL2 are both connected to a drain of the transistor TL3, and a source of the transistor TL2 is grounded.
Optionally, the second inverter includes a transistor TR1 and a transistor TR2, wherein a source of the transistor TR1 is connected to the power supply VDD, a gate of the transistor TR1 and a gate of the transistor TR2 are both connected to the QB point, a drain of the transistor TR1 and a drain of the transistor TR2 are both connected to a drain of the transistor TR3, and a source of the transistor TR2 is grounded.
The invention also provides a single-bit differential SRAM integrated device, which comprises:
n of the integrated memory arrays, the input driving module, the bit line driving module and the word line driving module, wherein N is a positive integer greater than or equal to 1;
The input driving module comprises M data output ends, wherein the data output ends are used for outputting data IN;
the bit line driving module comprises N bit line output ends and N bit line inversion output ends, wherein the bit line output ends are used for outputting bit lines, and the bit line inversion output ends are used for outputting bit line inversion;
The word line driving module comprises M word line output ends, wherein the word line output ends are used for outputting word lines;
Each integrated unit in the ith row is respectively connected with the ith data output end of the input driving module, each integrated unit in the ith row is respectively connected with the ith word line output end of the word line driving module, each integrated unit in the jth column is respectively connected with the jth bit line output end of the bit line driving module, each integrated unit in the jth column is respectively connected with the jth inverse bit line output end of the bit line driving module, wherein i is a positive integer greater than or equal to 1 and less than or equal to M, and j is a positive integer greater than or equal to 1 and less than or equal to N.
Alternatively, N is 64 and m is 128.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
The invention relates to a single-bit differential SRAM (static random Access memory) storage integrated array and a device, wherein the array comprises a plurality of storage integrated units, a first capacitor and a second capacitor, each storage integrated unit comprises a 6T-SRAM storage unit, a first inverter, a second inverter, a transistor TL3 and a transistor TR3, the first inverter is respectively connected with drains of the storage unit and the TL3, a grid electrode of the TL3 is used for inputting data IN, a source electrode of the TL3 is connected with one end of the first capacitor, the other end of the first capacitor is grounded, the second inverter is respectively connected with drains of the storage unit and the TR3, a grid electrode of the TR3 is used for inputting data IN, a source electrode of the TR3 is connected with one end of the second capacitor, and the other end of the second capacitor is grounded. The integrated memory-calculation array calculates an integrated array of memory-calculation units simultaneously in the calculation process, has no influence on the weight value, completely eliminates the read-write interference by the decoupling operation, and enlarges the quantization margin.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a diagram of a single bit differential SRAM memory integrated array architecture of the present invention;
FIG. 2 is a diagram of a 6T-SRAM structure of the present invention;
fig. 3 is a schematic diagram of the operation of the present invention for calculating 1× (-1) = -1;
FIG. 4 is a schematic diagram of the operation of the present invention for calculating 1× (+1) = +1;
Fig. 5 is a schematic diagram of the operation of the present invention for calculating 0× (+1/-1) =0;
FIG. 6 is a block diagram of a single bit differential SRAM memory integrated device of the present invention;
Symbol description:
The circuit comprises a 1-input driving module, a 2-bit line driving module, a 3-word line driving module, a 4-memory integrated array, a 5-memory integrated unit, a 6-differential quantizer, a 7-first inverter and an 8-second inverter.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention aims to provide a single-bit differential SRAM (static random Access memory) integrated array and a device, so as to enlarge quantization margin and avoid read-write interference.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Example 1
The invention provides a single-bit differential SRAM (static random access memory) integrated array which comprises M integrated memory units 5 (namely cells), a first capacitor C1 and a second capacitor C2, wherein M is a positive integer greater than or equal to 1. Consider 1 calculation unit 5 as an example, as shown in fig. 1. The integrated memory unit 5 comprises a 6T-SRAM memory unit, a first inverter 7, a second inverter 8, a transistor TL3 and a transistor TR3, wherein the input end of the first inverter 7 is connected with the Q point of the 6T-SRAM memory unit, the output end of the first inverter 7 is connected with the drain electrode of the transistor TL3, the grid electrode of the transistor TL3 is used for inputting data IN, the source electrode of the transistor TL3 is connected with one end of a first capacitor C1, the other end of the first capacitor C1 is grounded, the input end of the second inverter 8 is connected with the QB point of the 6T-SRAM memory unit, the output end of the second inverter 8 is connected with the drain electrode of the transistor TR3, the grid electrode of the transistor TR3 is used for inputting data IN, the source electrode of the transistor TR3 is connected with one end of a second capacitor C2, and the other end of the second capacitor C2 is grounded.
As an alternative embodiment, the array of the invention further comprises a differential quantizer 6 connected to one end of the first capacitor C1 and one end of the second capacitor C2, respectively, for outputting a voltage difference OUT [4:0]. The voltage difference OUT [4:0] refers to the difference between the left Read Bit line (Read Bit Line Left, RBLL) and the right Read Bit line (Read Bit LINE RIGHT, RBLR). The memory integrated array in FIG. 1 consists of 1 memory weighted 6T-SRAM cells and Multiply-accumulate (MAC) computation logic on the left and right sides. The MAC calculation logic on the left consists of the first inverter, the transistor TL3 and the coupling capacitor C1, and the MAC calculation logic on the right consists of the second inverter, the transistor TR3 and the coupling capacitor C2. In this embodiment, the transistor TL3 and the transistor TR3 are both NMOS transistors. The transistor TL3 and the transistor TR3 are controlled by the input data IN, and when the input data in=1, the switch is turned on, otherwise the switch is turned off.
As shown in FIG. 2, the 6T-SRAM cell of the present invention includes a transistor TP1, a transistor TP2, a transistor TN1, a transistor TN2, a transistor TN3, and a transistor TN4.
The source of the transistor TP1 and the source of the transistor TP2 are connected with a power supply VDD, the grid of the transistor TP1, the grid of the transistor TN1, the drain of the transistor TP2 and the drain of the transistor TN2 are connected with a QB point, the grid of the transistor TP2, the grid of the transistor TN2, the drain of the transistor TP1 and the drain of the transistor TN1 are connected with a Q point, the source of the transistor TN1 and the source of the transistor TN2 are connected with a common end VSS, the grid of the transistor TN3 and the gate of the transistor TN4 are connected with a word line WL, the drain of the transistor TN3 is connected with a Q point, the source of the transistor TN3 is connected with a bit line BL, the drain of the transistor TN4 is connected with an inverse bit line BLB, and the source of the transistor TN4 is connected with the QB point.
In this embodiment, the transistors TP1, TP2, TN1, TN2, TN3, and TN4 constitute a classic 6T-SRAM memory cell for storing weight values. Wherein, the weight value of the difference is respectively stored in the Q point and the QB point. Word Line (WL) is connected to the gates of the transistors TN3 and TN4, controls on/off of the transistors TN3 and TN4, bit Line (BL) is connected to the source of the transistor TN3, bit Line Bit (BLB) is connected to the drain of the transistor TN4, the Bit Line BL of the current column is precharged to high level, the Bit Line BLB is low level, after the Word Line WL of the current column is high level, the transistors TN3 and TN4 are turned on, the Bit Line BL is turned on with the Q point, the Q point is high level, and after the inverter composed of the transistors TP2 and TN2 is passed, the QB point value becomes low level, and meanwhile, the discharging speed of the QB point is accelerated due to the Bit Line Bit being low level. This process completes the writing of the Q-point high level and the QB-point low level. In the present embodiment, q=1, qb=0 represents the weight w= +1, and q=0, qb=1 represents the weight w= -1. (note: BL, BLB, WL are omitted in fig. 1,3 and 5 because the BL, BLB, WL associated with the 6T-SRAM memory cell is only related to the weight writing and does not participate in the calculation process).
As shown in fig. 1, the first inverter 7 includes a transistor TL1 and a transistor TL2, wherein a source of the transistor TL1 is connected to the power supply VDD, a gate of the transistor TL1 and a gate of the transistor TL2 are both connected to the Q point, a drain of the transistor TL1 and a drain of the transistor TL2 are both connected to a drain of the transistor TL3, and a source of the transistor TL2 is grounded. The second inverter 8 comprises a transistor TR1 and a transistor TR2, wherein the source electrode of the transistor TR1 is connected with a power supply VDD, the grid electrode of the transistor TR1 and the grid electrode of the transistor TR2 are both connected with a QB point, the drain electrode of the transistor TR1 and the drain electrode of the transistor TR2 are both connected with the drain electrode of the transistor TR3, and the source electrode of the transistor TR2 is grounded. In this embodiment, the transistor TL2 and the transistor TR2 are both NMOS transistors, and the transistor TL1 and the transistor TR1 are both PMOS transistors.
In FIG. 1, the left PMOS transistor TL1 and the NMOS transistor TL2 of the 6T-SRAM memory cell form a first inverter 7, the Q value of the 6T-SRAM is connected to the gates of the transistor TL1 and the transistor TL2, the source of the transistor TL1 is connected to VDD, the source of the transistor TL2 is connected to VSS, the drains of the transistor TL1 and the transistor TL2 are commonly connected to the right end of the NMOS transistor TL3 (i.e., the drain of the transistor TL 3), the left end of the TL3 is a left read bit line (Read Bit Line Left, RBLL for short), and RBLL is connected to the upper end of the capacitor C1 and also connected to the first input end of the differential quantizer. Similarly, the PMOS transistor TR1 and the NMOS transistor TR2 on the right side of the 6T-SRAM memory cell form the second inverter 8, and the QB value of the 6T-SRAM memory cell is connected to the gates of the transistor TR1 and the transistor TR2, the source of the transistor TR1 is connected to VDD, the source of the transistor TR2 is connected to VSS, the drains of the transistor TR1 and the transistor TR2 are commonly connected to the left end of the NMOS transistor TR3 (i.e., the drain of the transistor TR 3), the right end of the transistor TR3 is a right Read Bit LINE RIGHT (RBLR for short), and RBLR is connected to the upper end of the capacitor C2 and also connected to the second input end of the differential quantizer.
The final calculation result is calculated from the voltage difference accumulated at the differential quantizer 6 at the two upper terminals RBLL and RBLR of the coupling capacitors C1 and C2, and the specific truth table and calculation logic are as follows:
The computational logic truth table is shown in table 1:
Table 1 calculate logic truth table
The calculation logic described in table 1, the first column is Input value Input, high level indicates Input 1, low level indicates Input 0, the second column is Weight when q=1, qb=0 indicates weight= +1, and q=0, qb=1 indicates weight= -1, the third column is calculation result, i.e. Input Weight product (Input Weight Product, IWP) where the voltage on RBLR minus the voltage on RBLL is positive indicates ipw= +1, and the voltage on rblr minus the voltage on RBLL is negative indicates ipw= -1. The specific calculation process is as follows:
taking the array of fig. 1 as an example, the coupling capacitor voltage is pre-charged to 0.6V.
The operation diagram of calculating 1× (-1) = -1 is shown in fig. 3, (light part of the circuit in the figure shows non-conduction and non-operation, dark color is conduction and operation, arrow direction is current trend), and the operation process is as follows:
If the input data is 1, the transistor TL3 and the transistor TR3 are both turned on, the weight w= -1, and q=0, so that TL1 and VDD are turned on in the MAC calculation logic on the left side of the 6T-SRAM memory cell, the transistor TL2 is turned off, the upper terminal RBLL of the coupling capacitor C1 is charged by VDD through the turned-on TL1 and TL3, and finally there is a rise in +Δv voltage in RBLL, and qb=1, so that the transistor TR2 and VSS are turned on in the MAC calculation logic on the right side of the 6T-SRAM memory cell, the transistor TR1 is turned off, the upper terminal RBLR of the coupling capacitor C2 is discharged by VSS through the turned-on transistor TR2 and transistor TR3, and finally there is a drop in- Δv in RBLR. The voltage difference V RBLR-VRBLL = (- Δv) - (+Δv) = -2 Δv, and the design provides that the negative voltage difference is a logical negative value of-1, so the process is completed in=1, w= -1, iwp=1× (-1) = -1.
The operation diagram for calculating 1× (+1) = +1 is shown in fig. 4, (in the figure, the light-colored part of the circuit indicates non-conduction and non-operation, the dark color is conduction and operation, and the arrow direction is current trend), and the operation process is as follows:
If the input data is 1, the transistor TL3 and the transistor TR3 are both turned on, the weight w= +1 is q=1, so that the transistor TL2 and VSS are turned on in the MAC calculation logic on the left side of the 6T-SRAM memory cell, the transistor TL1 is turned off, the upper terminal RBLL of the coupling capacitor C1 is discharged from the VSS via the turned-on transistor TL3 and the transistor TL2, and finally the voltage of- Δv decreases in RBLL, and qb=0, so that the transistor TR1 and VDD are turned on in the MAC calculation logic on the right side of the 6T-SRAM memory cell, the transistor TR2 is turned off, the upper terminal RBLR of the coupling capacitor C2 is charged from the VDD via the turned-on transistor TR1 and the transistor TR3, and finally the voltage of +Δv increases in RBLR. The voltage difference V RBLR-VRBLL = (+Δv) - (- Δv) = +2Δv, the design specifies that the positive voltage difference is a logical positive value +1, so the process is completed in=1, w= +1, iwp=1× (+1) = +1.
The operation diagram for calculating 0× (+1/-1) =0 is shown in fig. 5, (the light part of the circuit in the figure indicates non-conduction and non-operation, the dark color is conduction and operation, and the arrow direction is current trend), and the operation process is as follows:
If the input data is 0, then both the transistor TL3 and the transistor TR3 IN the MAC calculation logic are IN the cut-off region, no matter the weight w= +1, or w= -1, the coupling capacitances C1, C2 and VDD, or VSS are all not passing, so there is no voltage ripple on RBLL and RBLR, so V RBLR-VRBLL =0, representing in=0, w= +1/-1, iwp=0.
The above three calculations are multiplication results that may occur for each Cell due to different inputs and weights, and accumulating the multiplication results is realized by sharing the same column of bit lines in the present design. The calculation results of each cell are respectively accumulated in the form of analog voltage at RBLL and RBLR, and finally the voltage difference is calculated by a differential quantizer and quantized into a 5-bit digital value.
Example 2
The invention also provides a single-bit differential SRAM integrated device, which comprises:
The input driving module 1 comprises M data output ends and N bit line output ends, the bit line driving module 2 comprises N bit line output ends and N bit line inversion output ends, the bit line output ends are used for outputting bit lines, the word line driving module 3 comprises M word line output ends, the word line output ends are used for outputting word lines, each memory integrated unit 5 IN an ith row is connected with an ith data output end of the input driving module 1, each memory integrated unit 5 IN the ith row is connected with an ith word line output end of the word line driving module 3, each memory integrated unit 5 IN a jth column is connected with a jth bit line output end of the bit line driving module 2, each memory integrated unit 5 IN the jth column is connected with a bit line output end of the bit line driving module 2, and the memory integrated unit 5 IN the ith row is connected with the ith word line output end of the input driving module 1, the memory integrated unit 5 is equal to or greater than or equal to the positive integer which is equal to or greater than 1, and the positive integer which is equal to or less than the positive integer which is output by 1.
In this embodiment, taking N as 64 and m as 128 as an example, the device structure is shown in fig. 6, and includes 64 integrative arrays 4, and each integrative array 4 includes 128 integrative units 5 (i.e., cells).
The input driving module 1 comprises 128 data output terminals for outputting 128 data, IN0-IN127 respectively.
The bit line driving module 2 includes 64 bit line terminals for outputting 64 bit lines BL0-BL63, respectively, and 64 bit bar terminals for outputting 64 bit bar lines BLB0-BLB63, respectively.
The word line driving module 3 includes 128 word line ends for outputting 128 word lines WL0 to WL127, respectively.
The integrated memory unit 5 of the ith row and the jth column is respectively connected with the ith data output end of the input driving module 1, the ith word line output end of the word line driving module 3, the jth bit line output end of the bit line driving module 2 and the jth inverse bit line output end. The left read bit lines of each bank are denoted by RBLL0-RBLL63, the right read bit lines by RBLR0-RBLR63, and the outputs of the 64 differential quantizers 6 by OUT0[4:0] -OUT64[4:0 ].
The invention discloses a single-bit differential SRAM (Static Random Access Memory, SRAM for short) memory integrated array and device without read-write interference for enlarging quantization margin, which consists of a plurality of memory computing units, wherein the memory computing unit 5 (Cell) consists of 1 6T-SRAM weight storage unit and 2 computing circuits, the computing circuits are symmetrically distributed on two sides of the weight unit, and hardware acceleration can be realized on a neural network with 1bit input and 1bit weight. The product and accumulation of the input and the weight are represented by the charge and discharge of the load capacitance, and the quantized result is determined by the voltage difference of the load capacitance at two sides after the calculation is finished. The final analog calculation result is quantized into a 5-bit digital value to be output through a differential quantizer, and the in-memory calculation device can finish multiply-accumulate calculation of 128 single-bit data and 128 single-bit weights at a time in columns, so that completely parallel vector matrix multiplication is realized in a single period.
The scheme disclosed by the invention has the following advantages:
The in-memory computing unit 5 designed by the invention adopts a classical 6T-SRAM memory cell to store weight values, and utilizes the weight values to control the gates of the transistors TL1, TL2, TR1 and TR2, so that a whole row of memory computing integrated units can be simultaneously computed in the computing process, the weight values are not influenced, and the decoupling operation completely eliminates the read-write interference.
The invention simplifies the operation part IN the memory calculation unit, simplifies half multiplication and accumulation operation amount, realizes multiplication combination of four types IN the traditional memory calculation, namely 1×1=1, 1×0=0, 0×1=0 and 0×0=0, and IN the invention, the input data IN is used for controlling the transistor TL3 and the transistor TR3, the circuit is conducted to perform charge and discharge operation only when the input data in=1, and is not conducted when the input data in=0, and the charge and discharge circuit is IN a holding state, so that the invalid part of multiplying the input data 0 by the weight is omitted, half operation amount is saved, and the power consumption and the calculation speed are greatly improved.
The weight of the invention is represented by a binary value, namely W= -1 or W= +1, when the input data IN=1, the calculation paths on the left side and the right side of the calculation cell always show opposite voltage accumulation effects, and the final calculation result obtained by voltage difference calculation has a larger quantization range than that of single-side charge and discharge, and simultaneously, the requirement on the quantization precision of a differential quantizer is reduced, and the design complexity of a quantization circuit is reduced.
The single cell multiplication calculation effect of the invention is twice of the conventional unilateral calculation voltage difference, so that the quantization pressure of analog-to-digital conversion can be reduced, and the differential quantizer can quantize the multiplication accumulation result more easily.
The design adopts each column to share the coupling capacitor and the differential quantizer, instead of the traditional design that each calculation capacitor is mounted with a small capacitor, a certain area is reduced in the later layout design realization, and meanwhile, the problem of capacitor leakage is also indirectly reduced.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
The principles and embodiments of the present invention have been described herein with reference to specific examples, which are intended to facilitate an understanding of the principles and concepts of the invention and are to be varied in scope and detail by persons of ordinary skill in the art based on the teachings herein. In view of the foregoing, this description should not be construed as limiting the invention.
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| CN114913895B (en) * | 2022-07-19 | 2022-11-01 | 中科南京智能技术研究院 | Memory computing macro unit for realizing two-bit input single-bit weight |
| CN115132244B (en) * | 2022-07-27 | 2025-09-16 | 中科南京智能技术研究院 | Subtracting in-memory computing device |
| CN115691613B (en) * | 2022-12-30 | 2023-04-28 | 北京大学 | A Memristor-Based Charge-type Memory Computing Implementation Method and Its Cell Structure |
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| CN112151091A (en) * | 2020-09-29 | 2020-12-29 | 中科院微电子研究所南京智能技术研究院 | 8T SRAM unit and memory computing device |
| CN112558919A (en) * | 2021-02-22 | 2021-03-26 | 中科院微电子研究所南京智能技术研究院 | Memory computing bit unit and memory computing device |
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| CN113257306B (en) * | 2021-06-10 | 2021-11-26 | 中科院微电子研究所南京智能技术研究院 | Storage and calculation integrated array and accelerating device based on static random access memory |
| CN113255904B (en) * | 2021-06-22 | 2021-09-24 | 中科院微电子研究所南京智能技术研究院 | Voltage margin enhanced capacitive coupling storage and computing integrated unit, sub-array and device |
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| CN112558919A (en) * | 2021-02-22 | 2021-03-26 | 中科院微电子研究所南京智能技术研究院 | Memory computing bit unit and memory computing device |
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