CN114628492A - Transistor with air gap under source/drain regions in bulk semiconductor substrate - Google Patents

Abstract

The present invention relates to transistors with air gaps under source/drain regions in bulk semiconductor substrates. A transistor includes: a bulk semiconductor substrate; and a first source/drain region in the bulk semiconductor substrate separated from a second source/drain region in the bulk semiconductor substrate by a channel region . A first air gap is defined in the bulk semiconductor substrate and below the first source/drain region; a second air gap is defined in the bulk semiconductor substrate and below the second source/drain region. The gate is over the channel region. The spacing between the first air gap and the second air gap is greater than or equal to the length of the channel region such that the first air gap and the second air gap are not below the channel region. The air gap may have a rectangular cross-sectional shape. The air gap reduces the off capacitance of the bulk semiconductor structure to a level close to that of the semiconductor-on-insulator without the disadvantages of the air gap below the channel region.

Description

Transistor with air gap under source/drain regions in bulk semiconductor substrate

technical field

The present disclosure relates to integrated circuits (ICs) and, more particularly, to devices that include an air gap under source/drain regions in a bulk semiconductor substrate to reduce junction capacitance to near the level of a semiconductor-on-insulator (SOI) substrate transistor.

Background technique

Advanced IC manufacturing requires the formation of individual circuit elements, such as transistors such as field effect transistors (FETs), etc., based on a specific circuit design. A FET typically includes a source region, a drain region, and a gate region. The gate region is located between the source and drain regions and controls current flow through the channel region between the source and drain regions. The gate can be composed of various metals, and typically includes a work function metal that is selected to create the desired FET characteristics. The transistors can be formed over a substrate and can be electrically isolated from an insulating dielectric layer, such as an interlayer dielectric (ILD) layer or a high resistance polycrystalline layer. Contacts may be formed to each of the source, drain, and gate regions to electrically connect the transistor to other circuit elements in other metal levels that may be formed after the transistor.

Substrates used to form ICs are generally divided into two categories: bulk semiconductor substrates and semiconductor-on-insulator (SOI) substrates. SOI substrates include layered semiconductor-insulator-semiconductor substrates, replacing more traditional bulk semiconductor substrates. More specifically, SOI substrates include a thin semiconductor-on-insulator (SOI) layer over a buried insulator layer over a base semiconductor layer. SOI substrates are more expensive to manufacture than bulk semiconductor substrates, but generally provide better-performing ICs. For example, bulk semiconductor substrates have higher n-type field effect transistor (NFET) _{offcapacitance} (Coff) due to the relatively large source/drain junction area required. Because of the source/drain junction capacitance, the C _off of bulk semiconductor technology may be about 30% _higher than that of SOI substrates. A method of improving the performance of a bulk semiconductor substrate includes providing an air gap under a channel region of a transistor. However, this approach increases the variability of the transistor's turn-on voltage (ie, its threshold voltage) and creates mechanical stress on the channel region, which makes this approach difficult to use.

SUMMARY OF THE INVENTION

An aspect of the present disclosure relates to a transistor, comprising: a bulk semiconductor substrate; and first source/drain regions in the bulk semiconductor substrate, which are connected to a transistor in the bulk semiconductor substrate through a channel region second source/drain regions are separated; a first air gap defined in the bulk semiconductor substrate and below the first source/drain regions; a second air gap defined in in the bulk semiconductor substrate and under the second source/drain region; and a gate over the channel region, wherein a space between the first air gap and the second air gap The spacing is greater than or equal to the length of the channel region such that the first air gap and the second air gap are not below the channel region.

Another aspect of the present disclosure includes a transistor comprising: a bulk semiconductor substrate; and a first source/drain region in the bulk semiconductor substrate connected to the bulk semiconductor substrate through a channel region the second source/drain regions are separated; a first air gap, which is defined in the bulk semiconductor substrate and in direct contact with the first source/drain region; a second air gap, which is defined in the bulk semiconductor substrate and in direct contact with the second source/drain regions; a gate over the channel region; and a doped polysilicon isolation region in the bulk semiconductor substrate , which extends under the trench isolation and under the gate, the first source/drain region and the second source/drain region, wherein the first air gap and the The second air gaps each have a substantially rectangular cross-sectional shape, and the spacing between the first and second air gaps is greater than or equal to the length of the channel region, such that the first air gaps and the second air gap is not below the channel region.

One aspect of the present disclosure relates to a method comprising: forming a first silicon germanium SiGe section and a second SiGe section spaced apart from the first SiGe section on a bulk semiconductor substrate; forming a silicon layer over the portion and the second SiGe portion; forming a first source/drain region in the silicon layer and a second source/drain region in the silicon layer; forming a first source/drain region in the silicon layer; forming a gate over a channel region between a source/drain region and the second source/drain region; and by removing the first SiGe portion and the second SiGe portion from under the silicon layer part to form a first air gap under the first source/drain region and a second air gap under the second source/drain region, wherein the first air gap and the first air gap The interval between the two air gaps is greater than or equal to the length of the channel region, so that the air gap is not under the channel region.

The above and other features of the present disclosure will become apparent from the following more detailed description of embodiments of the present disclosure.

Description of drawings

Embodiments of the present disclosure will be described in detail with reference to the following drawings, wherein like numerals refer to like elements, and wherein:

1 shows a cross-sectional view of a transistor according to some embodiments of the present disclosure.

2 illustrates a cross-sectional view of a transistor according to further embodiments of the present disclosure.

3 illustrates a cross-sectional view of a transistor according to still further embodiments of the present disclosure.

4 shows a cross-sectional view of an initial structure of a method according to some embodiments of the present disclosure.

5 illustrates a cross-sectional view of forming a silicon germanium portion in accordance with some embodiments of the present disclosure.

6 illustrates a cross-sectional view of forming a silicon layer in accordance with some embodiments of the present disclosure.

7 illustrates a cross-sectional view of forming trench isolation in accordance with some embodiments of the present disclosure.

8 illustrates a cross-sectional view of forming source/drain regions and gates in accordance with some embodiments of the present disclosure.

9 illustrates a cross-sectional view of a silicon germanium portion removed in accordance with some embodiments of the present disclosure.

10 illustrates a cross-sectional view of forming an air gap under source/drain regions in accordance with some embodiments of the present disclosure.

11 illustrates a cross-sectional view of forming trench pairs in accordance with some embodiments of the present disclosure.

12 illustrates a cross-sectional view of forming silicon germanium portions in trench pairs in accordance with some embodiments of the present disclosure.

13 illustrates a cross-sectional view of forming a silicon layer in accordance with some embodiments of the present disclosure.

14 illustrates a cross-sectional view of forming trench pairs according to further embodiments of the present disclosure.

15 illustrates a cross-sectional view of forming a silicon germanium portion and a silicon layer in accordance with some embodiments of the present disclosure.

It should be noted that the drawings of the present disclosure are not necessarily drawn to scale. The drawings are intended to depict only typical aspects of the disclosure, and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like numerals refer to like elements between the drawings.

Detailed ways

In the following description, reference is made to the accompanying drawings which form a part hereof, and in which there are shown by way of illustration specific exemplary embodiments in which the present teachings may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, it being understood that other embodiments may be utilized and changes may be made without departing from the scope of the present teachings. Therefore, the following description is illustrative only.

It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "over" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly on" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

Reference in the specification to "one embodiment" or "an embodiment" of the present disclosure and other variations thereof means that a particular feature, structure, characteristic, etc. described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases "in one embodiment" or "in an embodiment" and any other variations appearing in various places in the specification are not necessarily all referring to the same embodiment. It should be understood that, for example, in the context of "A/B", "A and/or B" and "at least one of A and B" the use of "/", "and/or" and "at least one of" Either is intended to involve selecting only the first listed option (a), or only the second listed option (B), or both options (A and B). As other examples, in the context of "A, B, and/or C" and "at least one of A, B, and C," these phrases are intended to include selecting only the first listed option (A), or Select only the second listed option (B), or only the third listed option (C), or only the first and second listed options (A and B), or only The first and third listed options (A and C), or only the second and third listed options (B and C), or all three options (A and B and C) ). As will be apparent to those of ordinary skill in the art, this situation can be extended to many of the items listed.

Embodiments of the present disclosure provide a transistor including a bulk semiconductor substrate and a first source/drain region in the bulk semiconductor substrate, the first source/drain region being connected to the bulk semiconductor substrate through a channel region The second source/drain regions in the bottom are separated. A first air gap is defined in the bulk semiconductor substrate under the first source/drain region, and a second air gap is defined in the bulk semiconductor substrate under the second source/drain region. The gate is over the channel region. The spacing between the first air gap and the second air gap is greater than or equal to the length of the channel region such that the first air gap and the second air gap are not below the channel region. The air gap may have a rectangular cross-sectional shape. The air gap reduces the off capacitance of the bulk semiconductor structure to a level close to that of the semiconductor-on-insulator, and does not have the disadvantage of the air gap under the channel region. The source/drain regions have a thickness within the range of the SOI layer of the SOI substrate.

1 shows a cross-sectional view of a pair of adjacent transistors 100, 101 in accordance with an embodiment of the present disclosure. These transistors 100, 101 may form a single multi-finger transistor or two separate transistors. For descriptive purposes, only one transistor 100 (on the left) will be described herein, the other transistor 102 (on the right) is typically a mirror image of the one and they may share the source/drain regions in the middle. Transistor 100 includes a semiconductor substrate 102, which in the illustrative embodiment is a bulk semiconductor substrate rather than a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 102 may include, but is not limited to, silicon, germanium, silicon germanium, silicon carbide, and materials consisting essentially of one or more III-V compound semiconductors having the chemical formula _{AlX1GaX2 .} In _X3 As _Y1 P _Y2 N _Y3 Sb _Y4 defines the composition, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions greater than or equal to zero, respectively, and X1+X2+X3+Y1+Y2+Y3+ Y4=1 (1 is the total relative molar amount). Other suitable substrates include II-VI compound semiconductors with compositions Zn _A1 Cd _A2 Se _B1 Te _B2 , where A1, A2, B1, and B2 are relative ratios greater than or equal to zero, respectively, and A1+A2+B1+B2=1 (1 is the total molar amount). In addition, a portion or the entirety of substrate 102 may be strained.

The transistor 100 also includes a first source/drain region 110 in the bulk semiconductor substrate 102 which is connected to a second source/drain region in the bulk semiconductor substrate 102 through a channel region 114 The pole regions 112 are separated. The source/drain regions 110, 112 may include any suitable dopants.

Gate 120 is located over channel region 114 . The gate 120 may comprise any now known or later developed gate material. In one non-limiting example, gate 120 may comprise polysilicon. In another example, the gate 120 may include a metal gate. Although shown as a single material for clarity, the metal gate may include one or more conductive components used to provide the gate terminal of the transistor. For example, a metal gate may include a high dielectric constant (high K) layer, a work function metal layer, and a gate conductor (not all shown for clarity). The high-K layer may comprise any now known or later developed high-K material commonly used for metal gates, such as, but not limited to, such as tantalum _oxide ( _Ta2O5 ), barium titanium oxide (BaTiO3 ₎ , hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), metal oxides such as aluminum oxide (Al ₂ O ₃ ), or hafnium oxysilicate (Hf _A1 Si _A2 O _A3 ) or hafnium oxynitride silicate (Hf Metal silicates such as _A1 Si _A2 O _A3 N _A4 ), where A1, A2, A3 and A4 represent relative proportions, respectively greater than or equal to zero and A1+A2+A3+A4 (1 being the total relative molar amount). Depending on whether it is used for an NFET device or a PFET device, the work function metal layer may include various metals, but may include, for example: aluminum (Al), zinc (Zn), indium (In), copper (Cu), indium copper (InCu) , Tin (Sn), Tantalum (Ta), Tantalum Nitride (TaN), Tantalum Carbide (TaC), Titanium (Ti), Titanium Nitride (TiN), Titanium Carbide (TiC), TiAlC, TiAl, Tungsten (W) , tungsten nitride (WN), tungsten carbide (WC), polysilicon (polySi), and/or combinations thereof. The gate conductor may comprise any now known or later developed gate conductor, such as copper (Cu). A gate cap (not shown), eg, made of nitride, may also be formed over the gate region. The gate 120 may also include a spacer 122 around it, for example composed of silicon nitride.

Transistor 100 may also include any form of trench isolation 124 located in bulk semiconductor substrate 102 and surrounding first source/drain region 110 and second source/drain region 112 . As understood in the art, trench isolation 124 may isolate one region of substrate 102 from adjacent regions of substrate 102 . One or more transistors of a given polarity may be disposed in regions isolated by trench isolation 124 . Each trench isolation 124 may be formed of any now known or later developed substance for providing electrical isolation, which may include, for example: silicon _nitride (Si3N4 ₎ , silicon oxide ( _SiO2 ), fluorinated SiO ₂ (FSG), hydrogenated silicon oxycarbide (SiCOH), porous SiCOH, borophosphosilicate glass (BPSG), silsesquioxane, including silicon (Si), carbon (C), oxygen (O) and/or Carbon (C) doped oxides of hydrogen (H) atoms (ie organosilicates), thermosetting polyarylene ethers, spin-coated silicon-containing carbon polymer materials, near frictionless carbon (NFC) or multilayers thereof .

In one embodiment, transistor 100 may also include a doped polysilicon isolation region 130 in bulk semiconductor 102 and extending below gate 120 , first source/drain region 110 and second source/drain region 112 . Isolation regions 130 may extend between the sides of trench isolation 124 . The doped polysilicon isolation regions 130 may include any dopant capable of forming insulating polysilicon in the substrate 102 (eg, argon). As understood in the art, doped polysilicon isolation regions 130 provide high resistivity electrical isolation for transistor 100 . FIG. 2 shows a cross-sectional view of another embodiment in which the doped polysilicon isolation regions 130 are omitted.

Transistor 100 includes a first air gap 140 defined in bulk semiconductor substrate 102 and below first source/drain region 110, and a second source/drain defined in bulk semiconductor substrate 102 The second air gap 142 below the region 112 . Air gaps 140, 142 are cavities or voids in the material of transistor 100 that act as gaseous dielectrics. The spacing S between the first air gap 140 and the second air gap 142 is greater than or equal to the length L of the channel region 114 such that the first and second air gaps 140 , 142 are not below the channel region 114 . In FIGS. 1 and 2 , the sides of the first air gap 140 and the second air gap 142 are aligned with the edges of the gate 120 and the channel 114 such that the spacing S is equal to the length L of the channel region 114 . Alternatively, as shown in FIG. 3 , the sides of the first air gap 140 and the second air gap 142 may not be aligned with the edges of the gate 120 and the channel 114 such that the spacing S is greater than the length L of the channel region 114 . FIG. 3 shows transistor 100 including doped polysilicon isolation regions 130 , but the doped polysilicon isolation regions may be omitted as in FIG. 2 .

The first air gap 140 is in direct contact with the first source/drain region 110 , and the second air gap 142 is in direct contact with the second source/drain region 112 . Furthermore, the first air gap 140 and/or the second air gap 142 may adjoin the trench isolation 124 , ie, have their ends in direct contact with the trench isolation 124 . In FIGS. 1-3 , only the first air gap 140 is shown adjoining the trench isolation 124 ; however, it will be appreciated that if the transistor 101 were omitted, the second air gap 142 would adjoin the trench isolation 124 . Furthermore, due to the method of forming the air gap, as will be further described herein, the first air gap 140 and the second air gap 142 each have a substantially rectangular cross-sectional shape. The air gaps 140 , 142 may be formed without a liner therein such that the inner surface 148 of each of the first air gap 140 and the second air gap 142 is the same material as the bulk semiconductor substrate 102 .

As will be described herein, the silicon layer 150 in which the first source/drain regions 110 and the second source/drain regions 112 are formed may have a thickness in the range of 30 to 50 nanometers. This thickness is determined in part by the thickness of the air gaps 140, 142 and the materials used to form them. The silicon layer 150 may have a thickness similar to a semiconductor-on-insulator (SOI) layer of an SOI substrate, and may provide an SOI substrate that uses air gaps 140, 142 and optional doped polysilicon isolation regions 130 instead of a buried insulator layer. similar performance.

For reasons that will become apparent herein, transistor 100 may also include filled vias 156 extending through each of first source/drain region 110 and second source/drain region 112 . Filled vias 156 may be filled with oxide liners and spacer nitrides, for example. Each source/drain region 110 , 112 may also include a suicide 158 thereon for coupling to a contact (not shown) through an interlayer dielectric (ILD) 160 . Any technique now known or later developed, such as performing in-situ pre-cleaning, depositing metals such as titanium, nickel, cobalt, etc., performing annealing to react the metal with the silicon, and then removing unreacted metal, can be used to Silicide 158 is formed. ILD 160 may be deposited and include materials such as, but not limited to, the following: carbon doped silica materials; fluorinated silicate glass (FSG); organic polymer thermosets; silicon oxycarbide; SiCOH dielectrics; fluorine doped Silica; spin-on glass; silsesquioxane, including hydrogen silsesquioxane (HSQ), methylsilsesquioxane (MSQ), and mixtures or copolymers of HSQ and MSQ; based on benzo rings Polymer dielectrics of butene (BCB), and any silicon-containing low-k dielectrics. Examples of spin-coated low-k films with SiCOH-type compositions using silsesquioxane chemistry include HOSP ^™ (available from Honeywell), JSR 5109 and 5108 (available from Japan Synthetic Rubber), Zirkon ^™ (available from Shipley Microelectronics) Rohm and Haas Division), and porous low-k (ELk) materials (available from Applied Materials). Examples of carbon-doped silica materials or organosilanes include Black Diamond ^™ (available from Applied Materials) and Coral ^™ (available from Lam Research). An example of a HSQ material is FOx ^™ (available from Dow Corning).

"Deposition" may include any now known or later developed technique suitable for the material to be deposited, including but not limited to, for example, chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), Subatmospheric Pressure CVD (SACVD) and High Density Plasma CVD (HDPCVD), Rapid Thermal CVD (RTCVD), Ultra High Vacuum CVD (UHVCVD), Limited Reaction Processing CVD (LRPCVD), Metal Organic CVD (MOCVD), Sputter Deposition, Ion Beam Deposition, Electron Beam Deposition, Laser Assisted Deposition, Thermal Oxidation, Thermal Nitriding, Spin Coating, Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), Chemical Oxidation, Molecular Beam Epitaxy (MBE), Plating, evaporation. ILD 160 may be deposited using ALD, for example.

It will be appreciated that transistor 101 may comprise a similar structure as transistor 100 . In other embodiments, the transistor 101 may be omitted. As shown, in the presence of the transistor pair 100, 101, a third air gap 162 under the other source/drain region 180 may be provided.

Referring to FIGS. 4-15 , according to some embodiments of the present disclosure, the transistor 100 may be formed according to various methods. 4-10 illustrate embodiments in which the sides of the air gaps 140 , 142 may not be aligned with the source/drain regions 110 , 112 . 11-15 illustrate cross-sectional views of embodiments of processes in which the sides of the air gaps 140 , 142 are aligned with the source/drain regions 110 , 112 .

FIG. 4 shows a cross-sectional view of one embodiment of the initial structure 166 in accordance with embodiments of the present disclosure. As described herein, initial structure 166 may include bulk semiconductor substrate 102 . FIG. 4 also illustrates the formation of trench isolations 124 in the bulk semiconductor substrate 102 . Here, trenches 126 may be etched in substrate 102 using, for example, a mask (not shown) and filled with an insulating material, such as oxide, to connect a region of the substrate with a phase in the substrate. Neighboring areas are isolated. Trench isolation 124 surrounds the area in which transistor 100 will be built. Any of the trench isolation 124 materials listed herein may be used. Alternatively, appropriate doped wells can be used as isolation.

Etching generally refers to the removal of material from a substrate (or structures formed on a substrate) and is usually performed with a mask in place to selectively remove material from specific areas of the substrate while allowing Materials in other areas of the substrate are not affected. There are generally two types of etching: (i) wet etching and (ii) dry etching. Wet etching is performed using a solvent (eg, acid), which can be selected for its ability to selectively dissolve a given material (eg, oxide) while leaving another material (eg, polysilicon) relatively intact. This ability to selectively etch a given material underlies many semiconductor manufacturing processes. Wet etching typically etches homogeneous materials (eg oxides) isotropically, but wet etching can also anisotropically etch single crystal materials (eg silicon wafers). Dry etching can be performed using plasma. The plasma system can operate in several modes by adjusting the plasma parameters. Ordinary plasma etching produces neutrally charged energetic radicals that react at the wafer surface. The process is isotropic as neutrals attack the wafer from all angles. Ion milling or sputter etching bombards the wafer with energetic ions of a noble gas that approach the wafer from roughly one direction, so the process is highly anisotropic. Reactive ion etching (RIE), operating at conditions intermediate between sputtering and plasma etching, can be used to create deep and narrow features, such as trenches 126 for trench isolation 124 .

FIG. 4 also illustrates the optional formation of doped polysilicon isolation regions 130 in the bulk semiconductor substrate 102 . The doped polysilicon isolation regions 130 may be formed in any manner now known or later developed, such as, but not limited to, argon doping with sufficient dose and intensity to the desired depth in the substrate 102 such as by ion implantation and annealing form an isolation area. See US Patent 10,192,779. Any form of nitride cap (not shown) may be used to control the positioning and shape of isolation regions 130 . As shown in one non-limiting example in FIGS. 1 and 3 , the doping is formed in the bulk semiconductor substrate 102 in the first source/drain region 110 , the second source/drain region 112 , the gate 120 , the doped polysilicon isolation region 130 extending below the first air gap 140 and the second air gap 142 . Other arrangements of isolation regions 130 are also possible.

5 illustrates a cross-sectional view of forming a first silicon germanium (SiGe) portion 170 and a second SiGe portion 172 spaced apart from the first SiGe portion 170 on the bulk semiconductor substrate 102 . A third SiGe portion 174 spaced apart from the second SiGe portion 172 may also be formed. In this embodiment, a mask 168 (eg, a nitride hard mask) is patterned over the bulk semiconductor substrate 102, exposing portions of the substrate. Each SiGe portion 170 , 172 , 174 may be selectively epitaxially grown in exposed portions of the substrate according to the guidance of the patterned mask 168 on the substrate 102 . The terms "epitaxial growth" and "epitaxial formation and/or growth" refer to the growth of a semiconductor material, such as silicon, on a deposition surface of semiconductor material, wherein the grown semiconductor material may have the same crystalline properties as the semiconductor material of the deposition surface. During epitaxial growth, the chemical reactants provided by the source gases are controlled and the system parameters are set such that the deposited atoms reach the deposition surface of the semiconductor substrate with sufficient energy to move across the surface and orient themselves for deposition The crystalline arrangement of atoms on the surface. The addition of germanium (Ge) can be turned on during the epitaxial growth process to form SiGe, eg, SiGe has a Ge content of up to 20% by weight. Alternatively, the addition of germanium (Ge) can be turned off during the epitaxial growth process, thereby forming pure silicon. The thickness and width of the SiGe portions 170 , 172 , 174 determine the thickness and width of the air gaps 140 , 142 . The SiGe portions 170, 172 are positioned laterally and their widths match as closely as possible the widths of the source/drain regions 110, 112 to be formed over them. The SiGe portions 170, 172, 174 may have widths commensurate with, for example, the desired source/drain region widths and channel lengths of the particular technology node employed. In one non-limiting example, for the 14nm technology node, the width may be 360-400 nanometers, or the width may be 560-600 nanometers, or any width in between these ranges. The SiGe portions 170, 172, 174 may have a thickness of, for example, 10-30 nm.

6 shows a cross-sectional view of the formation of silicon layer 150 over first SiGe portion 170 and second SiGe portion 172 (and third SiGe portion 174, if provided). Here, mask 168 is first removed using any suitable ashing process (eg, a thermal phosphorous process). Silicon layer 150 may then be selectively epitaxially grown from bulk semiconductor substrate 102 and SiGe portions 170 , 172 , 174 . The silicon layer 150 may have any thickness desired for the source/drain regions 110 , 112 . In one embodiment, even though the transistor 100 is formed on the bulk semiconductor substrate 102, the thickness of the silicon layer 150 over the SiGe portions 170, 172, 174 is made close to the thickness of the SOI layer in the SOI substrate to obtain a similar performance at the bottom. In one non-limiting example, the silicon layer 150 may have a thickness in the range of 30 to 50 nanometers.

FIG. 6 also shows that trench isolation 124 is extended to be coplanar with silicon layer 150 . Here, additional trench isolation 124X is formed over trench isolation 124 to bring the trench isolation to the same height as silicon layer 150 . Any necessary planarization can be performed to make the surfaces coplanar.

In an alternative embodiment, as shown in the cross-sectional view of FIG. 7 , the optional doped polysilicon isolation region 130 formation of FIG. 4 and the processes of FIGS. 5 and 6 may be performed before trench isolation 124 is formed. In this case, patterned mask 168 (FIG. 5) is used to expose portions of substrate 102, and first and second SiGe portions 170, 172 (FIG. 6) and third SiGe portion 174 (if provided) are epitaxially grown if). Mask 168 is then removed, and silicon layer 150 is epitaxially grown as described with respect to FIG. 6 . In this case, the silicon layer 150 grows from the substrate 102 and the SiGe portions 170, 172, 174 in a non-selective manner since the trench isolation 124 is not initially present. Next, as shown in FIG. 7, trench isolation 124 may be formed in bulk semiconductor substrate 102 to be coplanar with silicon layer 150, eg, using pad oxide and pad nitride masks to etch the trenches, Oxide deposition and planarization (not shown) are performed. Thus, trench isolation 124 includes a single structure, eg, a single structure of oxide. Also with regard to trench isolation, the embodiment of FIG. 7 is shown in FIG. 1 , and the embodiment of FIG. 6 is shown in FIGS. 2 and 3 . The subsequent processing of FIGS. 1 to 3 is explained based on the embodiment of FIG. 7 .

FIG. 8 shows a cross-sectional view of forming first source/drain regions 110 in silicon layer 150 and second source/drain regions 112 in silicon layer 150 . FIG. 8 also shows that gate 120 is formed over channel region 114 between first source/drain region 110 and second source/drain region 112 . Gate 120 and source/drain regions 110, 112 (and second gate 120 and third source/drain regions 180) may be formed using any now known or later developed process. In one non-limiting example, the gate 120 material may be deposited and patterned using photolithography, wherein the source/drain regions 110, 112, 180 are formed by doping the silicon layer 150 with appropriate dopants (eg, , using ion implantation) and performing an anneal to drive the dopant to form. The dopants used can vary depending on the type of transistor to be formed. The gates 120 may comprise dummy gate material, such as sacrificial material to be replaced by final gate material after the source/drain regions are formed, or they may comprise final gate material, such as polysilicon or metal gates Material.

FIG. 9 shows the formation of a first SiGe portion 170 and a second SiGe portion 172 below the first source/drain region 110 by removing the first SiGe portion 170 and the second SiGe portion 172 from below the silicon layer 150 (now including the source/drain regions 110, 112). A cross-sectional view of an air gap 140 and the second air gap 142 formed under the second source/drain region 112 . The formation of air gaps 140, 142 under the first and second source/drain regions 110, 112 may include forming through the first and second source/drain regions 110, 112 (and source/drain regions 180, if provided) vias 184. The vents 184 may be formed using any now known or later developed process, eg, forming a patterned mask with small openings that match the locations of the vents 184, and etched (eg, RIE). 9 also shows the etching and removal of SiGe layers 170, 172 (and 174 (FIG. 8)) through vent 184, eg, using hot ammonia ( _NH3 ) and/or hydrochloric acid, as is known in the art. After removal of the SiGe layers 170, 172, 174, an optional thermal oxidation may be performed to passivate the air gap semiconductor surfaces. Removal of the SiGe portion leaves gas, such as air, in the space.

FIG. 10 shows a cross-sectional view of sealing vent 184 ( FIG. 9 ) to form first and second air gaps 140 , 142 (and third air gap 162 , if desired) and filling vent 156 . This can be achieved, for example, by thermally oxidizing vias (shown) or depositing a dielectric such as nitride and/or spacer nitride (which also forms gate spacers 122), or by depositing borophosphosilicate glass (BPSG). Perform sealing. It should be noted that the vents 184 have a sufficiently small lateral dimension (across or into the page in Figure 9), as described above, not to adversely affect the source as compared to the source/drain regions 110, 112 that seal them Electrical properties of the electrode/drain regions. As described above, the first air gap 140 and the second air gap 142 each have a substantially rectangular cross-sectional shape due to the shape of the SiGe portion. In an embodiment, the spacing S between the first air gap 140 and the second air gap 142 is greater than or equal to the length L of the channel region 114 such that the air gaps 140 , 142 are not below the channel region 114 .

FIGS. 1-3 illustrate the processing after silicide 158 is formed over source/drain regions 110 , 112 , 180 . Silicide 158 may be formed using any now known or later developed technique, for example, performing in-situ precleaning, depositing metals such as titanium, nickel, cobalt, platinum, etc., performing annealing to align the metal with the source/drain The silicon of the pole regions 110, 112 reacts and unreacted metal is removed. The ILD 160 may be formed over and any desired interconnects, such as contacts and wiring (not shown), may be formed through the ILD 160 in a known manner.

In the embodiments of FIGS. 5-10, SiGe portions 170, 172, 174 are not formed in alignment with source/drain regions 110, 112, 180, thus possibly resulting in air gaps 140, 142 not being aligned with source/drain regions 110, 112, 180 The drain regions 110 are aligned, where the spacing S may be approximately equal to but more likely greater than the length L of the channel regions 114 . The spacing S greater than the length L of the channel region 114 is shown in an exaggerated manner in FIG. 3 .

11-14 illustrate cross-sectional views of embodiments in which air gaps 140 , 142 are formed in alignment with source/drain regions 110 , 112 . That is, as shown in FIGS. 1 and 2 , the sides of the first air gap 140 and the second air gap 142 are aligned with the edges of the gate electrode 120 such that the spacing S therebetween is equal to the length L of the channel region 114 . As will be described, in these embodiments, trench isolations 124 may be formed in bulk semiconductor substrate 102 prior to forming first SiGe portion 170 and second SiGe portion 172 . Each of the air gaps 140 , 142 may adjoin the trench isolation 124 .

11 shows a cross-sectional view where processing begins in FIG. 4 and gate 120 is formed prior to forming first SiGe portion 170 and second SiGe portion 172 and forming silicon layer 150, as described in previous embodiments. As described herein, gate 120 may be formed over bulk semiconductor substrate 102 in any manner. FIG. 11 also shows the formation of pairs of trenches 190 adjacent to gates 120 in bulk semiconductor substrate 102 . Another trench 190 may also be provided in the case where the two gate electrodes 120 are formed adjacent to each other. Hardmask 192 may be formed over trench isolation 124 and/or gate 120 and an etch such as RIE performed to open trench 190 . The trenches 190 extend in the substrate 102 to a desired depth to the bottom of the air gaps 140, 142 (FIGS. 1-3).

12 shows a cross-sectional view of epitaxially growing a first SiGe portion 170 and a second SiGe portion 172 in a pair of trenches 190 (and epitaxially growing a third SiGe portion 174 in another trench 190, if provided). In an embodiment, the first SiGe portion 170 is epitaxially grown selectively for source/drain transistor regions. 13 shows a cross-sectional view of epitaxially grown silicon layer 150 over first SiGe portion 170 and second SiGe portion 172 and third SiGe portion 174 (if provided) in pair of trenches 190 (Fig. 11). Processing from this point on may proceed as described with respect to FIGS. 1-3 and 8-10, such as gate 120 formation, first and second source/drain regions 110, 112 formation, and gas Gaps 140, 142 are formed. As shown in FIGS. 1 and 2 , the sides of the first air gap 140 and the second air gap 142 are aligned with the edges of the gate 120 such that the spacing S is equal to the length L of the channel region 114 .

FIG. 14 shows cross-sectional views of further embodiments in which the sides of the air gaps 140 , 142 are formed in alignment with the edges of the source/drain regions 110 , 112 . In this embodiment, gates 120 are not used to form pairs of trenches 190 (FIG. 11), but masks 200 are used. Here, the gate 120 is formed after the SiGe portions 170 , 172 , 174 . FIG. 14 shows a cross-sectional view in which processing is started from FIG. 4 . At this stage, trench isolations 124 are formed in bulk semiconductor substrate 102 , and mask 200 is used to form pairs of trenches 202 in bulk semiconductor substrate 102 . A mask 200 (eg, a nitride hard mask) is patterned over the bulk semiconductor substrate 102 to expose portions of the bulk semiconductor substrate 102 that require the air gaps 140 , 142 . Pairs of trenches 202 are formed in bulk semiconductor substrate 102 adjacent gate 120 by etching using mask 200 . Another trench 202 may also be provided where the three portions are exposed by the mask 200 . Etching may include, for example, RIE. The trenches 202 extend in the substrate 102 to a desired depth to the bottom of the air gaps 140, 142 (FIGS. 1-3).

FIG. 15 shows that after mask 200 (FIG. 14) is removed (eg, by any suitable ashing process), first SiGe portion 170 and second SiGe portion 172 are epitaxially grown in trench 202, and then first SiGe portion 172 is epitaxially grown in trench 202. Cross-sectional view after epitaxial growth of silicon layer 150 (in trench 202 ( FIG. 14 )) over portion 170 and second SiGe portion 172 . Subsequent processing of this embodiment may be performed in a similar manner as described with respect to FIGS. 1-3 and 8-10 to achieve the transistor 100 in FIGS. 1-3 .

Embodiments of the present disclosure provide a transistor 100 that exhibits reduced junction capacitance even though the transistor is built into the bulk semiconductor substrate 102 due to the presence of the air gaps 140 , 142 . The air gaps 140 , 142 have a rectangular cross-sectional shape and extend under the source/drain regions 110 , 112 but not under the channel region 114 . In certain embodiments, the sides of the air gaps 140 , 142 are aligned with the edges of the gate 120 and channel 114 . Although SOI substrates typically have about 50% lower drain-to-source capacitance (C _DS ) than bulk semiconductor substrates due to the buried insulator layer, the air gaps 140 , 142 under the source/drain regions 110 , 112 reduce C _DS in the bulk semiconductor substrate 102 . The thickness of the source/drain regions 110, 112 can also be configured to be similar to that of the SOI substrate, eg, about 80 nm. The reduction in C _DS caused by the air gaps 140, 142 under the source/drain regions 110, 112 can be up to about 50%, which can reduce the off capacitance (C _off ) by up to 25% to approximate or match the SOI substrate the value in . Although the air gaps 140, 142 provide this advantage, they are not located under the channel region 114, thus eliminating any mechanical stress caused by this arrangement.

The above method is used in the manufacture of integrated circuit chips. The resulting integrated circuit chips may be distributed by the manufacturer in raw wafer form (ie, as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chips are in a single-chip package (eg a plastic carrier with leads attached to a motherboard or other higher level carrier) or a multi-chip package (eg a ceramic carrier with surface interconnects and/or buried interconnects) ) is installed. In any case, the chip is then integrated with other chips, discrete circuit elements and/or other signal processing devices as part of (a) an intermediate product (eg, a motherboard) or (b) an end product. The final product can be anything including integrated circuit chips, from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that when used in this specification, the terms "comprising" and/or "comprising" specify the presence of stated features, integers, steps, operations, elements and/or parts, but do not exclude one or more other features , integers, steps, operations, elements, parts, and/or the presence or addition of groups thereof. "Optional" or "optionally" means that the subsequently described event or circumstance may or may not occur, and that the description includes instances where the event occurs and instances where it does not.

Approximate language used throughout the specification and claims can be used to modify any quantitative representation that can be allowed to vary without causing a change in the basic function with which it is associated. Thus, a value modified by one or more terms such as "about", "approximately" and "substantially" is not limited to the precise value specified. In at least some cases, the language of approximation may correspond to the precision of the instrument used to measure the value. Range limitations may be combined and/or interchanged herein and throughout the specification and claims, such ranges are identified and include all sub-ranges subsumed therein unless context or language dictates otherwise. "Approximate" applied to a particular value of a range applies to both values, and may indicate +/- 10% of the stated value unless otherwise dependent on the precision of the instrument by which the value is measured.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or to limit the disclosure to the form disclosed. Numerous modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of this disclosure. The embodiment was chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others skilled in the art to understand the disclosure for various embodiments with various modifications as are suited to the particular use contemplated.

Claims (20)

1. A transistor comprising: bulk semiconductor substrate; a first source/drain region in the bulk semiconductor substrate separated from a second source/drain region in the bulk semiconductor substrate by a channel region; a first air gap defined in the bulk semiconductor substrate below the first source/drain region; a second air gap defined in the bulk semiconductor substrate below the second source/drain region; and the gate above the channel region, wherein the interval between the first air gap and the second air gap is greater than or equal to the length of the channel region, so that the first air gap and the second air gap are not under the channel region . 2. The transistor of claim 1, wherein the first air gap and the second air gap are aligned with the gate such that the spacing is equal to the length of the channel region. 3. The transistor of claim 1, wherein the first air gap is in direct contact with the first source/drain region, and the second air gap is in direct contact with the second source/drain region direct contact. 4. The transistor of claim 1, wherein the first air gap and the second air gap each have a substantially rectangular cross-sectional shape. 5. The transistor of claim 1, further comprising: trench isolation in the bulk semiconductor substrate and surrounding the first source/drain region and the second source/drain region; and a doped polysilicon isolation region in the bulk semiconductor substrate at the gate, the first source/drain region, the second source/drain region, the first air gap and extending below the second air gap, wherein the first air gap and the second air gap are isolated adjacent to the trench. 6. The transistor of claim 1, wherein the first source/drain region and the second source/drain region have a thickness in the range of 30 to 50 nanometers. 7. The transistor of claim 1, wherein an inner surface of each of the first air gap and the second air gap is the same material as the bulk semiconductor substrate. 8. The transistor of claim 1, further comprising a filled via extending through each of the first source/drain region and the second source/drain region. 9. A transistor comprising: bulk semiconductor substrate; a first source/drain region in the bulk semiconductor substrate separated from a second source/drain region in the bulk semiconductor substrate by a channel region; a first air gap defined in the bulk semiconductor substrate and in direct contact with the first source/drain region; a second air gap defined in the bulk semiconductor substrate and in direct contact with the second source/drain region; a gate over the channel region; and a doped polysilicon isolation region in the bulk semiconductor substrate at the gate, the first source/drain region, the second source/drain region, the first air gap and extending below the second air gap, wherein the first air gap and the second air gap each have a substantially rectangular cross-sectional shape, and the spacing between the first air gap and the second air gap is greater than or equal to the channel region , so that the first air gap and the second air gap are not under the channel region. 10. The transistor of claim 9, wherein sides of the first and second air gaps are aligned with edges of the gate such that the spacing is equal to the length of the channel region . 11. A method comprising: forming a first silicon germanium SiGe portion and a second SiGe portion spaced apart from the first SiGe portion on a bulk semiconductor substrate; forming a silicon layer over the first SiGe portion and the second SiGe portion; forming first source/drain regions in the silicon layer and second source/drain regions in the silicon layer; forming a gate over the channel region between the first source/drain region and the second source/drain region; and A first air gap under the first source/drain region and the second source/drain are formed by removing the first SiGe portion and the second SiGe portion from under the silicon layer the second air gap below the polar region, The interval between the first air gap and the second air gap is greater than or equal to the length of the channel region, so that the air gap is not below the channel region. 12. The method of claim 11, further comprising: Doping is performed to form doped polysilicon isolation regions in the bulk semiconductor substrate, the doped polysilicon isolation regions in the first source/drain region, the second source/drain region, the The gate, the first air gap and the second air gap extend below. 13. The method of claim 11, wherein sides of the first and second air gaps are aligned with edges of the gate such that the spacing is equal to the length of the channel region . 14. The method of claim 11, wherein the first air gap and the second air gap each have a substantially rectangular cross-sectional shape. 15. The method of claim 11, wherein the underside of the first source/drain region is formed by removing the first portion and the second portion of SiGe from under the silicon layer The first air gap and the second air gap under the second source/drain region include: forming vias through the first source/drain region and the second source/drain region; performing an etch through the via hole to remove the first SiGe portion and the second SiGe portion; and The vent hole is sealed to form the first air gap and the second air gap. 16. The method of claim 11, further comprising forming trench isolation in the bulk semiconductor substrate prior to forming the first SiGe portion and the second SiGe portion, wherein the first air gap and Each of the second air gaps abuts the trench isolation. 17. The method of claim 11, wherein forming the silicon layer prior to forming the first SiGe portion and the second SiGe portion and forming the silicon layer over the first SiGe portion and the second SiGe portion The gate, and forming the first SiGe portion and the second SiGe portion and forming the silicon layer over the first SiGe portion and the second SiGe portion include: forming a pair of trenches in the bulk semiconductor substrate adjacent to the gate; epitaxially growing the first SiGe portion and the second SiGe portion in the trench pair; and epitaxially growing the silicon layer over the first SiGe portion and the second SiGe portion in the pair of trenches, wherein sides of the first and second air gaps are aligned with edges of the gate such that the spacing is equal to the length of the channel region. 18. The method of claim 11, wherein forming the first SiGe portion and the second SiGe portion and forming the silicon layer over the first SiGe portion and the second SiGe portion occurs at a before forming the gate over the channel region. 19. The method of claim 18, wherein forming the first SiGe portion and the second SiGe portion and forming the silicon layer over the first SiGe portion and the second SiGe portion comprises: patterning a mask over the bulk semiconductor substrate, the mask exposing a portion of the bulk semiconductor substrate; epitaxially growing the first SiGe portion and the second SiGe portion over the exposed portion; removing the mask; and The silicon layer is epitaxially grown over the first SiGe portion and the second SiGe portion and the bulk semiconductor substrate. 20. The method of claim 18, wherein forming the first SiGe portion and the second SiGe portion and forming the silicon layer over the first SiGe portion and the second SiGe portion comprises: forming pairs of trenches in the bulk semiconductor substrate; epitaxially growing the first SiGe portion and the second SiGe portion in the trench pair; and The silicon layer is epitaxially grown over the first SiGe portion and the second SiGe portion in the pair of trenches.

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