CN114640346A - Multi-level digital precision time delay control method and system for optical fiber time transfer - Google Patents

Abstract

The invention discloses a multi-level digital precision time delay control method and system for optical fiber time transfer. The method includes: step 1, obtaining an initial delay control amount; step 2, obtaining an FPGA shift based on the initial delay control amount The integer multiple clock cycle of the phase is compensated according to the integer multiple clock cycle of the FPGA phase shift; Step 3, determine whether the update delay control amount is within the preset threshold range; 5; Step 4, obtain the integer multiple clock cycle of the FPGA phase shift based on the update delay control amount, perform compensation according to the integer multiple clock cycle of the FPGA phase shift, and jump to perform step 3; Step 5, according to the update delay control amount Adopt The DPLL performs phase shifting. Through the combination of FPGA technology and DPLL phase shifting technology, the invention can realize the coarse adjustment and fine adjustment of the phase delay, and can realize the multi-level digital precise delay control of the large-scale delay.

Description

Multi-level digital precision time delay control method and system for optical fiber time transfer

technical field

The invention belongs to the technical field of optical fiber time transfer, and in particular relates to a multi-stage digital precise time delay control method and system for optical fiber time transfer.

Background technique

Optical fiber time transfer has gradually become an important method of high-precision time transfer at home and abroad due to its obvious stability and security advantages such as stable transmission medium, low loss, anti-electromagnetic interference, less environmental interference, and single path. In the system, the transmission delay between the two places is often obtained by estimation or actual measurement, and then the transmission delay is compensated, so as to realize the transmission synchronization of time.

The delay control technology currently used in optical fiber time transfer mainly includes: phase shifter, which uses phase shifter to generate stable phase difference; this technology may have signal discontinuity, and the control range is extremely narrow, generally 10ns; programmable delay line , although the resolution is high, it is also difficult to achieve large-scale delay control, generally only a few tens of ns; FPGA (field programmable gate array), using FPGA to achieve phase shift, because the resolution of FPGA phase shift depends on The clock frequency of the FPGA greatly limits its resolution; the two-stage adjustment uses a combination of FPGA coarse adjustment and PLL phase shift fine adjustment to control a wide range of precise time delays. This method is mainly implemented by analog circuits, and the hardware The selection, processing and debugging requirements in the circuit are relatively high, and the intermediate state of compensation cannot be checked.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a multi-stage digital precision time delay control method and system for optical fiber time transfer, so as to solve one or more of the above-mentioned technical problems. The multi-stage digital precision time delay control method provided by the invention can realize the coarse adjustment and fine adjustment of the phase time delay through the combination of the FPGA technology and the DPLL phase shift technology, and can realize the multi-stage digital precision time delay control of the large-scale time delay.

To achieve the above object, the present invention adopts the following technical solutions:

A multi-stage digital precision time delay control method for optical fiber time transfer of the present invention comprises the following steps:

Step 1, obtain the initial delay control amount of the local end and the remote end;

Step 2, obtaining an integer multiple clock cycle of the FPGA phase shift based on the initial delay control amount, performing compensation according to the integer multiple clock cycle of the FPGA phase shifting, and obtaining an updated delay control amount after compensation;

Step 3, judging whether the update delay control amount is within the preset threshold range; if otherwise, skip to step 4, and if so, skip to step 5;

Step 4: Obtain the integer multiple clock cycle of the FPGA phase-shift based on the update delay control amount, perform compensation according to the integer multiple clock cycle of the FPGA phase shift, obtain the compensated update delay control amount, and jump to execute step 3;

Step 5, adopting DPLL to perform phase shifting according to the update delay control amount, and completing multi-stage digital precision delay control.

A further improvement of the method of the present invention is that step 1 specifically includes:

作为初始时延控制量。The actual delay between the external 1PPS signal transmitted by the optical fiber link and the 1PPS signal generated by the FPGA measured by the measurement unit

as the initial delay control amount.

A further improvement of the method of the present invention is that step 2 specifically includes:

公式处理初始时延控制量后，设定整周期移相的周期数N，FPGA延迟N个周期后输出1PPS信号。Determine the clock cycle of the FPGA as T, according to

After the formula processes the initial delay control quantity, set the cycle number N of the whole cycle phase shift, and the FPGA outputs a 1PPS signal after delaying N cycles.

A further improvement of the method of the present invention is that step 3 specifically includes:

Determine whether the update delay control amount is between plus and minus 150ns; if otherwise, skip to step 4, and if so, skip to step 5.

A further improvement of the method of the present invention is that step 5 specifically includes:

β为相位累加器与频率控制字的比例因子；判定粗调频率控制字值ξ是否大于最大阈值ξ_max或者小于最小阈值ξ_min；若否则按照初设值配置粗调频率控制字值ξ，若是则按照最大阈值ξ_max或者最小阈值ξ_min配置粗调频率控制字值ξ；Step 5.1, configure the maximum threshold ξ _max of the internal phase accumulator of the numerical control oscillator, the minimum threshold value of the phase accumulator ξ _min and the center value of the frequency control word ξ _m , ξ _m =2 ^n-1 , n is the internal phase accumulation of the numerical control oscillator The maximum threshold value of the coarse phase accumulator ξ _max , the minimum threshold value of the phase accumulator ξ _min and the coarse adjustment frequency control word value ξ according to the measured value of the time interval between the sending and receiving ends,

β is the proportional factor between the phase accumulator and the frequency control word; determine whether the coarse adjustment frequency control word value ξ is greater than the maximum threshold ξ _max or less than the minimum threshold ξ _min ; otherwise, configure the coarse adjustment frequency control word value ξ according to the initial value, if Then configure the coarse frequency control word value ξ according to the maximum threshold ξ _max or the minimum threshold ξ _min ;

是否在正负300ps之间，若否则跳转执行步骤5.1，若是则跳转执行步骤5.3；Step 5.2, determine the measured value of the time interval between the sending and receiving ends

Whether it is between plus and minus 300ps, if otherwise, jump to step 5.1, if so, jump to step 5.3;

Step 5.3, perform phase detection between the 10MHz output from the numerically controlled oscillator and the external input 10MHz, and configure the frequency control word value to change the minimum step value δ according to the phase detection value, and change the frequency control precisely in the forward or reverse direction according to the minimum step value δ Word value ξ, ξ=ξ±δ;

是否在正负30ps之间；若否则跳转执行步骤5.3，若是则完成多级数字精密时延控制。Step 5.4, determine the measured value of the time interval between the sending and receiving ends

Whether it is between plus and minus 30ps; if not, skip to step 5.3, if so, complete multi-level digital precision delay control.

A multi-stage digital precision time delay control system for optical fiber time transfer provided by the present invention includes:

The measurement acquisition module is used to acquire the initial delay control amount of the local end and the remote end;

a compensation module, configured to obtain an integer multiple clock period of the FPGA phase-shift based on the initial delay control amount, perform compensation according to the integer multiple clock period of the FPGA phase shift, and obtain an updated delay control amount after compensation;

a judging module for judging whether the update delay control amount is within a preset threshold range; if otherwise, skip to the step of executing the iteration module, and if so, skip to the step of executing the phase-shifting module;

The iterative module is used to obtain the integer multiple clock cycle of the FPGA phase shift based on the update delay control amount, perform compensation according to the integer multiple clock cycle of the FPGA phase shift, obtain the compensated update delay control amount, and jump to execute the judgment module. step;

The phase-shifting module is used to perform phase-shifting with DPLL according to the update delay control quantity, and complete multi-level digital precision delay control.

A further improvement of the system of the present invention is that the steps performed by the measurement acquisition module specifically include:

作为初始时延控制量。The actual delay between the external 1PPS signal transmitted by the optical fiber link and the 1PPS signal generated by the FPGA measured by the measurement unit

as the initial delay control amount.

A further improvement of the system of the present invention is that the steps performed by the compensation module specifically include:

公式处理初始时延控制量后，设定整周期移相的周期数N，FPGA延迟N个周期后输出1PPS信号。Determine the clock cycle of the FPGA as T, according to

After the formula processes the initial delay control quantity, set the cycle number N of the whole cycle phase shift, and the FPGA outputs a 1PPS signal after delaying N cycles.

A further improvement of the system of the present invention is that the steps performed by the judgment module specifically include:

It is judged whether the update delay control amount is between plus and minus 150ns; if otherwise, the step of executing the iteration module is skipped, and if so, the step of executing the phase-shifting module is skipped.

A further improvement of the system of the present invention is that the steps performed by the phase shifting module specifically include:

β为相位累加器与频率控制字的比例因子；判定粗调频率控制字值ξ是否大于最大阈值ξ_max或者小于最小阈值ξ_min；若否则按照初设值配置粗调频率控制字值ξ，若是则按照最大阈值ξ_max或者最小阈值ξ_min配置粗调频率控制字值ξ；Step 5.1, configure the maximum threshold ξ _max of the internal phase accumulator of the numerical control oscillator, the minimum threshold value of the phase accumulator ξ _min and the center value of the frequency control word ξ _m , ξ _m =2 ^n-1 , n is the internal phase accumulation of the numerical control oscillator The maximum threshold value of the coarse phase accumulator ξ _max , the minimum threshold value of the phase accumulator ξ _min and the coarse adjustment frequency control word value ξ according to the measured value of the time interval between the sending and receiving ends,

β is the proportional factor between the phase accumulator and the frequency control word; determine whether the coarse adjustment frequency control word value ξ is greater than the maximum threshold ξ _max or less than the minimum threshold ξ _min ; otherwise, configure the coarse adjustment frequency control word value ξ according to the initial value, if Then configure the coarse frequency control word value ξ according to the maximum threshold ξ _max or the minimum threshold ξ _min ;

是否在正负300ps之间，若否则跳转执行步骤5.1，若是则跳转执行步骤5.3；Step 5.2, determine the measured value of the time interval between the sending and receiving ends

Whether it is between plus and minus 300ps, if otherwise, jump to step 5.1, if so, jump to step 5.3;

Step 5.3, perform phase detection between the 10MHz output from the numerically controlled oscillator and the external input 10MHz, and configure the frequency control word value to change the minimum step value δ according to the phase detection value, and change the frequency control precisely in the forward or reverse direction according to the minimum step value δ Word value ξ, ξ=ξ±δ;

是否在正负30ps之间；若否则跳转执行步骤5.3，若是则完成多级数字精密时延控制。Step 5.4, determine the measured value of the time interval between the sending and receiving ends

Whether it is between plus and minus 30ps; if not, skip to step 5.3, if so, complete multi-level digital precision delay control.

Compared with the prior art, the present invention has the following beneficial effects:

The invention realizes a multi-level digital precise time delay control method applied to optical fiber time transfer through the application of FPGA and DPLL phase shifting technology. Relying on the high-precision optical fiber time transfer, the present invention provides a multi-level digital precise control method for a wide range of time delays. The invention can check the current work progress status by retrieving data, and can improve the problem location efficiency when the equipment fails, which is beneficial to standardization, integrated production and intelligent promotion. Specifically, the present invention can realize multi-level digital precision delay control applied to optical fiber time transfer, and the delay control accuracy is better than 30ps.

Description of drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the accompanying drawings used in the description of the embodiments or the prior art; obviously, the accompanying drawings in the following description are For some embodiments of the present invention, for those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative efforts.

1 is a schematic flowchart of a multi-stage digital precision time delay control method for optical fiber time transfer according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a multi-stage digital precision time delay control system for optical fiber time transfer according to an embodiment of the present invention.

Detailed ways

In order to make those skilled in the art better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only Embodiments are part of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

It should be noted that the terms "first", "second" and the like in the description and claims of the present invention and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific sequence or sequence. It is to be understood that the data so used may be interchanged under appropriate circumstances such that the embodiments of the invention described herein can be practiced in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "having", and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those expressly listed Rather, those steps or units may include other steps or units not expressly listed or inherent to these processes, methods, products or devices.

Below in conjunction with accompanying drawing, the present invention is described in further detail:

A multi-stage digital precision time delay control method for optical fiber time transfer according to an embodiment of the present invention includes the following steps:

Step 1, obtain the initial delay control amount of the local end and the remote end;

Step 2, obtaining an integer multiple clock cycle of the FPGA phase-shifting based on the initial delay control amount, performing primary compensation according to the integer multiple clock cycle of the FPGA phase shifting, and obtaining an updated delay control amount after the first-level compensation;

Step 3, judging whether the update delay control amount is within the preset threshold range; if not, then jump to step 4, if it is, then jump to step 5;

Step 4: Obtain the integer multiple clock cycle of the FPGA phase shift based on the update delay control amount, perform first-level compensation according to the integer multiple clock cycle of the FPGA phase shift, obtain the update delay control amount after the first-level compensation, and jump to the execution step 3;

Step 5, adopting DPLL to perform phase shifting according to the update delay control amount, and completing multi-stage digital precision delay control.

The embodiment of the present invention discloses a multi-level digital precision time delay control method applied to optical fiber time transfer based on FPGA and DPLL phase-shifting technology. Relying on high-precision optical fiber time transfer, multi-level digital precision can be performed on a wide range of time delays. Control, the current work progress status can be viewed by fetching data, which can improve the efficiency of problem location when equipment fails, which is conducive to standardized, integrated production and intelligent promotion.

Referring to FIG. 1, a multi-level digital precision time delay control method for optical fiber time transfer according to an embodiment of the present invention includes the following steps:

作为一个时延控制量。1. The actual delay between the external 1PPS signal transmitted by the optical fiber link and the 1PPS signal generated by the FPGA is measured by the measurement unit

as a delay control quantity.

送给控制单元处理，控制单元将其中为时钟周期整数倍的时延控制量发送给FPGA，开始第一级时延补偿，进入状态A并锁定。2. The delay control amount described in step 1

It is sent to the control unit for processing, and the control unit sends the delay control amount, which is an integer multiple of the clock period, to the FPGA, starts the first-stage delay compensation, enters state A and locks.

公式处理测量数据后，设定整周期移相的周期数N，FPGA延迟N个周期后输出1PPS信号，进入状态B。3. After the state A described in step 2 is locked, determine that the clock cycle of the FPGA is T, and the control chip collects the time interval between the sending and receiving ends, according to

After the formula processes the measurement data, set the cycle number N of the whole cycle phase shift, and the FPGA outputs a 1PPS signal after delaying N cycles, and enters state B.

是否在正负150ns之间，不符合判定条件则返回到状态A，符合判定条件则状态B锁定。4. The main control unit in step 2 determines the measured value of the time interval between the two ends of the sending and receiving

Whether it is between plus and minus 150ns, if it does not meet the judgment conditions, it will return to state A, and if it meets the judgment conditions, state B will be locked.

β为相位累加器与频率控制字的比例因子)。主控单元判定粗调的频率控制字值ξ是否大于最大阈值ξ_max或者小于最小阈值ξ_min，如果在两者之间，则NCO按照初设值配置粗调频率控制字值ξ，若不在两者之间，则按照最大阈值ξ_max或者最小阈值ξ_min配置粗调频率控制字值ξ，进入状态C。5. The main control unit described in step 2 begins to configure the maximum threshold ξ _max of the NCO internal phase accumulator and the minimum threshold ξ _min of the phase accumulator, and the center value of the frequency control word is ξ _m (ξ _m =2 ^n-1 , where n is The number of bits of the internal phase accumulator of the NCO), the maximum threshold value of the coarse phase accumulator ξ _max and the minimum threshold value of the phase accumulator ξ _min , and the coarse adjustment frequency control word value is configured according to the measured value of the time interval at both ends of the transmission and reception.

β is the scale factor of the phase accumulator and the frequency control word). The main control unit determines whether the coarse frequency control word value ξ is greater than the maximum threshold ξ _max or smaller than the minimum threshold ξ _min , if it is between the two, the NCO configures the coarse frequency control word value ξ according to the initial value, if it is not between the two. Between them, configure the coarse adjustment frequency control word value ξ according to the maximum threshold ξ _max or the minimum threshold ξ _min , and enter state C.

是否在正负300ps之间，不符合判定条件则返回到状态B，符合判定条件则状态C锁定；6. The main control unit described in step 2 further determines the measured value of the time interval at both ends of the transceiver

Whether it is between plus and minus 300ps, if it does not meet the judgment conditions, it will return to state B, and if the judgment conditions are met, state C will be locked;

7. At this time, the delay amount has been controlled within 300ps. It is necessary to perform phase detection between the 10MHz output from the NCO and the external input 10MHz, and feed back the phase detection value to the main control unit described in step 2, and further configure the frequency control word value to change. The minimum step value δ, the NCO precisely changes the frequency control word value ξ (ξ=ξ±δ) according to the change of the minimum step value δ forward or reverse, and enters the state D.

是否在正负30ps之间，如果是则进入最终锁定状态即状态D锁定，不满足判定条件则跳转至状态C继续调整时延，最终将时延控制在30ps之内，进行状态D的锁定。8. The main control unit described in step 2 finally determines the measured value of the time interval between the sending and receiving ends

Whether it is between plus and minus 30ps, if so, it will enter the final locking state, that is, state D is locked. If the judgment condition is not met, it will jump to state C to continue adjusting the delay, and finally control the delay within 30ps and lock state D. .

So far, the multi-level digital precision delay control applied to optical fiber time transfer has been realized, and the delay control accuracy is better than 30ps.

The following are apparatus embodiments of the present invention, which can be used to execute method embodiments of the present invention. For details that are not omitted in the device embodiments, please refer to the method embodiments of the present invention.

Referring to FIG. 2, a multi-stage digital precision time delay control system for optical fiber time transfer according to an embodiment of the present invention includes: a measurement unit, a main control unit, an FPGA, an NCO (Numerically Controlled Oscillator), and a DPD (Digital Phase Detection) Frequency discriminator), DLF (digital loop filter), which is composed of NCO, DPD, DLF to form a DPLL phase shift loop. The external 1PPS signal transmitted by the local end through the optical fiber link, the external 10MHz and the 1PPS signal output by the FPGA are used as input signals, and the output signal is a delayed time signal.

Aiming at the deficiencies of the current technology, the embodiment of the present invention proposes a multi-stage digital precise time delay control method applied to optical fiber time transfer based on FPGA coarse adjustment and PLL phase shift fine adjustment, so as to realize the multi-level delay in a wide range. Advanced digital precision delay control. This method can have a more intuitive digital identification status for the internal delay control status and lock status, and you can view the current work progress status by retrieving data, which is conducive to standardization, integrated production and intelligent promotion; specific advantages include: 1. The system has high time delay control resolution and adopts DPLL (Digital Phase Locked Loop) phase shifting technology to realize high resolution time delay control. 2. The FPGA is used to perform a full-cycle phase shift and enter the first-level state to perform rough adjustment of the delay, which can control the large-scale delay within one FPGA clock cycle. 3. Enter the next-level state. For the delay error in one FPGA clock cycle, use multi-stage cyclic digital adjustment until the control delay is within the precise range, that is, enter the final locked state.

As will be appreciated by those skilled in the art, the embodiments of the present application may be provided as a method, a system, or a computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present application. It will be understood that each flow and/or block in the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to the processor of a general purpose computer, special purpose computer, embedded processor or other programmable data processing device to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing device produce Means for implementing the functions specified in a flow or flow of a flowchart and/or a block or blocks of a block diagram.

These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory result in an article of manufacture comprising instruction means, the instructions The apparatus implements the functions specified in the flow or flow of the flowcharts and/or the block or blocks of the block diagrams.

These computer program instructions can also be loaded on a computer or other programmable data processing device to cause a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process such that The instructions provide steps for implementing the functions specified in the flow or blocks of the flowcharts and/or the block or blocks of the block diagrams.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: the present invention can still be Modifications or equivalent replacements are made to the specific embodiments of the present invention, and any modifications or equivalent replacements that do not depart from the spirit and scope of the present invention shall be included within the protection scope of the claims of the present invention.

Claims (10)

1. A multi-stage digital precision time delay control method for optical fiber time transmission is characterized by comprising the following steps:

step 1, acquiring initial delay control quantities of a local end and a remote end;

step 2, obtaining an integral multiple clock period of the FPGA phase shift based on the initial time delay control quantity, and compensating according to the integral multiple clock period of the FPGA phase shift to obtain a compensated updated time delay control quantity;

step 3, judging whether the updating time delay control quantity is in a preset threshold value range; if not, skipping to execute the step 4, and if so, skipping to execute the step 5;

step 4, obtaining an integral multiple clock period of the FPGA phase shift based on the updating time delay control quantity, compensating according to the integral multiple clock period of the FPGA phase shift, obtaining the compensated updating time delay control quantity, and skipping to execute the step 3;

and 5, performing phase shift by adopting the DPLL according to the updated time delay control quantity to complete multi-stage digital precise time delay control.

2. The method for controlling the multistage digital precision time delay for the optical fiber time transmission according to claim 1, wherein the step 1 specifically comprises:

the measurement unit measures the actual time delay amount of the external 1PPS signal transmitted by the optical fiber link and the 1PPS signal generated by the FPGA

As an initial delay control quantity.

3. The method according to claim 2, wherein the step 2 specifically comprises:

determining the clock period of FPGA as T according to

After the initial delay control quantity is processed by a formula, the number N of the periods of the whole-period phase shift is set, and the FPGA delays for N periods and outputs a 1PPS signal.

4. The method for controlling the multistage digital precision time delay for the optical fiber time transmission according to claim 3, wherein the step 3 specifically comprises:

judging whether the updating time delay control quantity is between plus or minus 150 ns; if not, skipping to execute the step 4, and if so, skipping to execute the step 5.

5. The method according to claim 3, wherein the step 5 specifically comprises:

step 5.1, configuring a maximum threshold xi of an internal phase accumulator of the numerically controlled oscillator_maxMinimum threshold xi of phase accumulator_minAnd center value xi of the frequency control word_m，ξ_m＝2^n-1N is the digit of the phase accumulator in the numerically controlled oscillator; coarse phase accumulator maximum threshold ξ_maxMinimum threshold xi of phase accumulator_minAnd configuring a coarse frequency control word value xi according to the time interval measurement value of the receiving and transmitting ends,

beta is a proportional factor of the phase accumulator and the frequency control word; determining whether coarse frequency control word value xi is greater than maximum threshold value xi_maxOr less than a minimum threshold ξ_min(ii) a If not, configuring a coarse tuning frequency control word value xi according to an initial value, and if so, configuring a maximum threshold value xi_maxOrMinimum threshold xi_minConfiguring a coarse adjustment frequency control word value xi;

step 5.2, judging the time interval measurement value of the transmitting end and the receiving end

Whether the difference is between plus and minus 300ps, if not, skipping to execute the step 5.1, and if so, skipping to execute the step 5.3;

step 5.3, phase discrimination is carried out between 10MHz output by the numerical control oscillator and 10MHz input by the outside, a frequency control word value is configured according to a phase discrimination numerical value to change a minimum step value delta, and the frequency control word value xi is precisely changed in the positive direction or the negative direction according to the minimum step value delta, and xi is equal to xi +/-delta;

step 5.4, judging the time interval measurement value of the transmitting end and the receiving end

Whether between plus or minus 30 ps; if not, skipping to execute the step 5.3, and if so, completing the multi-stage digital precision time delay control.

6. A multi-stage digital precision time delay control system for optical fiber time transfer, comprising:

the measurement acquisition module is used for acquiring initial delay control quantities of the local end and the remote end;

the compensation module is used for obtaining the integral multiple clock period of the FPGA phase shift based on the initial time delay control quantity, compensating according to the integral multiple clock period of the FPGA phase shift and obtaining the updated time delay control quantity after compensation;

the judging module is used for judging whether the updating time delay control quantity is within a preset threshold value range; if not, skipping the step of executing the iterative module, and if so, skipping the step of executing the phase shifting module;

the iteration module is used for obtaining the integral multiple clock period of the FPGA phase shift based on the updating time delay control quantity, compensating according to the integral multiple clock period of the FPGA phase shift, obtaining the compensated updating time delay control quantity, and skipping to execute the step of the judgment module;

and the phase-shifting module is used for performing phase shifting by adopting the DPLL according to the updated time delay control quantity to finish multi-stage digital precise time delay control.

7. The system of claim 6, wherein the measurement acquisition module performs steps comprising:

the measurement unit measures the actual time delay amount of the external 1PPS signal transmitted by the optical fiber link and the 1PPS signal generated by the FPGA

As an initial delay control quantity.

8. The system of claim 7, wherein the compensation module performs steps comprising:

determining the clock period of FPGA as T according to

After the initial delay control quantity is processed by a formula, the number N of the periods of the whole-period phase shift is set, and the FPGA delays for N periods and outputs a 1PPS signal.

9. The system according to claim 8, wherein the determining module performs the steps of:

judging whether the updating time delay control quantity is between plus or minus 150 ns; if not, skipping the step of executing the iteration module, and if so, skipping the step of executing the phase shifting module.

10. The system of claim 8, wherein the phase shifting module performs steps comprising:

step 5.1, configuring a maximum threshold xi of an internal phase accumulator of the numerically controlled oscillator_maxMinimum threshold xi of phase accumulator_minAnd center value xi of the frequency control word_m，ξ_m＝2^n-1N is the digit of the phase accumulator in the numerically controlled oscillator; coarse phase accumulator maximum threshold ξ_maxMinimum threshold xi of phase accumulator_minAnd a coarse tuning frequency control word value xi is configured according to the time interval measurement value of the receiving and transmitting ends,

beta is a proportional factor of the phase accumulator and the frequency control word; determining whether coarse frequency control word value xi is greater than maximum threshold value xi_maxOr less than a minimum threshold ξ_min(ii) a If not, configuring a coarse tuning frequency control word value xi according to an initial value, and if so, configuring a maximum threshold value xi_maxOr minimum threshold ξ_minConfiguring a coarse adjustment frequency control word value xi;

step 5.2, judging the time interval measurement value of the transmitting end and the receiving end

Whether the difference is between plus and minus 300ps, if not, skipping to execute the step 5.1, and if so, skipping to execute the step 5.3;

step 5.3, phase discrimination is carried out between 10MHz output by the numerical control oscillator and 10MHz input by the outside, a frequency control word value is configured according to a phase discrimination numerical value to change a minimum step value delta, and the frequency control word value xi is precisely changed in the positive direction or the negative direction according to the minimum step value delta, and xi is equal to xi +/-delta;

step 5.4, judging the time interval measurement value of the transmitting end and the receiving end

Whether between plus or minus 30 ps; if not, skipping to execute the step 5.3, and if so, completing the multi-stage digital precision time delay control.

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