CN114640812B - Reset and read time sequence control method of image sensor - Google Patents
Reset and read time sequence control method of image sensor Download PDFInfo
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- CN114640812B CN114640812B CN202011478944.1A CN202011478944A CN114640812B CN 114640812 B CN114640812 B CN 114640812B CN 202011478944 A CN202011478944 A CN 202011478944A CN 114640812 B CN114640812 B CN 114640812B
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- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
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- H—ELECTRICITY
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- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
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Abstract
The invention provides a reset and readout time sequence control method of an image sensor, wherein the image sensor at least comprises a pixel unit, a row driving circuit and a time sequence control module, and the row driving circuit transmits a row driving signal to the pixel unit through a row connecting wire; the timing control method comprises the following steps: while the pixel units of the reset row execute the reset operation, the output signals of the pixel units of the readout row are in a stable process, and the pixel units of the readout row execute the readout operation, so that the parallel operation of the reset pixel units and the readout of the pixel units of the readout row is realized. The invention shortens the line period time and improves the frame rate through simultaneous operation of reading and resetting; the state of the pixel unit row driving signal is maintained by using the capacitor on the row connecting line connected with the pixel unit by the row driving circuit so as to ensure that the reading operation and the resetting operation are performed simultaneously.
Description
Technical Field
The present invention relates to the field of image sensors, and in particular, to a method for controlling reset and readout timing of an image sensor.
Background
An image sensor is a semiconductor device that converts an optical signal into an electrical signal. Currently, conventional image sensors include Charge Coupled Device (CCD) image sensors, complementary Metal Oxide Semiconductor (CMOS) image sensors. CMOS image sensors are widely used in the field of image sensors because of their low power consumption and high signal to noise ratio.
In a conventional image sensor, reset and readout operations of pixel units in different rows are performed in a time-sharing (serial) manner, reset operations are performed on pixel units in one row or a plurality of rows first, then readout operations are performed on pixel units in another row or a plurality of rows, reset operations of reset rows and readout operations of readout rows are performed in a time-sharing (serial) manner, and a frame rate of the image sensor is limited.
Therefore, how to increase the frame rate of an image sensor has become a new research direction for sensor technology.
Disclosure of Invention
The invention aims to provide a reset and readout time sequence control method of an image sensor, which is used for shortening the line period time and improving the frame rate.
Based on the above, the present invention provides a reset and readout timing control method of an image sensor, where the image sensor at least includes a pixel unit and a row driving circuit, and the row driving circuit transmits a row driving signal to the pixel unit through a row connection line;
While the pixel units of the reset row execute the reset operation, the output signals of the pixel units of the readout row are in a stable process, and the pixel units of the readout row execute the readout operation, so that the parallel operation of the reset pixel units and the readout of the pixel units of the readout row is realized.
Optionally, the timing control method specifically includes:
S01: selecting pixel units of a read row, and starting a read operation by the selected pixel units of the read row;
S02, the output signals of the pixel units of the readout row to be selected start to be stable, and then the pixel units of the reset row are selected;
S03, resetting the selected reset row pixel units, and simultaneously, stabilizing output signals of the read row pixel units;
S04: after the selected pixel units of the reset row complete the reset operation, the pixel units of the readout row are reselected, and the readout operation is continued;
during the readout operation and the reset operation, the strobe signal of the pixel unit of the readout row is kept valid, and the strobe signals of the pixel units of the rows other than the readout row are not valid.
Alternatively, a set of row decoding circuits is employed to select pixel cells of a readout row or a reset row.
Alternatively, the state of the row driving signal output by the row driving circuit is maintained by a capacitance on a row connection line between the row driving circuit and the pixel unit.
Optionally, the capacitance on the row connection line comprises a parasitic capacitance of the row connection line and a device capacitance connected to the row connection line.
Optionally, the disconnection or connection of the row driving circuit and the row connection line is controlled using an enable signal and a switching circuit provided between the row driving circuit and the pixel unit.
Optionally, the switching circuit includes a pass transistor or pass gate or a switch composed of logic circuits other than the pass transistor or pass gate.
Optionally, the reset line comprises one or more lines, and the readout line comprises one or more lines
The reset and readout time sequence control method of the image sensor has the following beneficial effects:
The reading and resetting are operated simultaneously, so that the line period time is shortened, and the frame rate is improved;
The state of the pixel cell row driving signal is maintained by the capacitance on the row connection line to ensure that the readout operation and the reset operation are performed simultaneously.
Drawings
Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments which follows, which is read in connection with the accompanying drawings.
FIG. 1 is a schematic diagram of a pixel unit of an image sensor according to the prior art;
FIG. 2 is a timing diagram of prior art image sensor reset and read operations;
FIG. 3 is a timing diagram of the reset and read operations of the image sensor according to the present invention;
FIG. 4 is a schematic diagram of a pixel unit with equivalent capacitance according to the present invention;
FIG. 5 is a schematic diagram of a row circuit according to the present invention;
fig. 6 shows a timing diagram of the operation of the row circuit provided by the present invention.
In the drawings, the same or similar reference numerals denote the same or similar devices (modules) or steps throughout the different drawings.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be embodied in many other forms than those herein described, and those skilled in the art will readily appreciate that the present invention may be similarly embodied without departing from the spirit or essential characteristics thereof, and therefore the present invention is not limited to the specific embodiments disclosed below.
Next, the present invention will be described in detail with reference to the drawings, which are only examples for convenience of illustration, and should not be construed as limiting the scope of the invention.
The pixel cell structure provided in the prior art is shown in fig. 1, and generally, a pixel cell includes a photodiode D1, a transfer transistor MTX, a floating diffusion FD, a reset transistor MRST, an amplifying transistor (source follower) MSF, and a gate transistor MSEL. The transmission signal TX, the reset signal RST, and the row selection signal SEL are row driving signals of the pixel unit, and are sent out by a row driving circuit. The transfer signal TX drives the gate of the transfer transistor MTX through the row connection line_tx, the reset signal RST drives the gate of the reset transistor MRST through the row connection line_rst, and the row selection signal SEL drives the gate of the gate transistor MSEL through the row connection line_sel. The reset operation process of the pixel unit is that firstly, a reset signal RST is changed from low to high, a reset transistor MRST is conducted, and a floating diffusion region FD is reset to VDD; then the reset signal RST goes low and the reset transistor MRST turns off; then the transfer signal TX changes from low to high, the transfer transistor MTX turns on, and all electrons accumulated in the photodiode D1 are transferred to the floating diffusion FD; finally the transmission signal TX goes low and the transmission transistor MTX turns off. In this way, the reset operation of the electrons accumulated in the photodiode D1 in the pixel unit is completed. The readout operation of the pixel unit is that, first, the reset signal RST is changed from low to high, the reset transistor MRST is turned on, and the floating diffusion FD is reset to VDD; then the reset signal RST goes low, the reset transistor MRST is turned off, the voltage of the floating diffusion FD is output to the pixel unit output terminal through the amplifying transistor MSF and the gating transistor MSEL, and then a readout circuit (not shown) reads the voltage of the pixel unit output terminal, i.e., reads out the reference voltage; then the transfer signal TX changes from low to high, the transfer transistor MTX turns on, and all electrons accumulated in the photodiode D1 are transferred to the floating diffusion FD; then the transfer signal TX goes low, the transfer transistor MTX turns off, the voltage of the floating diffusion FD is output to the pixel unit output terminal through the amplifying transistor MSF and the gating transistor MSEL, and then a readout circuit (not shown) reads the voltage of the pixel unit output terminal, i.e., the readout signal voltage. Thus, the readout operation of electrons accumulated in the photodiode D1 in the pixel unit is completed.
In a conventional image sensor, the reset and readout operations of pixel units in different rows are performed in a time-sharing (serial) manner, wherein the reset operation is performed on pixel units in one row or a plurality of rows, and then the readout operation is performed on pixel units in another row or a plurality of rows. The row cycle time is the time to complete one complete reset operation and read operation. As shown in fig. 2, the row select signal SEL < i > drives the gate of the reset row i pixel cell gate transistor, the reset signal RST < i > drives the gate of the reset row i pixel cell reset transistor, and the transfer signal TX < i > drives the gate of the reset row i pixel cell transfer transistor; the row selection signal SEL < j > drives the gate of the readout row j pixel cell gate transistor, the reset signal RST < j > drives the gate of the readout row j pixel cell reset transistor, and the transfer signal TX < j > drives the gate of the readout row j pixel cell transfer transistor; t1 is the reset operation time of the pixel units of the reset row i, T2 is the read operation time of the pixel units of the read row j, and T is the row period time, namely the sum of the time of T1 and T2. In the row period time T, firstly, resetting operation is carried out on the pixel units in the ith row, and after the resetting operation is finished, reading operation is carried out on the pixel units in the jth row, wherein the resetting operation and the reading operation in the row are carried out in a time sharing (serial) mode.
In order to shorten the line period time and provide the frame rate, the invention provides a time sequence control method for parallel operation of resetting and reading out of an image sensor. The foregoing objects, features and advantages of the invention will be more readily apparent from the following detailed description taken in conjunction with the accompanying drawings.
The embodiment provides a time sequence control method for parallel operation of resetting and reading out of an image sensor, which is used for improving the frame rate of the image sensor, wherein the image sensor at least comprises a pixel unit and a row driving circuit, and the row driving circuit transmits a row driving signal to the pixel unit through a row connecting wire;
The time sequence control method comprises the following steps: while the pixel units of the reset row execute the reset operation, the output signals of the pixel units of the readout row are in a stable process, and the pixel units of the readout row execute the readout operation, so that the parallel operation of the reset pixel units and the readout of the pixel units of the readout row is realized.
As shown in fig. 3, in the timing chart of the readout and reset operations of the pixel unit of the image sensor provided by the invention, the row selection signal SEL < i > drives the gate of the pixel unit gating transistor of the reset row i, the reset signal RST < i > drives the gate of the pixel unit resetting transistor of the reset row i, and the transmission signal TX < i > drives the gate of the pixel unit transmission transistor of the reset row i; the row selection signal SEL < j > drives the gate of the readout row j pixel cell gate transistor, the reset signal RST < j > drives the gate of the readout row j pixel cell reset transistor, and the transfer signal TX < j > drives the gate of the readout row j pixel cell transfer transistor; the time sequence control method comprises the following specific steps:
S01: the pixel cells of the readout row are selected, and the selected pixel cells of the readout row start the readout operation. As shown in fig. 3, at time A1, the row selection signal SEL < j > and the reset signal RST < j > of the readout row j are at high level, the floating diffusion area FD of the pixel unit of the readout row j is reset to VDD, then at time B1, the reset signal RST < j > of the readout row j becomes low, the voltage of the floating diffusion area FD is output to the output end of the pixel unit through the amplifying transistor MSF and the gating transistor MSEL, and the output signal of the pixel unit of the selected readout row j starts to be stable;
s02, the output signals of the pixel units of the read-out row to be selected start to be stable, and the pixel units of the reset row are selected. As at time C1 in fig. 3, the pixel cell of the read-reset row i is selected;
S03, resetting the pixel units of the selected reset row, and simultaneously, stabilizing the output signals of the pixel units of the read row j. As shown in a period T1 of fig. 3, that is, in a period from C1 to D1, the reset signal RST < i > of the reset row i is from high to low, and the transmission signal TX < i > of the reset row i drives the transmission transistor to be turned on and then turned off, so as to complete the reset operation of the reset row i; meanwhile, the gating signal SEL < j > of the reading row j is always in a high level state, and the output signal of the pixel unit of the selected reading row j is always in a stable process;
S04: after the pixel units of the selected reset row i complete the reset operation, the pixel units of the readout row j are reselected, and the pixel units of the readout row continue the readout operation. As in the period T2 in fig. 3, the transmission signal of the readout row j is turned on and then turned off, the pixel cells of the readout row j continue to perform the readout operation, and the readout operation is completed at the time E1;
During the readout operation and the reset operation, the strobe signal of the pixel unit of the readout row j is kept active (at a high level), and the strobe signals of the other rows (including the reset row i) other than the readout row are inactive (at a low level) to output the signal voltage of the readout row i.
As shown in fig. 3, in the present embodiment, T1 is the reset operation time of the pixel cells of the reset row i, T2 is the readout operation time of the pixel cells of the readout row j, and T is the row cycle time. T1 and T2 overlap in time, i.e., the reset operation of the reset row i is performed simultaneously (in parallel) with the read operation of the read row j, and only the read row select signal SEL < j > is active (high level) and the other row select signals (including SEL < i >) are inactive (low level) in the time T1 and T2, so that the correct readout of the electronic signals in the pixel cell photodiodes of the read row j can be achieved, and thus the parallel performance of the reset operation and the read operation of different rows is achieved in the time T1 and T2. Compared with the traditional method, the line operation method saves the whole line period time of the pixel unit, saves about 200-500 ns, and improves the frame rate of the image sensor.
Alternatively, the state of the pixel cell row driving signal is maintained by a capacitance on a row connection line to which the row driving circuit is connected. When the row driving circuit of the readout row is disconnected from the row connection line, the capacitance of the readout row pixel cell connection line keeps the row selection signal valid, so that when the row connection line is disconnected, the readout operation can be continued to realize parallel operation of resetting the row pixel cell and readout of the readout row pixel cell.
The capacitance on the row connection line includes parasitic capacitance existing in the row connection line itself and device capacitance of the transistor connected to the row connection line.
As shown in fig. 4, the row select signal SEL drives the gate of the gate transistor MSEL through the row connection line_sel, the reset signal RST drives the gate of the reset transistor MRST through the row connection line_rst, and the transfer signal TX drives the gate of the transfer transistor MTX through the row connection line_tx. The parasitic capacitance of the line connection line_sel and the device capacitance of the gating transistor MSEL are equivalent to the capacitance CSEL on the line connection line line_sel, the parasitic capacitance of the line connection line_rst and the device capacitance of the reset transistor MRST are equivalent to the capacitance CRST on the line connection line line_rst, and the parasitic capacitance of the line connection line_tx and the device capacitance of the transmission transistor MTX are equivalent to the capacitance CTX on the line connection line_tx. Since the row connection line_sel is connected to the gate of the whole row pixel cell gating transistor MSEL, the row connection line_rst is connected to the gate of the whole row pixel cell reset transistor MRST, and the row connection line_tx is connected to the gate of the whole row pixel cell transfer transistor, the capacitors CSEL, CRST, CTX are all pF levels. When the row drive circuit is disconnected from the row connection lines line_sel, line_rst, line_tx, the capacitance of the row connection lines maintains SEL, RST, TX voltage information on the row connection lines. When the readout line is disconnected and the reset line is selected to perform the reset operation, the strobe signal and the reset signal of the readout line are respectively in a high level state and a low level state, so that the readout operation of the readout line is maintained, and the parallel performance of the reset operation of the reset line and the readout operation of the readout line is realized.
Optionally, a set of row decoders is provided, connected to the row driving circuit, to select the pixel cells of the reset row or the readout row.
Alternatively, disconnection or connection of the row connection lines may also be controlled by an enable signal and a switching circuit between the row driving circuit and the pixel cells.
As shown in fig. 5, a set of decoders is added to select a read row or a reset row and control the disconnection or connection of the row connection lines through an enable signal cnct and a switching circuit. Where ADDR <10:0> is a row address signal (for example, an 11-bit row address code), RSEL, RG, TG, cnct are row input signals. RSEL is used to generate the row select signal SEL, RG is used to generate the reset signal RST, TG is used to generate the transmission signals TX, cnct as the enable signals. The output of the row driver circuit is connected to the input of the switch circuit and the row input signal cnct is connected to the input of the switch circuit. When cnct is high, the row drive circuit is disconnected from the row connection lines line_sel, line_rst, and when cnct is low, the row drive circuit is connected to the row connection lines line_sel, line_rst. Within the dashed line box is a set of row decoding circuits, the row address signals ADDR <10:0> are decoded by the row decoding circuits and output to the input terminals of the row driving circuits, the row input signals RSEL, RG, TG, cnct are connected to the input terminals of the row driving circuits, and the output of the row address signals ADDR <10:0> decoded by the row decoding circuits is connected to the input terminals of the row driving circuits together with the row input signals RSEL, RG, TG, cnct to jointly control the row driving circuits to generate output row selection signals SEL, RST, TX.
The switching circuit may be a transfer transistor or a transfer gate or a switch composed of logic circuits other than the transfer transistor or the transfer gate.
Specific operation procedure as shown in fig. 6, at time A2, the read row address j is translated, and the read row of the read row starts the read operation. At time B2, the enable signal cnct goes high from low, the row driving circuit is disconnected from the row connection lines line_sel and line_rst, and the capacitors CSEL and CRST of the row connection lines respectively hold the SEL and RST voltage information on the row connection lines, and at this time, the row selection signal SEL of the readout row j is high and the reset signal RST is low; the row select signal SEL of the reset row i is low and the reset signal RST is high; the row select signal SEL of the other row is low, the reset signal RST is high, and the row select signals of the reset row and the other row are low except that the row select signal SEL of the read row is high, so that the read row can read out the correct signal. At time C2, the reset row address i is translated, and the reset row starts the reset operation, and T1 (time C2 to time D2) is the reset operation time of the reset row i. At time E2, cnct goes low, and the read row address j is decoded again, and the row driving circuit is connected to the row connection lines SEL and RST, and at this time, the row selection signal SEL of the read row j is high and the reset signal RST is low; the row select signal SEL of the reset row i is low and the reset signal RST is high; the row select signal SEL of the other row is low, the reset signal RST is high, the row select signals SEL of the reset row and the other row are low except for the row select signal SEL of the readout row, the readout row i continues the readout operation, and T2 (time A2 to time F2) is the readout operation time of the readout row j.
The embodiment provides a timing control method for parallel operation of resetting and reading out of an image sensor, which keeps the state of a pixel unit row driving signal through a capacitor on a row connecting line, and realizes that pixel units in a reset row execute the resetting operation and simultaneously, pixel units in a read-out row execute the reading-out operation.
In summary, the present invention provides a timing control method for parallel operation of reset and readout of an image sensor, in which, when the pixel units of the reset row execute the reset operation, the pixel units of the readout row execute the readout operation, and the output signals of the pixel units of the readout row are in a stable process, so as to realize the parallel operation of reset of the pixel units of the reset row and readout of the pixel units of the readout row, thereby shortening the cycle time of the row and improving the frame rate; and the state of the pixel cell row driving signal is maintained by the capacitance on the row connection line to ensure that the readout operation and the reset operation are performed simultaneously.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Thus, the embodiments should be considered in all respects as illustrative and not restrictive. Furthermore, it is evident that the word "comprising" does not exclude other elements or steps, and that the word "a" or "an" does not exclude a plurality. The elements recited in the apparatus claims may also be embodied by one element. The terms first, second, etc. are used to denote a name, but not any particular order.
Claims (8)
1. The reset and readout time sequence control method of the image sensor is characterized in that the image sensor at least comprises a pixel unit and a row driving circuit, and the row driving circuit transmits a row driving signal to the pixel unit through a row connecting wire;
The timing control method comprises the following steps: when the pixel units of the reset row execute the reset operation, the output signals of the pixel units of the readout row are in a stable process, and the pixel units of the readout row execute the read operation, so that the parallel operation of the reset pixel units and the readout of the pixel units of the readout row is realized; the state of a row driving signal output by the row driving circuit is maintained by using a capacitor on a row connecting line between the row driving circuit and the pixel unit, wherein the capacitor on the row connecting line comprises a parasitic capacitor of the row connecting line and a device capacitor connected with the row connecting line; wherein the reset row and the read-out row are different rows.
2. The method for controlling the reset and read-out timing of an image sensor according to claim 1, wherein said timing control method specifically comprises:
S01: selecting pixel units of a read row, and starting a read operation by the selected pixel units of the read row;
S02: the output signals of the pixel units of the read-out row to be selected start to be stable, and then the pixel units of the reset row are selected;
S03: resetting the selected reset row pixel units, and simultaneously, stabilizing output signals of the read row pixel units;
S04: after the selected pixel units of the reset row complete the reset operation, the pixel units of the readout row are reselected, and the readout operation is continued;
during the readout operation and the reset operation, the strobe signal of the pixel unit of the readout row is kept valid, and the strobe signals of the pixel units of the rows other than the readout row are not valid.
3. The reset and readout timing control method of an image sensor according to claim 1 or 2, wherein a set of row decoding circuits is employed to select pixel cells of a readout row or a reset row.
4. The reset and readout timing control method of an image sensor according to claim 1 or 2, wherein disconnection or connection of the row connection lines is controlled by employing an enable signal and a switching circuit provided between a row driving circuit and a pixel unit.
5. The reset and readout timing control method of an image sensor according to claim 3, wherein disconnection or connection of the row connection lines is controlled by using an enable signal and a switching circuit provided between a row driving circuit and a pixel unit.
6. The reset and readout timing control method of an image sensor according to claim 4, wherein the switching circuit includes a transfer transistor or a transfer gate or a switch composed of a logic circuit other than the transfer transistor or the transfer gate.
7. The reset and readout timing control method of an image sensor according to claim 5, wherein the switching circuit includes a transfer transistor or a transfer gate or a switch composed of a logic circuit other than the transfer transistor or the transfer gate.
8. The reset and readout timing control method of an image sensor according to claim 1, wherein the reset line includes one or more lines, and the readout line includes one or more lines.
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| JP2010251829A (en) * | 2009-04-10 | 2010-11-04 | Olympus Corp | Solid-state image sensor, camera system, and signal reading method |
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| CN103491321A (en) * | 2012-06-12 | 2014-01-01 | 索尼公司 | Solid-state imaging device, method for driving solid-state imaging device, and electronic device |
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| CN103491321A (en) * | 2012-06-12 | 2014-01-01 | 索尼公司 | Solid-state imaging device, method for driving solid-state imaging device, and electronic device |
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