CN114664847B

CN114664847B - Semiconductor structure and manufacturing method thereof

Info

Publication number: CN114664847B
Application number: CN202210125492.1A
Authority: CN
Inventors: 童宇诚; 张钦福
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2022-02-10
Filing date: 2022-02-10
Publication date: 2025-09-26
Anticipated expiration: 2042-02-10
Also published as: CN114664847A

Abstract

The invention discloses a semiconductor structure and a manufacturing method thereof, comprising a substrate, a plurality of grooves and active areas, a plurality of bit lines which are arranged on a storage unit area at equal intervals along a first direction and extend towards a second direction orthogonal to the first direction, wherein the bit lines are electrically connected to the active areas in the substrate through the grooves, and a dummy bit line which is positioned at the outermost side of the bit lines in the first direction and extends towards the second direction, wherein the width of the dummy bit line in the first direction is larger than the width of the bit lines in the first direction, the bottoms of the dummy bit lines are not in the same horizontal plane, and the dummy bit line and the bit lines have the same composition and layer structure.

Description

Semiconductor structure and manufacturing method thereof

Technical Field

Embodiments disclosed herein relate to a semiconductor structure and a method of fabricating the same, and more particularly, to a semiconductor structure having bit lines with different widths and a method of fabricating the same.

Background

A memory device is an integrated circuit that is typically used in computer systems to store data, fabricated into one or more array patterns with individual memory cells. The memory device may use bit lines (also referred to as digit lines, data lines, or sense lines) and word lines (also referred to as access lines) for writing and reading, wherein the bit lines may be electrically connected to the memory cells along columns of the matrix and the word lines may be electrically connected to the memory cells along rows of the matrix. Each memory cell is individually addressable via a combination of a bit line and a word line.

The memory device may be volatile, semi-volatile, or non-volatile in nature. Non-volatile memory devices can store data for a long period of time without power, and volatile memory devices dissipate the stored data, thus requiring continuous refresh/rewrite to maintain its data storage. The memory device uses a capacitor to store charge, and the charge of the capacitor is read to determine which memory state, such as "0" or "1" is used in the memory cell, so as to achieve the purposes of data storage and reading. The memory device also has electronic components such as transistors to control the switching of the gate and the storage and release of charge. The periphery of the memory cell array region of the memory device has a peripheral circuit region, and bit lines and word lines extend from the memory cell array region to the peripheral circuit region and are electrically connected to external circuits in the region through other interconnection structures such as wires and contacts.

In the fabrication of memory devices or other circuits, the goal of ever shrinking and tightening the components to achieve higher storage capacities per unit area has been a constant goal of industry efforts. However, as the memory device is continuously miniaturized, many problems to be overcome in the manufacturing process, such as micro-loading effect caused by different pattern densities, or insufficient layout space caused by too tight components, are also encountered. The motivation of the present invention is to overcome some of the problems encountered in the fabrication of the above-described circuits.

Disclosure of Invention

The invention provides a novel semiconductor structure and a manufacturing method thereof, which are characterized in that the dummy bit line positioned at the outermost side has larger width and different partition wall types, and can solve the problem of micro-load effect of devices.

One aspect of the present invention is directed to a semiconductor structure, comprising a substrate defining a memory cell region thereon, wherein the substrate further has a plurality of grooves, a plurality of bit lines arranged on the memory cell region at equal intervals along a first direction and extending in a second direction orthogonal to the first direction, the bit lines being electrically connected to an active region in the substrate via the grooves, and a dummy bit line located at an outermost side of the bit lines in the first direction and extending in the second direction, wherein a width of the dummy bit line in the first direction is larger than a width of the bit line in the first direction, and a bottom of the dummy bit line is not in a same level, the dummy bit line and the bit lines have a same composition and layer structure, and a portion of the dummy bit line is located in the grooves and electrically connected to an active region in the substrate.

Another aspect of the present invention is to provide a method for manufacturing a semiconductor structure, which includes providing a substrate, defining a memory cell region on the substrate, and further having a plurality of grooves, forming a bit line material layer on the substrate, forming a plurality of bit line shielding patterns on the bit line material layer, wherein the bit line shielding patterns are arranged on the memory cell region at equal intervals along a first direction and extend in a second direction orthogonal to the first direction, forming a photoresist on the bit line shielding patterns, wherein the photoresist covers a region outside the memory cell region and the bit line shielding patterns located at the outermost side in the first direction, but exposes the other bit line shielding patterns, and etches the bit line material layer with the photoresist and the bit line shielding patterns as etching masks, so as to form a plurality of bit lines and bit lines located at the outermost side of the bit lines in the first direction, wherein the bit lines and the dummy bit lines extend in the second direction, and the bit lines electrically connect to the dummy lines in the first direction and have a dummy line width in the same direction as the bit line and the dummy line.

These and other objects of the present invention will become more readily apparent to those skilled in the art from a reading of the following detailed description of the preferred embodiment, which is to be read in connection with the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to further explain the principles of the invention. The drawings illustrate some embodiments of the invention and, together with the description, explain its principles. In these illustrations:

FIGS. 1A, 2A and 3A are schematic cross-sectional views illustrating a process for fabricating a semiconductor structure according to a preferred embodiment of the present invention;

FIGS. 1B, 2B and 3B are schematic cross-sectional views taken along section lines A-A' of FIGS. 1A, 2A and 3A, respectively;

FIG. 4 is a schematic cross-sectional view of a semiconductor structure according to a preferred embodiment of the present invention;

FIG. 5 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present invention;

FIG. 6 is a schematic cross-sectional view of a semiconductor structure according to yet another embodiment of the present invention;

FIG. 7 is a schematic cross-sectional view of a semiconductor structure according to yet another embodiment of the present invention;

FIG. 8 is a schematic cross-sectional view of a semiconductor structure according to a preferred embodiment of the present invention;

FIG. 9 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present invention;

FIG. 10 is a schematic cross-sectional view of a semiconductor structure according to yet another embodiment of the present invention, and

Fig. 11 is a schematic cross-sectional view of a semiconductor structure according to yet another embodiment of the present invention.

It should be noted that all figures in this specification are schematic representations for clarity and convenience in the drawings, in which the various elements in the figures may be exaggerated in size or scale, and in general, the same reference numerals will be used to designate corresponding or analogous element features in modified or different embodiments.

Wherein reference numerals are as follows:

100. Semiconductor substrate

100A memory cell area

100B active region

100C active region

102. Device isolation layer

103. Groove

104. Insulating layer

105. Groove(s)

106. Contact layer

108. Barrier layer

110. Metal layer

112. Hard mask layer

114. Bit line shielding pattern

116. Photoresist

118. Bit line spacer

119. Bit line spacer

120. Partition wall

122. Partition wall

124. Spacer layer

126. Spacer layer

128. Spacer layer

130. Groove(s)

131. Contact region

132. Polysilicon layer

134. Silicide layer

136. Barrier layer

138. Metal layer

BL bit line

DBL dummy bit line

D1 First direction

D2 Second direction

SC storage node contact structure

Width of W1, W2, W3, W4

Detailed Description

In the drawings, fig. 1A, 2A and 3A are plan views showing a process of fabricating a semiconductor structure according to a preferred embodiment of the present invention, and fig. 1B, 2B and 3B are sectional views taken along the sectional lines A-A' in fig. 1A, 2A and 3A, respectively, which show the relative positions of the components of the semiconductor structure in the direction perpendicular to the substrate and the connection relationship thereof.

Please refer to fig. 1A and fig. 1B at the same time. The semiconductor structure of the present invention is fabricated on a semiconductor substrate 100, such as a silicon substrate, a germanium substrate, and/or a silicon germanium substrate. The semiconductor substrate 100 defines a memory cell region 100a for providing memory cells (cells) of the semiconductor memory device, and the memory cells can be configured to store charges in the memory cell region 100a to generate a distinct memory state, thereby achieving a memory effect. Surrounding the memory cell region 100a may be a peripheral region (not shown) for providing peripheral circuits of the memory device, such as column decoders, sense amplifiers, or I/O control modules. The memory cell region 100a of the semiconductor substrate 100 defines a plurality of active regions 100b, each active region 100b being separated and defined by a surrounding device isolation layer 102, such as a Shallow Trench Isolation (STI) structure. In the process, the device isolation layer 102 may be formed by performing a photolithography process on the semiconductor substrate 100 to form individual separated active regions 100b, and filling the trenches between the active regions 100b with an isolation material, such as silicon oxide. An insulating layer 104 is formed on the surface of the semiconductor substrate 100 to isolate the lower active region 100b from the upper components, which may also serve as a gate dielectric layer for the peripheral region gate devices. The insulating layer 104 may be formed of a single insulating layer or a plurality of insulating layers, such as a silicon nitride layer, and/or a silicon oxynitride layer. A portion of the active region 100b is formed with a recess 103 such that portions of the active region 100b are exposed from the insulating layer 104. It should be noted that in practice, the active regions 100b may be stripe-shaped in plan view and have long axes extending in the same direction, and are uniformly arranged in a staggered manner in plan view. Since the active region 100b is not an emphasis of the present invention, only the memory cell region 100a and the bit line mask pattern 114 thereon are shown in fig. 1A for simplicity of illustration and to avoid obscuring the emphasis of the present invention.

Referring back to fig. 1A and 1B. A contact layer 106, a barrier layer 108, a metal layer 110, and a hard mask layer 112 are sequentially formed over the memory cell region 100a of the semiconductor substrate 100, which may be defined over the memory cell region 100a by an anisotropic photolithography process that may also define gate features in the peripheral region. Preferably, the material of the contact layer 106 is doped polysilicon, the material of the barrier layer 108 is metal nitride such as titanium nitride, tantalum nitride and/or tungsten nitride, the material of the metal layer 110 is low-resistance metal such as tungsten, aluminum, titanium or tantalum, and the material of the hard mask layer 112 is silicon nitride or silicon oxynitride. A portion of the contact layer 106 is formed in the recess 103 and is electrically connected to the exposed active region 100 b. As can be seen from fig. 1A, a plurality of annular bit line shielding patterns 114 are formed on the semiconductor substrate 100, and the annular bit line shielding patterns 114 are arranged at intervals in a first direction D1, extend in a second direction D2 orthogonal to the first direction D1 and cross the memory cell region 100a, and both ends of the annular patterns are located outside the memory cell region 100 a. In the cross-sectional view of fig. 1B, the bit line shielding pattern 114 passing through the memory cell region 100a is located on the hard mask layer 112, and preferably aligned with the underlying portion of the recess 103 and the device isolation layer 102. The material of the bit line shielding pattern 114 may be a material having etch selectivity to the underlying hard mask layer 112, such as silicon oxide, which may be formed by a double pattern (double patterning) method. For example, the step of forming the ring patterns may include (1) forming a plurality of sacrificial patterns on the bit line material layer, the sacrificial patterns being arranged on the memory cell region 100a at equal intervals along the first direction D1 and extending in the second direction D2, (2) forming spacers on sidewalls of the sacrificial patterns, and (3) removing the sacrificial patterns such that the spacers form the ring bit line shielding patterns.

Please refer to fig. 2A and fig. 2B simultaneously. After the above-described layer structure and the bit line shield pattern 114 are formed, a trimming photoresist 116 is then formed on the bit line shield pattern 114. As shown in fig. 2A, the photoresist 116 covers the area outside the memory cell region 100a, including the two ends of the ring patterns in the second direction D2, and covers the bit line shielding pattern 114 located on the memory cell region 100a and located at the outermost side in the first direction D1, but exposes other bit line shielding pattern 114 located on the memory cell region 100 a. Thus, it can be seen that the layer structure of the memory cell region 100a is also covered by the photoresist 116, and the ring patterns exposed from the photoresist 116 become a plurality of bit line shielding patterns 114 extending in the second direction D2.

Please refer to fig. 3A and fig. 3B at the same time. After the formation of the photoresist 116, an etching process is performed using the photoresist 116 and the bit line shielding pattern 114 as masks to remove the exposed layer structure including the contact layer 106, the barrier layer 108, the metal layer 110 and the hard mask layer 112, thereby forming the bit line BL and the dummy bit line DBL structures on the memory cell region 100 a. As can be seen from fig. 3A, the bit lines BL and the dummy bit lines DBL are arranged at equal intervals in the first direction D1 and extend through the memory cell region 100a in the second direction D2, and the two dummy bit lines DBL are located at the outermost side in the 1 st direction D1. As can be seen from fig. 3B, the dummy bit line DBL and the bit line BL have the same composition and layer structure, and the formed bit line BL is electrically connected to the underlying active region 100B through the contact layer 106, and the contact layer 106 of the dummy bit line DBL in the recess 103 and the sidewall of the recess 103 form a smaller trench 105. The dummy bit line DBL located at the outermost side of the memory cell region 100a is partially located in the recess 103 and is electrically connected to the active region 100b below. Due to the trimming process described above, the width W1 of the dummy bit line DBL in the first direction D1 is greater than the width W2 of the bit line BL in the first direction D1. Forming the dummy bit line DBL having a larger width at the outermost side of the memory cell region 100a helps to improve the problem of the conventional outermost bit line structure that is deformed or easily collapsed due to the micro-loading effect. Furthermore, the design of forming the dummy bit line DBL on the recess surface and the substrate surface having different levels at the same time can make the outermost dummy bit line DBL more stable and less prone to collapse.

Please refer to fig. 4. After the bit line BL and the dummy bit line DBL are formed, a bit line spacer 118 is then formed in the trench 105. The bit line spacers 118 may be formed of an insulating material having an etch selectivity with respect to the insulating layer 104, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. After the formation of the bit line spacers 118, spacers 120, 122 are then formed on both sides of the bit line BL and the dummy bit line DBL, which may be formed by a deposition process as well as an anisotropic etching process. As can be seen from fig. 4, the width W4 of the spacers 122 located outside the dummy bit line DBL in the first direction D1 is larger than the width W3 of the spacers 120 located inside the dummy bit line DBL and the spacers 120 located on both sides of the bit line BL in the first direction D1. The spacers 120 inside the dummy bit line DBL may be located on the bit line spacers 118, and a portion of the deposited layer may remain on the surface of the insulating layer 104 to connect adjacent spacers 120. The material of the partition walls 120, 122 may be silicon oxide, silicon nitride, or a combination thereof.

Fig. 5 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the invention. In addition to the spacer aspects described above, the present invention may have other spacer aspects. As shown in fig. 5, in this embodiment, the trench 105 is not filled with the bit line spacers 118, and the spacers 120 on the inner side of the dummy bit line DBL and on the two sides of the bit line BL may also be a multi-layer structure including two conformal spacer layers 124, 126 distributed along the sidewalls on the inner side of the dummy bit line DBL and on the two sides of the bit line BL, the trench 105, and the surface of the insulating layer 104. The spacer 122 located outside the dummy bit line DBL has a single-layer structure. In other embodiments, the spacer layer 126 may fill the trench 105. The material of the spacer layers 124, 126 may be silicon oxide or silicon nitride, respectively. In this embodiment, the spacers 122 on both sides of the dummy bit line DBL are not equal in height to the bottom surfaces of the spacers 124, 126, and the width of the spacers 122 in the first direction D1 is also greater than the width of the spacers 124, 126.

Fig. 6 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the invention. In addition to the two aspects described above, other aspects of the spacer wall are also possible. In the embodiment of fig. 6, the original trench 105 is not filled with the bit line spacers 118, and a spacer 128 may be formed inside the dummy bit line DBL and on both sides of the bit line BL. The original trench 105 is then etched by an anisotropic etching process to become a trench 130 having a depth deeper than the original trench 103. This has the advantage that the isolation between the dummy bit line DBL and the adjacent bit line BL can be further improved.

Fig. 7 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the invention. After the formation of the bit line spacers 118 and the spacers 120, the storage node contact structure SC may be formed on the active region 100c between the bit lines BL, which may include first forming spacers (not shown) between the bit lines BL, then performing an anisotropic etching process with the photoresist, the spacers and the bit lines BL (including the spacers 120 on both sides thereof) as an etching mask to remove the insulating layer 104 between the spacers and the bit lines BL, exposing the underlying active region 100c, which is the contact region 131 for the storage node formation. This etching step may remove portions of the bit line spacers 118 and the active region 100c, and care should be taken that regions outside the memory cell region 100a (e.g., regions outside the dummy bit line DBL) are protected from etching by photoresist. After the contact region 131 is formed, a storage node contact structure SC is formed on the contact region 131, which may include, in order, a polysilicon layer 132, a silicide layer 134, a barrier layer 136, and a metal layer 138, as shown. The polysilicon layer 132 may be doped polysilicon, which directly contacts the exposed contact region 131 of the substrate. Silicide layer 134 may include titanium silicide, cobalt silicide, nickel silicide, tungsten silicide, platinum silicide, molybdenum silicide, and/or the like. The metal layer 138 may be tungsten, aluminum, titanium, tantalum, or the like. The barrier layer 136 may comprise a nitride of a metal material such as tungsten, aluminum, titanium, or tantalum. After the storage node contact structure SC is formed, a contact isolation structure is formed above the storage node contact structure SC and is connected to a charge storage component such as a capacitor, which is not shown in the following figures for simplicity.

Fig. 8 is a schematic cross-sectional view of a semiconductor structure according to a preferred embodiment of the invention. The structure of this embodiment is similar to that of fig. 7, except that fig. 8 is a memory node contact structure SC formed on the active region 100c between the bit lines BL following the structure of fig. 6, and it can be seen that the depth of the trench 130 inside the dummy bit line DBL is lower than the depth of the recess 103 where the dummy bit line DBL is located and lower than the depth of the trench 105 where the bit line BL is located. Bit line spacers 118 and 119 are formed in both the trench 130 and the trench 105. Note that in this embodiment, because trench 130 is lower, the top surface of bit line spacers 118 located in trench 130 is lower than the top surface of bit line spacers 119 located in trench 105. The bit line spacers 118, 119 may be formed of an insulating material having an etch selectivity with respect to the insulating layer 104, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. After the bit line spacers 118 and 119 are formed, another spacer 120 is formed on both sides of the bit line BL and the dummy bit line DBL, and the material may be silicon oxide, silicon nitride, or a combination thereof. The bottom surfaces of the spacers 120, 122 on both sides of the dummy bit line are not equal in height because the top surface of the bit line spacer 118 is lower. Because the inner sidewall of the dummy bit line DBL and the surface of the trench 130 are further formed with the spacer 128, the spacer 128 and the spacer 120 are integrally formed as a multi-layered spacer structure, and the spacer 122 located outside the dummy bit line DBL is formed as a single-layered structure. Thereafter, a storage node contact structure SC process is performed as described in fig. 7, and a storage node contact structure SC is formed on the active region 100c between the bit line BL and the dummy bit line DBL. The advantage of this embodiment is that the deeper trench 130 may further improve the isolation between the dummy bit line DBL and the adjacent bit line BL.

Referring to fig. 9, a cross-sectional view of a semiconductor structure according to another embodiment of the invention is shown. The structure of this embodiment is similar to that of fig. 8, except that the bit line spacers 118 in the trenches 130 in fig. 9 do not fill the trenches 130, but are formed in the trenches 130 in a conformal fashion, and portions of the spacer 120 extend into the bit line spacers 118. Likewise, the uppermost top surface of bit line spacers 118 in trench 130 in this embodiment may be lower than the top surface of bit line spacers 119 in trench 105.

Referring to fig. 10, a cross-sectional view of a semiconductor structure according to another embodiment of the invention is shown. The structure of this embodiment is similar to that of fig. 8, except that the bit line spacers 118 are not formed in the trenches 130 of fig. 10, and the subsequently formed spacers 120 directly fill the entire trenches 130 along the sidewalls of the dummy bit lines DBL. Bit line spacers 119 are formed in the trenches 105 on both sides of the bit line BL.

Finally, please refer to fig. 11, which is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present invention. The structure of this embodiment is similar to that of fig. 10, except that the spacer 128 originally formed on the surface of the trench 130 in a co-running manner in fig. 11 does not completely cover the surface of the trench 130, and part of the spacer 128 located at the bottom surface of the trench 130 is removed due to the anisotropic etching, exposing the active region 100b. In this way, the spacers 120 formed subsequently fill the entire trench 130 directly along the sidewalls of the dummy bit line DBL and directly contact the exposed active region 100b.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor structure, comprising:

A substrate having a memory cell region defined thereon and further comprising a plurality of recesses and active regions;

A plurality of bit lines are arranged at equal intervals along a first direction on the memory cell region and extend in a second direction orthogonal to the first direction; and

a dummy bit line located at an outermost side of the bit lines in the first direction and extending toward the second direction;

The width of the dummy bit line in the first direction is greater than the width of the bit lines in the first direction, and the bottoms of the dummy bit line are not on the same horizontal plane;

These bit lines have the same composition and layer structure as the dummy bit line, which includes a contact layer, a conductive layer and a hard mask layer in sequence from the substrate upward. The contact layer of the bit line is located in one of the grooves and is electrically connected to one of the active areas through the groove and forms a first trench with the sidewall of the groove. The contact layer of a portion of the dummy bit line is located in one of the grooves and is electrically connected to one of the active areas and forms a second trench with the sidewall of the groove, wherein the depth of the second trench is lower than the depth of the first trench.

2 . The semiconductor structure according to claim 1 , wherein a depth of the first trench is the same as a depth of the recess.

3. The semiconductor structure as described in claim 1 is characterized in that a conformal spacer layer is formed on the sidewalls on both sides of the bit lines, on the sidewalls on the inner side of the dummy bit line, on the surface of the first trench and on the surface of the second trench, and further includes spacers formed on the sidewalls on both sides of the bit lines and on both sides of the dummy bit line.

4 . The semiconductor structure according to claim 3 , wherein the spacer on the inner sidewall of the dummy bit line passes through the spacer layer and directly contacts the active region of the substrate below.

5. The semiconductor structure as claimed in claim 1 , wherein a first bit line spacer is filled in the first trench, a second bit line spacer is filled in the second trench, and further comprising spacers formed on sidewalls on both sides of the bit lines, on sidewalls on both sides of the dummy bit line, on the first bit line spacer, and on the second bit line spacer.

6 . The semiconductor structure of claim 5 , wherein a top surface of the second bit line spacer is lower than a top surface of the first bit line spacer.

7 . The semiconductor structure according to claim 5 , wherein the second bit line spacer is conformally formed on the surface of the second trench, and a portion of the spacer extends into the second bit line spacer.

8. The semiconductor structure as described in claim 5 is characterized in that the width of the partition wall located on the outside of the dummy bit line in the first direction is greater than the width of the partition wall located on the inside of the dummy bit line in the first direction and greater than the width of the partition walls of the bit lines in the first direction.

9 . The semiconductor structure according to claim 5 , wherein bottom surfaces of the spacers on both sides of the dummy bit line are not at the same height.

10 . The semiconductor structure according to claim 5 , wherein the spacer located outside the dummy bit line is a single-layer spacer structure, and the spacer located inside the dummy bit line is a multi-layer spacer structure.