CN114661086A - Band-gap reference voltage source circuit - Google Patents

Abstract

The invention discloses a bandgap reference voltage source circuit, comprising a pre-adjustment voltage circuit for generating a pre-adjustment voltage; a pseudo-cascode current mirror circuit connected to the pre-adjustment voltage circuit for performing current mirroring according to the pre-adjustment voltage The processing generates a first voltage signal and a second voltage signal with equal voltage values; a negative feedback operational amplifier loop is connected to a pre-adjusted voltage circuit and a pseudo-cascode current mirror circuit, and is used for comparing the first voltage signal and the second voltage signal according to the pre-adjusted voltage. The second voltage signal is subjected to negative feedback adjustment processing to ensure that the voltage values of the first voltage signal and the second voltage signal remain equal, and the corresponding bandgap reference voltage is output; the boost circuit is connected to the negative feedback op amp loop and is used for The bandgap reference voltage is boosted; the preconditioning voltage circuit is connected to the boosting circuit, and is also used for updating the preconditioning voltage according to the boosted bandgap reference voltage. The invention effectively saves the chip area and power consumption, and improves the PSRR performance of the bandgap reference voltage.

Description

A bandgap voltage reference circuit

technical field

The invention belongs to the technical field of integrated circuit design, in particular to a bandgap reference voltage source circuit.

Background technique

The reference voltage is one of the basic analog unit circuits in integrated circuit design. The reference voltage can provide voltages that do not vary with temperature and power supply voltage for other modules in the system, such as analog-to-digital converters (ADC), digital-to-analog converters (DAC), power management and voltage Controlled oscillator (Voltage-Controlled Oscillator, referred to as VCO) and other module circuits. Therefore, the reference voltage is an important content in the current integrated circuit design.

The base-emitter voltage V _BE of a bipolar transistor (Bipolar Junction Transistor, BJT for short) exhibits a negative temperature coefficient characteristic. Under unequal collector currents, the difference ΔV _BE of the base-emitter voltages of the two bipolar transistors is proportional to the absolute temperature, that is, it exhibits a positive temperature coefficient characteristic. The basic principle of the generation of the bandgap reference voltage is to use the negative temperature coefficient voltage of _VBE and the positive temperature coefficient voltage of _ΔVBE with appropriate weights to obtain a bandgap reference voltage with zero temperature coefficient. Up to now, most of the bandgap voltage reference circuits that have been proposed need an additional start-up circuit to eliminate the existence of the degeneracy point, otherwise the bandgap voltage reference circuit will not work after the power is turned on; In practical applications, the fluctuation of the power supply voltage will also affect the accuracy of the bandgap reference voltage. Therefore, these circuits affected by the fluctuation of the power supply voltage will use an external linear regulator to power the bandgap reference voltage source circuit separately to improve the bandgap reference voltage. The Power Supply Rejection Ratio (PSRR) of the voltage source circuit.

However, the above-mentioned method of additionally designing a start-up circuit and an external linear regulator has limited improvement in the PSRR performance of the bandgap reference voltage source circuit, and increases the area and power consumption of the chip.

SUMMARY OF THE INVENTION

In order to solve the above problems existing in the prior art, the present invention provides a bandgap reference voltage source circuit. The technical problem to be solved by the present invention is realized by the following technical solutions:

An embodiment of the present invention provides a bandgap reference voltage source circuit, including a pre-adjustment voltage circuit, a pseudo-cascode current mirror circuit, a negative feedback operational amplifier loop, and a boost circuit, wherein,

the pre-regulation voltage circuit for generating a pre-regulation voltage;

The pseudo-cascode current mirror circuit is connected to the pre-adjustment voltage circuit, and is configured to perform current mirror processing according to the pre-adjustment voltage to generate a first voltage signal and a second voltage signal with equal voltage values;

The negative feedback operational amplifier loop is connected to the pre-regulated voltage circuit and the pseudo-cascode current mirror circuit, and is used for pairing the first voltage signal and the second voltage signal according to the pre-regulated voltage performing a negative feedback adjustment process to ensure that the voltage values of the first voltage signal and the second voltage signal remain equal, and outputting a corresponding bandgap reference voltage;

the boosting circuit, connected to the negative feedback operational amplifier loop, for boosting the bandgap reference voltage;

The pre-regulating voltage circuit is connected to the boosting circuit, and is further configured to update the pre-regulating voltage according to the boosted bandgap reference voltage.

In an embodiment of the present invention, the pre-conditioning voltage circuit includes a resistor R1, a transistor NM1 and a transistor NM2, wherein,

One end of the resistor R1 and the drain of the transistor NM1 are connected to the power supply voltage VDD, the gate of the transistor NM1 is connected to the other end of the resistor R1 and the drain of the transistor NM2, and the source of the transistor NM1 is connected The pole is connected to the pseudo-cascode current mirror circuit, the negative feedback operational amplifier loop, and the boost circuit, the gate of the transistor NM2 is connected to the negative feedback operational amplifier loop, and the transistor NM2 is connected to the negative feedback operational amplifier loop. The source of NM2 is grounded to GND.

In an embodiment of the present invention, the pseudo-cascode current mirror circuit includes transistors PM1-PM4, wherein,

The source of the transistor PM1 and the source of the transistor PM2 are connected to the pre-conditioning voltage circuit, the gate of the transistor PM1 is connected to the gate of the transistor PM2, the gate of the transistor PM3, the The drain of the transistor PM3, the gate of the transistor PM4, the negative feedback operational amplifier loop, and the output terminal of the first voltage signal are connected, and the drain of the transistor PM1 is connected to the source of the transistor PM3 , the drain of the transistor PM2 is connected to the source of the transistor PM4, and the drain of the transistor PM4 is connected to the negative feedback operational amplifier loop and the output end of the second voltage signal.

In an embodiment of the present invention, the negative feedback operational amplifier loop includes transistors PM5-PM8, transistor NM3, transistor NM4, transistor Q1, transistor Q2, resistor R2 and resistor R3, wherein,

The source of the transistor PM5 is connected to the pre-regulated voltage circuit, the gate of the transistor PM5 is connected to the gate of the transistor PM2, the gate of the transistor PM6 is connected to the gate of the transistor PM4, The drain of the transistor PM5 is connected to the source of the PM6, the drain of the transistor PM6 is connected to the source of the transistor PM7 and the source of the transistor PM8, and the gate of the transistor PM7 is connected to the source of the transistor PM7. The output terminal of the first voltage signal and the collector of the transistor Q1 are connected, and the drain of the transistor PM7 is connected to the drain of the transistor NM3, the gate of the transistor NM3, and the gate of the transistor NM4. , the source of the transistor NM3 and the source of the transistor NM4 are grounded to GND, the gate of the transistor PM8 is connected to the output end of the second voltage signal and the collector of the transistor Q2, the transistor PM8 The drain of the transistor NM4 is connected to the drain of the transistor NM4 and the pre-regulated voltage circuit, the base of the transistor Q1 is connected to the base of the transistor Q2, the boost circuit, and the output of the bandgap reference voltage The emitter of the transistor Q1 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to the emitter of the transistor Q2 and one end of the resistor R3, and the other end of the resistor R3 is connected Ground GND.

In an embodiment of the present invention, the ratio of the junction area of the emitter of the transistor Q1 to the junction area of the emitter of the transistor Q2 is N, where N is an integer greater than 1.

In an embodiment of the present invention, the current flowing through the resistor R3 is twice the current flowing through the resistor R2.

In an embodiment of the present invention, the bandgap reference voltage formula is expressed as:

Wherein, VREF is the bandgap reference voltage, _VBE is the voltage between the base and the emitter of the transistor Q2, and has a first-order negative temperature coefficient characteristic, V _T is a thermal voltage, and has a first-order positive Temperature coefficient characteristics, N is the ratio of the junction area of the emitter of the transistor Q1 to the junction area of the emitter of the transistor _Q2 , _R3 is the resistance value of the resistor R3, R2 is the resistance of the resistor R2 value.

In an embodiment of the present invention, the negative feedback operational amplifier loop further includes a capacitor C1, one end of the capacitor C1 is connected to the drain of the transistor PM2, and the other end of the capacitor C1 is connected to the transistor NM4 the drain connection.

In an embodiment of the present invention, the boost circuit includes a resistor R4 and a resistor R5, wherein,

One end of the resistor R4 is connected to the pre-adjustment voltage circuit, the other end of the resistor R4 is connected to one end of the resistor R5 and the output end of the bandgap reference voltage, and the other end of the resistor R5 is grounded to GND .

In one embodiment of the present invention, the updated preconditioning voltage formula is expressed as:

Wherein, _{VDD_BGR} is the updated pre _- adjustment voltage, R4 is the resistance value of the resistor R4, R5 is the resistance value of the resistor R5, and VREF is the bandgap reference voltage.

Beneficial effects of the present invention:

The bandgap reference voltage source circuit proposed by the present invention effectively saves chip area and power consumption, and improves the PSRR performance of the bandgap reference voltage, specifically:

Under the power supply of the pre-regulated voltage provided by the pre-regulated voltage circuit, the pseudo-cascode current mirror circuit generates the first voltage signal and the second voltage signal with the same voltage value through the current mirror processing, and the first voltage signal and the second voltage signal with the same voltage value are generated by the current mirror process. Under the negative feedback adjustment, the voltage values of the first voltage signal and the second voltage signal are always kept equal, thereby outputting a stable bandgap reference voltage, thereby improving the PSRR performance of the bandgap reference voltage.

At the same time, the present invention updates the internal power supply pre-regulating voltage of the pre-regulating voltage circuit through the booster circuit, and the pre-regulating voltage is independent of the power supply voltage, but achieves a stable power supply voltage through the band gap reference voltage output by the band gap reference voltage source circuit. , so as to avoid the influence on the bandgap reference voltage due to the fluctuation of the power supply voltage; because there is no need for an additional linear regulator to stabilize the power supply voltage, and at the same time, the self-starting of the circuit can be realized without the need for an additional startup circuit, which can effectively save chip area and power consumption.

The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

Description of drawings

1 is a schematic structural diagram of a bandgap reference voltage source circuit provided by an embodiment of the present invention;

2 is a schematic diagram of a specific circuit structure of a bandgap reference voltage source circuit provided by an embodiment of the present invention;

3 is a schematic diagram of a specific circuit structure of another bandgap reference voltage source circuit provided by an embodiment of the present invention;

4 is a schematic diagram of a simulation result of a bandgap reference voltage correspondingly generated by a bandgap reference voltage source circuit provided in an embodiment of the present invention in a temperature variation range of -45°C to 125°C;

FIG. 5 is a schematic diagram of a corresponding PSRN simulation result under a bandgap reference voltage source circuit provided by an embodiment of the present invention.

Description of reference numbers:

10- pre-regulating voltage circuit; 20- pseudo-cascode current mirror circuit; 30- negative feedback op amp loop; 40- boost circuit.

Detailed ways

The present invention will be described in further detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

Example 1

In order to improve the accuracy of the reference voltage output by the bandgap reference voltage source circuit without increasing the chip area and power consumption, an embodiment of the present invention proposes a bandgap reference voltage source circuit, please refer to FIG. The gap reference voltage source circuit includes a pre-regulated voltage circuit 10, a pseudo-cascode current mirror circuit 20, a negative feedback operational amplifier loop 30 and a boost circuit 40, wherein,

a pre-regulation voltage circuit 10 for generating a pre-regulation voltage VDD_BGR;

The pseudo-cascode current mirror circuit 20 is connected to the pre-adjustment voltage circuit 10, and is configured to perform current mirror processing according to the pre-adjustment voltage VDD_BGR to generate a first voltage signal V _X and a second voltage signal V _Y with equal voltage values;

The negative feedback operational amplifier loop 30 is connected to the pre-adjustment voltage circuit 10 and the pseudo-cascode current mirror circuit 20, and is used for negative feedback adjustment of the first voltage signal V _X and the second voltage signal V _Y according to the pre-adjustment voltage VDD_BGR processing to ensure that the voltage values of the first voltage signal V _X and the second voltage signal V _Y remain equal, and output the corresponding bandgap reference voltage VREF;

The boosting circuit 40 is connected to the negative feedback operational amplifier loop 30, and is used for boosting the bandgap reference voltage VREF;

The pre-adjustment voltage circuit 10 is connected to the booster circuit 40, and is also used for updating the pre-adjustment voltage VDD_BGR according to the boosted bandgap reference voltage VREF.

Next, each part of the circuit is introduced in detail in the embodiments of the present invention.

The embodiment of the present invention provides an optional solution of a pre-adjustment voltage circuit 10. Referring to FIG. 2, the pre-adjustment voltage circuit 10 includes a resistor R1, a transistor NM1 and a transistor NM2, wherein one end of the resistor R1 and the drain of the transistor NM1 The pole is connected to the power supply voltage VDD, the gate of the transistor NM1 is connected to the other end of the resistor R1 and the drain of the transistor NM2, the source of the transistor NM1 is connected to the pseudo-cascode current mirror circuit 20, the negative feedback operational amplifier loop 30, the The voltage circuit 40 is connected, the gate of the transistor NM2 is connected to the negative feedback operational amplifier loop 30, and the source of the transistor NM2 is grounded to GND.

Preferably, the transistor NM1 and the transistor NM2 are both NMOS transistors.

Further, the embodiment of the present invention provides an optional solution of a pseudo-cascode current mirror circuit 20. Please refer to FIG. 2 again. The pseudo-cascode current mirror circuit 20 includes transistors PM1-PM4, wherein the transistors The source of PM1 and the source of transistor PM2 are connected to the source of transistor NM1 in the preconditioning voltage circuit 10, the gate of transistor PM1 is connected to the gate of transistor PM2, the gate of transistor PM3, the drain of transistor PM3, and the gate of transistor PM4 The gate of the negative feedback operational amplifier loop 30 and the output terminal of the first voltage signal V _X are connected, the drain of the transistor PM1 is connected to the source of the transistor PM3, the drain of the transistor PM2 is connected to the source of the transistor PM4, and the transistor PM1 is connected to the source of the transistor PM4. The drain of PM4 is connected to the negative feedback operational amplifier loop 30 and the output terminal of the second voltage signal V _Y.

Preferably, the transistors PM1 to PM4 are all PMOS transistors.

Further, the embodiment of the present invention provides an optional solution of the negative feedback operational amplifier loop 30. Please refer to FIG. 2 again. The negative feedback operational amplifier loop 30 includes transistors PM5-PM8, transistors NM3, transistors NM4, and triodes. Q1, transistor Q2, resistor R2 and resistor R3, wherein the source of the transistor PM5 is connected to the source of the transistor NM1 in the preconditioning voltage circuit 10, the gate of the transistor PM5 is connected to the gate of the transistor PM2, and the gate of the transistor PM6 It is connected to the gate of the transistor PM4, the drain of the transistor PM5 is connected to the source of PM6, the drain of the transistor PM6 is connected to the source of the transistor PM7 and the source of the transistor PM8, and the gate of the transistor PM7 is connected to the first voltage signal V The output terminal of _X and the collector of the transistor Q1 are connected, the drain of the transistor PM7 is connected to the drain of the transistor NM3, the gate of the transistor NM3 and the gate of the transistor NM4, the source of the transistor NM3 and the source of the transistor NM4 are connected to the ground GND , the gate of the transistor PM8 is connected to the output terminal of the second voltage signal V _Y and the collector of the transistor Q2, the drain of the transistor PM8 is connected to the drain of the transistor NM4, and the gate of the transistor NM2 in the pre-conditioning voltage circuit 10 is connected, and the transistor The base of Q1 is connected to the base of the transistor Q2, the booster circuit 40 and the output end of the bandgap reference voltage VREF, the emitter of the transistor Q1 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the emitter of the transistor Q2, One end of the resistor R3 is connected, and the other end of the resistor R3 is grounded to GND. Wherein, the ratio of the junction area of the emitter of the transistor Q1 to the junction area of the emitter of the transistor Q2 in the embodiment of the present invention is N, where N is an integer greater than 1; the current flowing through the resistor R3 is 2 times the current flowing through the resistor R2 times.

Preferably, the transistors PM5 to PM8 are all PMOS transistors; the transistors NM3 and NM4 are both NMOS transistors.

Further, in order to ensure the stability of the negative feedback op amp loop 30 in the bandgap reference voltage source circuit, the embodiment of the present invention provides another optional solution of the negative feedback op amp loop 30, please refer to FIG. 3, in the Based on the circuit shown in FIG. 2, the negative feedback operational amplifier loop 30 further includes a capacitor C1, one end of the capacitor C1 is connected to the drain of the transistor PM2, and the other end of the capacitor C1 is connected to the drain of the transistor NM4.

Further, the embodiment of the present invention provides an optional solution of the booster circuit 40. Please refer to FIG. 2 again. The booster circuit 40 includes a resistor R4 and a resistor R5, wherein one end of the resistor R4 is connected to the pre-adjustment voltage circuit 10. The source of the middle transistor NM1 is connected, the other end of the resistor R4 is connected to one end of the resistor R5, the output end of the bandgap reference voltage VREF, and the other end of the resistor R5 is grounded to GND.

Based on the specific circuit designs of the above-mentioned parts, the working principle of the bandgap reference voltage source circuit proposed in the embodiment of the present invention is described in detail next.

The embodiment of the present invention can realize self-starting without adding a startup circuit. Specifically, before the power supply voltage VDD is powered on, the internal circuit of the bandgap reference voltage source circuit is in a closed state; when the power supply voltage VDD is powered on, the pre-adjustment voltage circuit The transistor NM1 in 10 is first in the off state. Due to the pull-up effect of the resistor R1, the gate voltage of the transistor NM2 is the power supply voltage VDD. At this time, the transistor NM2 and the resistor R4 and the resistor R5 in the boost circuit 40 form a source follower. Therefore, the resistor R5, the base of the transistor Q1 and the base of the transistor Q2 will have a bias voltage. At this time, a current will be generated inside the bandgap reference voltage source circuit, so that in the negative feedback op amp loop 30 negative Under feedback regulation, the bandgap reference circuit will start up.

In the embodiment of the present invention, the transistor PM1 and the transistor PM3, the transistor PM2 and the transistor PM4 in the pseudo-cascode current mirror circuit 20 form a current mirror structure, and the current mirror ratio is 1:1. At this time, the pseudo-cascode current The mirror circuit 20 realizes current mirroring of the first voltage signal V _X at the output point X and the second voltage signal V _Y at the output point Y, that is, the voltage values of the first voltage signal V _X and the second voltage signal V _Y are equal. However, in the actual process, the first voltage signal V _X and the second voltage signal V _Y are not always equal, so that the bandgap reference voltage output by the bandgap reference voltage source circuit is not stable. Based on this problem, the inventor designed a negative feedback op-amp loop 30. Due to the function of the negative-feedback op-amp loop 30, the changed first voltage signal V _X or second voltage signal V _Y is adjusted back to the original voltage value, that is, the clamping process of the first voltage signal V _X corresponding to the output point X and the second voltage signal V _Y corresponding to the output point Y is realized, so that the first voltage signal V _X and the second voltage signal V _Y The voltage value of the transistor Q1 remains the same, so the currents flowing through the two branches of the collector of the transistor Q1 and the collector of the transistor Q2 are equal. Therefore, the current flowing through resistor R2 and the current flowing through resistor R3 are expressed as:

I _R3 = 2I _R2 (2)

Among them, I _R2 in the formula (1) is the current flowing through the resistor R2, V _BE1 and V _BE are the voltages between the base-emitter of the transistor Q1 and the transistor Q2, respectively, and both V _BE1 and V _BE have The first-order negative temperature coefficient characteristic, V _T is the thermal voltage, and V _T has the first-order positive temperature coefficient characteristic, R ₂ is the resistance value of the resistor R2, N is the junction area of the emitter of the transistor Q1 and the emitter of the transistor Q2. The ratio of the junction area; I _R3 in the formula (2) is the current flowing through the resistor R3.

It can be known from the KVL law that the bandgap reference voltage VREF output by the bandgap reference voltage source circuit proposed in the embodiment of the present invention is expressed as:

Wherein, VREF in the formula (3) is the bandgap reference voltage, and _R3 is the resistance value of the resistor R3. Since V _BE in formula (3) has a first-order negative temperature coefficient characteristic, and V _T has a first-order positive temperature coefficient characteristic, by adjusting the resistance values of resistor R2 and resistor R3, the zero temperature coefficient after first-order temperature compensation can be obtained Bandgap reference voltage VREF.

In the embodiment of the present invention, the resistor R4 and the resistor R5 in the booster circuit 40 can also be used to update the pre-adjustment voltage VDD_BGR inside the pre-adjustment voltage circuit 10 , and the update of the pre-adjustment voltage VDD_BGR is expressed as:

Among them, VDD_BGR is the updated pre-adjustment voltage, R ₄ is the resistance value of the resistor R4, R ₅ is the resistance value of the resistor R5, and VREF is the bandgap reference voltage.

Because the transistor NM1 isolates the power supply voltage VDD, the power supply voltage VDD will not directly affect the pre-regulation voltage VDD_BGR internally supplied by the pre-regulation voltage circuit 10 through the transistor NM1 . At the same time, the power supply voltage VDD will directly affect the bandgap reference voltage VREF through the resistor R1 and the source-follower structure composed of the transistor NM1, the resistor R4 and the resistor R5. However, due to the two-stage high-gain negative feedback operational amplifier composed of transistor PM7, transistor PM8, and transistors NM1-NM3, the voltage regulation of the bandgap reference voltage VREF can be directly realized. At the same time, the boost circuit 40 composed of resistor R4 and resistor R5 The pre-regulating voltage VDD_BGR with sufficient voltage margin can be generated to ensure the stability of the pre-regulating voltage VDD_BGR inside the pre-regulating voltage circuit 10 , so that the pre-regulating voltage VDD_BGR is no longer affected by the power supply voltage VDD. Through the above solution, the PSRR performance of the bandgap reference voltage VREF is improved. Moreover, the self-biased cascode structure composed of the transistor PM2 and the transistor PM4 can further improve the PSRR performance of the bandgap reference voltage source circuit.

In order to verify the validity of the bandgap reference voltage source circuit proposed in the embodiment of the present invention, the following experiments are used to verify the validity.

During the experiment, the embodiment of the present invention is simulated on the Cadence Spectre using the 0.18 μm BCD process of CSMC Corporation.

Please refer to FIG. 4 , under the condition that the temperature change range is -45°C to 125°C, the bandgap reference voltage VREF is generated by the bandgap reference band path proposed by the present invention, wherein the abscissa of FIG. 4 represents the temperature, and the ordinate represents the bandgap reference voltage VREF. It can be seen from FIG. 4 that the bandgap reference voltage source circuit proposed by the present invention has good temperature drift characteristics, and the temperature drift coefficient is 23ppm/°C.

Referring to FIG. 5 , the embodiment of the present invention simultaneously simulates the PSRR performance in the process of generating the bandgap reference voltage VREF by the bandgap reference voltage source circuit, wherein the abscissa of FIG. 5 represents the clock frequency, and the ordinate represents the PSRR. It can be seen from FIG. 5 that at a low frequency, the bandgap reference voltage source circuit proposed in the embodiment of the present invention has a very high PSRR, which can reach -91dB.

To sum up, the bandgap reference voltage source circuit proposed in the embodiment of the present invention effectively saves chip area and power consumption, and improves the PSRR performance of the bandgap reference voltage VREF, specifically:

Under the power supply of the pre-adjustment voltage VDD_BGR provided by the pre-adjustment voltage circuit 10, the pseudo-cascode current mirror circuit 20 generates the first voltage signal V _X and the second voltage signal V _Y with the same voltage value through the current mirror process, and the Under the negative feedback adjustment of the negative feedback op amp loop 30, the voltage values of the first voltage signal V _X and the second voltage signal V _Y are always kept equal, thereby outputting a stable bandgap reference voltage VREF, thereby increasing the bandgap reference voltage PSRR performance of VREF.

Meanwhile, in the embodiment of the present invention, the internal power supply pre-regulation voltage VDD_BGR of the pre-regulation voltage circuit 10 is updated by the booster circuit 40 . The pre-regulation voltage VDD_BGR has nothing to do with the power supply voltage VDD, but is a band-gap reference output by the band-gap reference voltage source circuit. voltage VREF to achieve a stable power supply voltage, thus avoiding the influence of the fluctuation of the power supply voltage VDD on the bandgap reference voltage VREF; because there is no need for an additional linear regulator to stabilize the power supply voltage, and no additional startup circuit is required. The self-starting of the circuit can be realized, and the chip area and power consumption can be effectively saved.

In the description of the present invention, it should be understood that the terms "first" and "second" are only used for description purposes, and cannot be interpreted as indicating or implying relative importance or the number of indicated technical features. Thus, a feature defined as "first" or "second" may expressly or implicitly include one or more of that feature. In the description of the present invention, "plurality" means two or more, unless otherwise expressly and specifically defined.

In the description of this specification, description with reference to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples", etc., mean specific features described in connection with the embodiment or example , structure, material or feature is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

Although the application is described herein in conjunction with the various embodiments, those skilled in the art will understand and understand from a review of the drawings, the disclosure, and the appended claims in practicing the claimed application. Other variations of the disclosed embodiments are implemented. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that these measures cannot be combined to advantage.

The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be considered that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deductions or substitutions can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (10)

1. A bandgap reference voltage source circuit is characterized in that, comprising a pre-regulated voltage circuit, a pseudo-cascode current mirror circuit, a negative feedback operational amplifier loop and a boost circuit, wherein, the pre-regulation voltage circuit for generating a pre-regulation voltage; The pseudo-cascode current mirror circuit is connected to the pre-adjustment voltage circuit, and is configured to perform current mirror processing according to the pre-adjustment voltage to generate a first voltage signal and a second voltage signal with equal voltage values; the negative feedback op-amp loop is connected to the pre-regulated voltage circuit and the pseudo-cascode current mirror circuit, and is used for pairing the first voltage signal and the second voltage signal according to the pre-regulated voltage performing a negative feedback adjustment process to ensure that the voltage values of the first voltage signal and the second voltage signal are kept equal, and outputting a corresponding bandgap reference voltage; the boosting circuit, connected to the negative feedback operational amplifier loop, for boosting the bandgap reference voltage; The pre-regulating voltage circuit is connected to the boosting circuit, and is further configured to update the pre-regulating voltage according to the boosted bandgap reference voltage. 2 . The bandgap reference voltage source circuit according to claim 1 , wherein the pre-regulated voltage circuit comprises a resistor R1 , a transistor NM1 and a transistor NM2 , wherein, One end of the resistor R1 and the drain of the transistor NM1 are connected to the power supply voltage VDD, the gate of the transistor NM1 is connected to the other end of the resistor R1 and the drain of the transistor NM2, and the source of the transistor NM1 is connected The pole is connected to the pseudo-cascode current mirror circuit, the negative feedback operational amplifier loop, and the boost circuit, the gate of the transistor NM2 is connected to the negative feedback operational amplifier loop, and the transistor NM2 is connected to the negative feedback operational amplifier loop. The source of NM2 is grounded to GND. 3 . The bandgap reference voltage source circuit according to claim 1 , wherein the pseudo-cascode current mirror circuit comprises transistors PM1 to PM4 , wherein, The source of the transistor PM1 and the source of the transistor PM2 are connected to the pre-conditioning voltage circuit, the gate of the transistor PM1 is connected to the gate of the transistor PM2, the gate of the transistor PM3, the The drain of the transistor PM3, the gate of the transistor PM4, the negative feedback operational amplifier loop, and the output terminal of the first voltage signal are connected, and the drain of the transistor PM1 is connected to the source of the transistor PM3 , the drain of the transistor PM2 is connected to the source of the transistor PM4, and the drain of the transistor PM4 is connected to the negative feedback operational amplifier loop and the output end of the second voltage signal. 4. The bandgap reference voltage source circuit according to claim 3, wherein the negative feedback operational amplifier loop comprises transistors PM5-PM8, transistor NM3, transistor NM4, transistor Q1, transistor Q2, resistor R2 and resistor R3, where, The source of the transistor PM5 is connected to the pre-regulated voltage circuit, the gate of the transistor PM5 is connected to the gate of the transistor PM2, the gate of the transistor PM6 is connected to the gate of the transistor PM4, The drain of the transistor PM5 is connected to the source of the PM6, the drain of the transistor PM6 is connected to the source of the transistor PM7 and the source of the transistor PM8, and the gate of the transistor PM7 is connected to the source of the transistor PM7. The output terminal of the first voltage signal and the collector of the transistor Q1 are connected, and the drain of the transistor PM7 is connected to the drain of the transistor NM3, the gate of the transistor NM3, and the gate of the transistor NM4. , the source of the transistor NM3 and the source of the transistor NM4 are grounded to GND, the gate of the transistor PM8 is connected to the output end of the second voltage signal and the collector of the transistor Q2, the transistor PM8 The drain of the transistor NM4 is connected to the drain of the transistor NM4 and the pre-regulated voltage circuit, the base of the transistor Q1 is connected to the base of the transistor Q2, the boost circuit, and the output of the bandgap reference voltage The emitter of the transistor Q1 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to the emitter of the transistor Q2 and one end of the resistor R3, and the other end of the resistor R3 is connected Ground GND. 5 . The bandgap reference voltage source circuit according to claim 4 , wherein the ratio of the junction area of the emitter of the transistor Q1 to the junction area of the emitter of the transistor Q2 is N, and N is greater than 1. 6 . the integer. 6 . The bandgap reference voltage source circuit according to claim 5 , wherein the current flowing through the resistor R3 is twice the current flowing through the resistor R2 . 7. The bandgap reference voltage source circuit according to claim 6, wherein the bandgap reference voltage calculation formula is expressed as:

Wherein, VREF is the bandgap reference voltage, _VBE is the voltage between the base and the emitter of the transistor Q2, and has a first-order negative temperature coefficient characteristic, V _T is a thermal voltage, and has a first-order positive Temperature coefficient characteristics, N is the ratio of the junction area of the emitter of the transistor Q1 to the junction area of the emitter of the transistor _Q2 , _R3 is the resistance value of the resistor R3, R2 is the resistance of the resistor R2 value. 8 . The bandgap reference voltage source circuit according to claim 4 , wherein the negative feedback operational amplifier loop further comprises a capacitor C1 , and one end of the capacitor C1 is connected to the drain of the transistor PM2 . The other end of the capacitor C1 is connected to the drain of the transistor NM4. 9. The bandgap reference voltage source circuit according to claim 4, wherein the boost circuit comprises a resistor R4 and a resistor R5, wherein, One end of the resistor R4 is connected to the pre-adjustment voltage circuit, the other end of the resistor R4 is connected to one end of the resistor R5 and the output end of the bandgap reference voltage, and the other end of the resistor R5 is grounded to GND . 10. The bandgap reference voltage source circuit according to claim 9, wherein the updated pre-regulated voltage formula is expressed as:

Wherein, _{VDD_BGR} is the updated pre _- adjustment voltage, R4 is the resistance value of the resistor R4, R5 is the resistance value of the resistor R5, and VREF is the bandgap reference voltage.

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