CN114662443B - Integrated circuit layout design method, device and readable storage medium - Google Patents

Abstract

The invention relates to an integrated circuit layout design method, a device and a readable storage medium, firstly generating a grid, wherein the grid comprises a plurality of grid points; converting the grid into a matrix, wherein each grid point corresponds to an element of the matrix; judging whether each grid point is in the layout range of the integrated circuit; if so, setting the value of the corresponding element as true; designating all elements with true values as an original layout matrix, wherein the original layout matrix carries the integrated circuit information. The invention can rapidly and efficiently obtain the operation result of the geometric figure.

Description

Integrated circuit layout design method, device and readable storage medium

Technical Field

The present invention generally relates to the field of semiconductors and more particularly to an integrated circuit layout design method, device and readable storage medium.

Background technique

Chip design is mainly divided into two stages: logical design of front-end design and physical design of back-end design. Front-end design is to obtain the gate-level netlist circuit of the chip to achieve specific functions; while physical design is generally based on the GDSII standard layout description language, using binary format to convert the gate-level netlist circuit into layout geometry, topology, structure, hierarchy and other information. Only with this information can the gate-level netlist circuit be made into an integrated circuit in the form of a chip.

During the physical design phase, layout geometry is required in many programs. For example, when designing rules, all the geometry in the layout is compared with the size and spacing specified in the design rules, and all violations of the rules are notified to the developer for adjustment. For example, when evaluating circuit delay operations, calculations are also performed based on layout geometry. In addition, layout planning also needs to make arrangements for chip size, input and output, etc. based on layout geometry.

Therefore, a geometry for computing integrated circuits is urgently needed.

Summary of the invention

In order to at least partially solve the technical problems mentioned in the background technology, the solution of the present invention provides an integrated circuit layout design method, device and readable storage medium.

In one aspect, the present invention discloses an integrated circuit layout design method, comprising: generating a grid, the grid comprising a plurality of grid points; converting the grid into a matrix, each grid point corresponding to an element of the matrix; determining whether each grid point falls within a layout range of the integrated circuit; if so, setting the value of the corresponding element to true; and designating all elements whose values are true as an original layout matrix, the original layout matrix carrying the integrated circuit information.

In another aspect, the present invention discloses a computer-readable storage medium having stored thereon a computer program code for obtaining geometric information of a circuit layout. When the computer program code is executed by a processor, the aforementioned method is executed.

In another aspect, the present invention discloses an integrated circuit layout design device, comprising a generation module, a conversion module, a judgment module, a setting module and a designation module. The generation module is used to generate a grid, the grid comprising a plurality of grid points; the conversion module is used to convert the grid into a matrix, each grid point corresponding to an element of the matrix; the judgment module is used to determine whether each grid point falls within the layout range of the integrated circuit; the setting module is used to set the value of the corresponding element to true when the grid point falls within the layout range; the designation module is used to designate all elements with true values as the original layout matrix, the original layout matrix carrying the integrated circuit information.

The present invention converts the geometric figures of the integrated circuit into a matrix, presents the geometric space in a matrix manner, and uses a related algorithm for graphic calculation based on matrix operations to quickly and efficiently obtain the calculation results of the geometric figures.

BRIEF DESCRIPTION OF THE DRAWINGS

By reading the detailed description below with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood. In the accompanying drawings, several embodiments of the present invention are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

FIG1 is a grid showing an EDA tool;

2 is a flow chart showing an integrated circuit layout design method according to an embodiment of the present invention;

FIG3 is a schematic diagram showing the conversion of grid points into matrix elements according to an embodiment of the present invention;

FIG4 is a schematic diagram showing an exemplary integrated circuit in a grid;

FIG5 is a schematic diagram showing the values of matrix elements according to an embodiment of the present invention;

6 is a flow chart showing an integrated circuit layout design method according to another embodiment of the present invention;

7 is a schematic diagram showing that the original layout matrix according to another embodiment of the present invention is moved one grid point to the right on the grid;

8 is a schematic diagram showing the geometry of a second layout matrix according to another embodiment of the present invention;

9 is a schematic diagram showing the geometry of a third layout matrix according to another embodiment of the present invention;

10 is a schematic diagram showing the geometry of a fifth layout matrix according to another embodiment of the present invention;

11 is a schematic diagram showing the geometry of a fourth layout matrix according to another embodiment of the present invention;

FIG12 is a schematic diagram showing the geometry of a sixth layout matrix according to another embodiment of the present invention; and

FIG. 13 is a structural diagram showing an integrated circuit layout design apparatus according to another embodiment of the present invention.

Detailed ways

The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

It should be understood that the terms "first", "second", "third" and "fourth" etc. in the claims, specifications and drawings of the present invention are used to distinguish different objects rather than to describe a specific order. The terms "include" and "comprise" used in the specification and claims of the present invention indicate the presence of the described features, wholes, steps, operations, elements and/or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and/or their collections.

It should also be understood that the terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention and the claims, the singular forms of "a", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should also be further understood that the term "and/or" used in the specification of the present invention and the claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

As used in this specification and claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context.

The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

Nowadays, chip design is assisted by EDA tools. EDA tools are electronic design automation systems that are software used to achieve goals such as logic compilation simplification, segmentation, layout, and optimization. As shown in FIG1 , each EDA tool display page is provided with a grid 100. The grid 100 includes a plurality of grid points 101, which developers can use to align and layout circuits. The grid 100 is a process manufacturing grid, a standard cell layout grid, a wiring channel grid, or a custom grid.

An embodiment of the present invention is an integrated circuit layout design method for obtaining a geometric pattern of an integrated circuit layout as a reference for subsequent physical design. FIG2 shows a flow chart of this embodiment.

In step 201 , a grid is generated. The grid referred to here is the grid 100 shown in FIG. 1 , which may be a process manufacturing grid, a standard cell layout grid, a wiring channel grid or a custom grid, which forms an array including a plurality of grid points 101 .

In step 202, the grid is converted into a matrix, and each grid point corresponds to an element of the matrix. The grid 100 of FIG1 is a square matrix, and each grid point 101 can be regarded as an element of a matrix. This embodiment matrices the grid, and encodes each grid point according to the rules of the matrix, such as the element a _xy of the matrix, where the subscript x represents the coordinate value of the grid point along the x-axis, and the subscript y represents the coordinate value of the grid point along the y-axis. As shown in FIG3, the grid point 301 is the matrix element a ₁₁ , the grid point 302 is the matrix element a ₂₁ , the grid point 303 is the matrix element a ₁₂ , and so on.

In step 203, it is determined whether each grid point falls within the layout range of the integrated circuit. In the EDA tool, the layout of the integrated circuit is performed based on this grid. FIG4 shows a schematic diagram of an exemplary integrated circuit in the grid, and the layout range 401 of the integrated circuit is the plane area of the integrated circuit. In this step, it is determined whether each grid point falls within the layout range 401 of the integrated circuit, that is, the black area in the figure.

If yes, then step 204 is executed to set the value of the corresponding element to true. In this embodiment, the element value "1" represents true. If no, then step 205 is executed to set the value of the corresponding element to false. In this embodiment, the element value "0" represents false. After step 204 and step 205 are executed, the entire matrix is shown in FIG. 5. The value of the element falling within the layout range of the integrated circuit is 1, and the rest is 0.

Next, in step 206, all elements whose values are true are designated as the original layout matrix, ie, the original layout matrix 501 in FIG. 5. The original layout matrix 501 carries the integrated circuit information, especially the geometric figure information.

This embodiment converts the geometric figure of the integrated circuit into a matrix and presents the geometric space in a matrix manner as a basis for subsequent procedures in the physical design stage.

Another embodiment of the present invention is an integrated circuit layout design method for obtaining the geometry of the integrated circuit layout, and in particular for obtaining edge information of the integrated circuit layout as a reference for subsequent physical design. FIG6 shows a flow chart of this embodiment.

In step 601, a grid is generated. In step 602, the grid is converted into a matrix, and each grid point corresponds to an element of the matrix. In step 603, it is determined whether each grid point falls within the layout range of the integrated circuit. If so, step 604 is executed to set the value of the corresponding element to true. In this embodiment, the element value "1" represents true. If not, step 605 is executed to set the value of the corresponding element to false. In this embodiment, the element value "0" represents false. Then in step 606, all elements with true values are designated as the original layout matrix, which carries the geometric information of the integrated circuit. Steps 601 to 606 are the same as steps 201 to 206, so they are not repeated.

In step 607, the original layout matrix is moved one grid point to one side on the grid to form a first layout matrix. FIG7 shows a schematic diagram of the original layout matrix 501 being moved one grid point to the right on the grid to form a first layout matrix 701. The first layout matrix 701 is completely identical in geometry to the original layout matrix 501, except that the first layout matrix 701 is a new layout matrix formed by moving the original layout matrix 501 one grid point to the right. For the first layout matrix 701, only the elements within the range of the first layout matrix 701 are 1, and the rest are 0.

In step 608, the original layout matrix 501 and the first layout matrix 701 are bitwise ORed to form a second layout matrix. FIG8 shows the geometry of the second layout matrix 801, which is the union of the original layout matrix 501 and the first layout matrix 701. The values of the black elements in the figure are 1, and the rest are 0.

In step 609, the second layout matrix 801 and the original layout matrix 501 are bitwise XORed to form a third layout matrix. The bitwise XOR operation represents that the elements of the intersection of the second layout matrix 801 and the original layout matrix 501 are set to 0, and the elements of the second layout matrix 801 and the original layout matrix 501 that do not intersect are set to 1. FIG. 9 shows the geometric figure of the third layout matrix 901. The third layout matrix 901 carries the geometric edge information on the right side of the layout range (i.e., the original layout matrix 501) of the integrated circuit. The value of the black element in the figure is 1, and the rest is 0. So far, this embodiment obtains the geometric edge information on the right side of the layout range.

In step 610, the third layout matrix 901 is moved one grid point in the opposite direction of the side on the grid to form a fifth layout matrix. For example, in step 607, the third layout matrix 901 is moved one grid point to the right, and this step is to move one grid point to the left, as shown in FIG. 10, to form a fifth layout matrix 1001, which carries the geometric inner edge information of the side.

In step 611, it is determined whether all sides have obtained geometrical outer edge information. If not, return to step 607, move the original layout matrix 501 one grid point to the other side on the grid, and go through steps 608, 609, and 610 to obtain geometrical inner and outer edge information on the other side of the layout range of the integrated circuit. This process continues until all four sides of the layout range have obtained geometrical inner and outer edge information.

If all sides have obtained geometric perimeter information, step 612 is executed to bitwise OR all third layout matrices 901 to form a fourth layout matrix. Figure 11 shows a fourth layout matrix 1101, which carries geometric perimeter information of the circuit layout.

Finally, step 613 is executed to perform bitwise OR on all fifth layout matrices 1001 to form a sixth layout matrix. FIG. 12 shows the sixth layout matrix 1201 , which carries geometric inner perimeter information of the circuit layout.

This embodiment converts the geometry of the integrated circuit into a matrix, and obtains the geometry of the inner and outer edges of each side of the integrated circuit and the information of the inner and outer perimeters of the geometry, which serves as the basis for subsequent procedures in the physical design stage. The following example will illustrate how the aforementioned geometry information is used in the physical design stage.

If the area information of the integrated circuit needs to be obtained in the physical design stage, the original layout matrix 501 can be directly summed. The area of each grid point is known, and the area of the original layout matrix 501 can be obtained by counting the number of elements in the original layout matrix 501 (i.e., the number of elements with a value of 1) and multiplying it by the area of each grid point.

If the integrated circuit needs to be proportionally enlarged in the physical design stage, the original layout matrix 501 and the fourth layout matrix 1101 are first bitwise ORed to form a seventh layout matrix, and then the seventh layout matrix is updated to the original layout matrix 501, so that the original layout matrix 501 is expanded by one grid point on the four sides, and steps 607 to 612 are performed based on the updated original layout matrix 501 to form an updated fourth layout matrix. In this way, the original layout matrix 501 can be enlarged one by one.

If the integrated circuit needs to be scaled down in the physical design stage, the original layout matrix 501 and the sixth layout matrix 1201 are first bitwise XORed to form an eighth layout matrix, and then the eighth layout matrix is updated to the original layout matrix 501, so that the original layout matrix 501 is shrunk inward by one grid point from four sides, and steps 607 to 613 are performed based on the updated original layout matrix 501 to form an updated sixth layout matrix 1201. The original layout matrix 501 can be scaled down in this way.

If the integrated circuit needs to be flipped clockwise or counterclockwise during the physical design stage, the original layout matrix 501 is transposed and then flipped horizontally to obtain a clockwise flip result, and the original layout matrix 501 is transposed and then flipped vertically to obtain a counterclockwise flip result.

If it is necessary to determine whether two integrated circuits intersect during the physical design stage, firstly, steps 601 to 606 are performed for the two integrated circuits to form a first original layout matrix and a second original layout matrix respectively, and then the first original layout matrix and the second original layout matrix are bitwise ANDed to form an intersection matrix, and then it is determined whether there is an element with a value of 1 in the intersection matrix. If so, the two integrated circuits intersect, and if not, the two integrated circuits do not intersect.

If it is necessary to determine whether an integrated circuit is included in another integrated circuit during the physical design stage, firstly, steps 601 to 606 are performed for the two integrated circuits to form a first original layout matrix and a second original layout matrix respectively, then the first original layout matrix and the second original layout matrix are bitwise ORed to form a union matrix, then the first original layout matrix and the union layout matrix are bitwise XORed to form a first XOR matrix, then it is determined whether there is an element with a value of 1 in the first XOR matrix, if so, the first original layout matrix does not include the second original layout matrix, if not, the first original layout matrix includes the second original layout matrix. Conversely, the second original layout matrix and the union layout matrix are bitwise XORed to form a second XOR matrix, then it is determined whether there is an element with a value of 1 in the second XOR matrix, if so, the second original layout matrix does not include the first original layout matrix, if not, the second original layout matrix includes the first original layout matrix.

If it is necessary to obtain the intersection graph of two integrated circuits in the physical design stage, firstly execute steps 601 to 606 for the two integrated circuits to form a first original layout matrix and a second original layout matrix respectively, and then bitwise AND the first original layout matrix and the second original layout matrix to form an intersection matrix, which is the intersection graph of the two integrated circuits.

If it is necessary to obtain the union graph of two integrated circuits in the physical design stage, firstly execute steps 601 to 606 for the two integrated circuits to form a first original layout matrix and a second original layout matrix respectively, and then bitwise OR the first original layout matrix and the second original layout matrix to form a union matrix, which is the union graph of the two integrated circuits.

If it is necessary to obtain a graphic of one integrated circuit minus another integrated circuit during the physical design stage, firstly perform steps 601 to 606 for the two integrated circuits to form a first original layout matrix and a second original layout matrix respectively, then bitwise OR the first original layout matrix and the second original layout matrix to form a union matrix, then bitwise XOR the second original layout matrix and the union layout matrix to form an XOR matrix, which is the geometric graphic of the first integrated circuit minus the second integrated circuit.

The above is only an example. According to the geometric figures of the inner and outer edges of each side and the geometric inner and outer perimeters obtained by the process of Figure 6 of this embodiment, after appropriate logical operations, all the geometric information required in the physical design stage can be obtained.

Another embodiment of the present invention is an integrated circuit layout design device, which is used to obtain the geometry of the integrated circuit layout, especially to obtain the edge information of the integrated circuit layout, as a reference for subsequent physical design. FIG13 shows a schematic diagram of the structure of this embodiment, and the device 1300 includes a generation module 1301, a conversion module 1302, a judgment module 1303, a setting module 1304, a designation module 1305, a shift module 1306, an operation module 1307 and a summation module 1308, and each module transmits signals through a bus 1309. The integrated circuit layout design device shown in FIG13 of the present invention can be integrated into a layout and wiring tool such as an EDA tool.

The generation module 1301 is used to generate a grid. The grid referred to here may be a process manufacturing grid, a standard cell layout grid, a wiring channel grid or a custom grid, which forms an array including a plurality of grid points.

The conversion module 1302 is used to convert the grid into a matrix, and each grid point corresponds to an element of the matrix. Each grid point 101 can be regarded as an element of a matrix. The conversion module 1302 matrixes the grid and encodes each grid point according to the rules of the matrix, such as the element a _xy of the matrix, where the subscript x represents the coordinate value of the grid point along the x-axis, and the subscript y represents the coordinate value of the grid point along the y-axis.

The judging module 1303 is used to judge whether each grid point falls within the layout range of the integrated circuit. In the EDA tool, the layout of the integrated circuit is performed based on the aforementioned grid, and the judging module 1303 judges whether each grid point falls within the layout range of the integrated circuit.

When the grid point falls within the layout range, the setting module 1304 is used to set the value of the corresponding element to true, and in this embodiment, the element value "1" represents true. When the grid point does not fall within the layout range, the setting module 1304 is used to set the value of the corresponding element to false, and in this embodiment, the element value "0" represents false. That is, the value of the elements of the entire matrix that fall within the layout range of the integrated circuit is 1, and the rest are 0.

The designation module 1305 is used to designate all elements whose values are true as the original layout matrix, where the original layout matrix carries the integrated circuit information.

The shift module 1306 is used to shift the original layout matrix one grid point to one side on the grid to form a first layout matrix. The shift module 1306 makes the original layout matrix move one grid point to the upper, lower, left and right sides of the grid respectively, forming four first layout matrices, each of which corresponds to one side. The first layout matrix is exactly the same as the original layout matrix in terms of geometry, except that the first layout matrix is a new layout matrix formed by shifting the original layout matrix one grid point to one side.

The operation module 1307 is used to perform bitwise OR operation on the original layout matrix and the first layout matrix to form a second layout matrix. The operation module 1307 generates four second layout matrices based on the four first layout matrices, each second layout matrix corresponds to one side, and the second layout matrix is the union of the original layout matrix and the first layout matrix.

The operation module 1307 then performs bitwise XOR on the second layout matrix and the original layout matrix to form a third layout matrix, which carries the geometric edge information of the side. The operation module 1307 sets the elements of the intersection of the second layout matrix and the original layout matrix to 0, and sets the elements of the second layout matrix and the original layout matrix that do not intersect to 1, forming a total of 4 third layout matrices, each of which corresponds to a side. So far, this embodiment obtains the geometric edge information of the four sides of this layout range.

The judgment module 1303 further judges whether all sides have obtained the geometric outer edge information. If not, the shift module 1306 is notified to move the original layout matrix one grid point on the grid to the side that has not obtained the geometric outer edge information, so that the operation module 1307 can obtain the geometric inner and outer edge information of the side. This continues until the geometric inner and outer edge information of the four sides of the layout range are obtained.

If all sides have obtained the geometric perimeter information, the operation module 1307 performs a bitwise OR operation on all the third layout matrices to form a fourth layout matrix, which carries the geometric perimeter information of the circuit layout.

The shift module 1306 continues to shift all the third layout matrices on the grid by one grid point in the opposite direction of the side to form four fifth layout matrices, each of which carries geometric inner edge information of one side.

The shift module 1306 then performs a bitwise OR operation on all fifth layout matrices to form a sixth layout matrix, where the sixth layout matrix carries geometric inner perimeter information of the circuit layout.

The summing module 1308 is used to sum the elements of the original layout matrix to obtain the geometric area information of the circuit layout. The area of each grid point is known, and the summing module 1308 only needs to count the number of elements in the original layout matrix (i.e., the number of elements with a value of 1) and multiply it by the area of each grid point to obtain the area of the original layout matrix.

Another embodiment of the present invention is a computer-readable storage medium, on which a computer program code for obtaining geometric information of a circuit layout is stored, and when the computer program code is run by a processor, the method of each embodiment described above is executed. In some implementation scenarios, the above-mentioned integrated unit can be implemented in the form of a software program module. If implemented in the form of a software program module and sold or used as an independent product, the integrated unit can be stored in a computer-readable memory. Based on this, when the solution of the present invention is embodied in the form of a software product (such as a computer-readable storage medium), the software product can be stored in a memory, which may include several instructions to enable a computer device (such as a personal computer, a server or a network device, etc.) to perform some or all of the steps of the method described in the embodiment of the present invention. The aforementioned memory may include, but is not limited to, various media that can store program codes, such as a USB flash drive, a flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

The present invention converts the geometric figures of the integrated circuit into a matrix, and obtains the information of the geometric figures of the inner and outer edges of each side of the integrated circuit and the geometric inner and outer perimeters, which serves as the basis for subsequent procedures in the physical design stage, and can efficiently execute chip design.

It should be noted that, for the purpose of simplicity, the present invention describes some methods and embodiments thereof as a series of actions and combinations thereof, but those skilled in the art will appreciate that the scheme of the present invention is not limited by the order of the described actions. Therefore, based on the disclosure or teaching of the present invention, those skilled in the art will appreciate that some of the steps therein may be performed in other orders or simultaneously. Further, those skilled in the art will appreciate that the embodiments described in the present invention may be regarded as optional embodiments, i.e., the actions or modules involved therein are not necessarily necessary for the implementation of one or some schemes of the present invention. In addition, depending on the different schemes, the present invention also has different emphases on the description of some embodiments. In view of this, those skilled in the art will appreciate that the parts not described in detail in a certain embodiment of the present invention may also refer to the relevant descriptions of other embodiments.

In terms of specific implementation, based on the disclosure and teachings of the present invention, those skilled in the art can understand that several embodiments disclosed in the present invention can also be implemented in other ways not disclosed herein. For example, with respect to the various units in the electronic device or device embodiments described above, this article splits them on the basis of considering the logical functions, and there may be other ways of splitting them in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features or functions in the units or components can be selectively disabled. In terms of the connection relationship between different units or components, the connection discussed in the above text in conjunction with the accompanying drawings can be a direct or indirect coupling between units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection using an interface, wherein the communication interface can support electrical, optical, acoustic, magnetic or other forms of signal transmission.

In the present invention, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units. The aforementioned components or units may be located at the same location or distributed on multiple network units. In addition, according to actual needs, some or all of the units may be selected to achieve the purpose of the scheme described in the embodiment of the present invention. In addition, in some scenarios, multiple units in the embodiment of the present invention may be integrated into one unit or each unit may exist physically separately.

In some other implementation scenarios, the above-mentioned integrated unit can also be implemented in the form of hardware, that is, a specific hardware circuit, which may include digital circuits and/or analog circuits, etc. The physical implementation of the hardware structure of the circuit may include but is not limited to physical devices, and the physical devices may include but are not limited to devices such as transistors or memristors. In view of this, the various devices described herein (such as computing devices or other processing devices) can be implemented by appropriate hardware processors, such as central processing units, GPUs, FPGAs, DSPs, and ASICs, etc. Further, the aforementioned storage unit or storage device may be any appropriate storage medium (including magnetic storage media or magneto-optical storage media, etc.), which may be, for example, a variable resistive memory (Resistive Random Access Memory, RRAM), a dynamic random access memory (Dynamic Random Access Memory, DRAM), a static random access memory (Static Random Access Memory, SRAM), an enhanced dynamic random access memory (Enhanced Dynamic Random Access Memory, EDRAM), a high bandwidth memory (High Bandwidth Memory, HBM), a hybrid memory cube (Hybrid Memory Cube, HMC), ROM and RAM, etc.

The foregoing content can be better understood in accordance with the following terms:

Item A1. An integrated circuit layout design method, comprising: generating a grid, the grid comprising a plurality of grid points; converting the grid into a matrix, each grid point corresponding to an element of the matrix; determining whether each grid point falls within the layout range of the integrated circuit; if so, setting the value of the corresponding element to true; and designating all elements with true values as an original layout matrix, the original layout matrix carrying the integrated circuit information.

Item A2. The method according to Item A1 further includes: moving the original layout matrix one grid point to one side on the grid to form a first layout matrix; bitwise ORing the original layout matrix and the first layout matrix to form a second layout matrix; and bitwise XORing the second layout matrix and the original layout matrix to form a third layout matrix, wherein the third layout matrix carries the geometric edge information of the side.

Item A3. A method according to Item A2, wherein the shifting, bitwise OR and bitwise XOR steps are performed on the other three sides, the method further comprising: bitwise ORing all third layout matrices to form a fourth layout matrix, the fourth layout matrix carrying geometric outer perimeter information of the circuit layout.

Item A4. The method according to Item A2 further includes: moving the third layout matrix on the grid by one grid point in the opposite direction of the side to form a fifth layout matrix, wherein the fifth layout matrix carries geometric inner edge information of the side.

Item A5. A method according to Item A4, wherein the moving, bitwise OR, bitwise XOR and reverse moving steps are performed on the other three sides, and the method further includes: bitwise ORing all of the fifth layout matrix to form a sixth layout matrix, wherein the sixth layout matrix carries the geometric inner perimeter information of the circuit layout.

Item A6. The method according to Item A1 further includes: summing the elements of the original layout matrix to obtain geometric area information of the circuit layout.

Item A7. The method of Item A1, wherein the grid is one of a process manufacturing grid, a standard cell placement grid, a routing channel grid, and a custom grid.

Item A8. A computer-readable storage medium having stored thereon a computer program code for obtaining geometric information of a circuit layout, wherein when the computer program code is executed by a processor, the method described in any one of Items A1-7 is executed.

Item A9. An integrated circuit layout design device, comprising: a generation module for generating a grid, the grid comprising a plurality of grid points; a conversion module for converting the grid into a matrix, each grid point corresponding to an element of the matrix; a judgment module for judging whether each grid point falls within the layout range of the integrated circuit; a setting module for setting the value of the corresponding element to true when the grid point falls within the layout range; and a designation module for designating all elements whose values are true as an original layout matrix, the original layout matrix carrying the integrated circuit information.

Item A10. The device according to Item A9 further includes: a shift module for moving the original layout matrix one grid point to one side on the grid to form a first layout matrix; and an operation module for: bitwise ORing the original layout matrix and the first layout matrix to form a second layout matrix; and bitwise XORing the second layout matrix and the original layout matrix to form a third layout matrix, wherein the third layout matrix carries the geometric edge information of the side.

Item A11. An apparatus according to Item A10, wherein the shift module moves the original layout matrix by one grid point on the other three sides respectively, and the operation module performs the bitwise OR operation and the bitwise XOR operation respectively to form three other third layout matrices, and bitwise ORs all the third layout matrices to form a fourth layout matrix, wherein the fourth layout matrix carries the geometric outer perimeter information of the circuit layout.

Item A12. An apparatus according to Item A10, wherein the shift module shifts the third layout matrix on the grid by one grid point in the opposite direction of the side to form a fifth layout matrix, wherein the fifth layout matrix carries geometric inner edge information of the side.

Item A13. An apparatus according to Item A12, wherein the shift module shifts the original layout matrix by one grid point on the other three sides respectively, and the operation module performs the bitwise OR operation and the bitwise XOR operation respectively to form three other fifth layout matrices, and bitwise ORs all the fifth layout matrices to form a sixth layout matrix, wherein the sixth layout matrix carries the geometric inner perimeter information of the circuit layout.

Item A14. The device according to Item A9 further includes: a summation module for summing the elements of the original layout matrix to obtain geometric area information of the circuit layout.

Item A15. The apparatus of Item A9, wherein the grid is one of a process manufacturing grid, a standard cell placement grid, a routing channel grid, and a custom grid.

The embodiments of the present invention are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims (13)

1. An integrated circuit layout design method, comprising:

generating a grid, the grid comprising a plurality of grid points;

Converting the grid into a matrix, wherein each grid point corresponds to an element of the matrix;

Judging whether each grid point is in the layout range of the integrated circuit;

if so, setting the value of the corresponding element as true; and

Designating all elements with true values as an original layout matrix, wherein the original layout matrix carries the integrated circuit information;

moving the original layout matrix to one side of the grid by one grid point to form a first layout matrix;

Bitwise or the original layout matrix and the first layout matrix to form a second layout matrix; and

The second layout matrix and the original layout matrix are bitwise exclusive-ored to form a third layout matrix, the third layout matrix carrying geometric outer edge information of the side.

2. The method of claim 1, wherein the moving, bitwise or and bitwise exclusive or steps are performed on three other sides, the method further comprising:

bits or all of the third layout matrix are used to form a fourth layout matrix that carries geometric perimeter information of the circuit layout.

3. The method of claim 1, further comprising:

And moving the third layout matrix by one lattice point on the lattice in the opposite direction of the side to form a fifth layout matrix, wherein the fifth layout matrix carries geometric inner edge information of the side.

4. The method of claim 3, wherein the moving, bitwise or, bitwise exclusive or, and reverse moving steps are performed on three other sides, the method further comprising:

Bits or all of the fifth layout matrix are used to form a sixth layout matrix that carries geometric inner perimeter information of the circuit layout.

5. The method of claim 1, further comprising:

The elements of the original layout matrix are summed to obtain geometric area information of the circuit layout.

6. The method of claim 1, wherein the grid is one of a process manufacturing grid, a standard cell layout grid, a routing channel grid, and a custom grid.

7. A computer readable storage medium having stored thereon computer program code for retrieving geometrical information of a circuit layout, which, when being executed by a processor, performs the method of any of claims 1-6.

8. An integrated circuit layout design apparatus, comprising:

A generation module to generate a grid, the grid comprising a plurality of grid points;

the conversion module is used for converting the grids into a matrix, and each grid point corresponds to an element of the matrix;

the judging module is used for judging whether each grid point falls in the layout range of the integrated circuit;

the setting module is used for setting the numerical value of the corresponding element to be true when the grid point falls in the layout range; and

The designating module is used for designating all elements with true values as an original layout matrix, and the original layout matrix carries the integrated circuit information;

The shifting module is used for shifting the original layout matrix to one side of the grid by one grid point so as to form a first layout matrix; and

The operation module is used for:

Bitwise or the original layout matrix and the first layout matrix to form a second layout matrix; and

The second layout matrix and the original layout matrix are bitwise exclusive-ored to form a third layout matrix, the third layout matrix carrying geometric outer edge information of the side.

9. The apparatus of claim 8, wherein the shift module shifts the original layout matrix by one lattice point on three other sides, respectively, the operation module performs the bitwise or operation and the bitwise exclusive or operation, respectively, to form three other third layout matrices, and bitwise or all third layout matrices to form a fourth layout matrix carrying geometric outer perimeter information of the circuit layout.

10. The apparatus of claim 8, wherein the shift module moves the third layout matrix one lattice point on the grid in a direction opposite the side to form a fifth layout matrix, the fifth layout matrix carrying geometric inner edge information of the side.

11. The apparatus of claim 10, wherein the shift module shifts the original layout matrix by one lattice point on three other sides, respectively, the operation module performs the bitwise or operation and the bitwise exclusive or operation, respectively, to form three other fifth layout matrices, and bitwise or all fifth layout matrices to form a sixth layout matrix, the sixth layout matrix carrying geometric inner perimeter information of the circuit layout.

12. The apparatus of claim 8, further comprising:

And the summing module is used for summing the elements of the original layout matrix to obtain the geometric area information of the circuit layout.

13. The apparatus of claim 8, wherein the grid is one of a process manufacturing grid, a standard cell layout grid, a routing channel grid, and a custom grid.