CN114675199B - Method for testing free carrier absorption loss and battery sample - Google Patents
Method for testing free carrier absorption loss and battery sampleInfo
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Abstract
本发明属于太阳电池技术领域，提供一种测试自由载流子吸收损失的方法及电池样品，该方法包括：制备特定结构的电池样品，电池样品包括前表面和后表面的局部均无掺杂的第一区域、前表面局部有第一重掺杂层而后表面局部无掺杂的第二区域及前表面局部无掺杂而后表面局部有第二重掺杂层的第三区域；测试第一区域、第二区域和第三区域在近红外波段的外量子效率；根据第一区域、第二区域和第三区域的外量子效率与AM1.5G光谱，获取第一区域、第二区域和第三区域的积分电流密度值；根据第一区域、第二区域和第三区域的积分电流密度值，获取自由载流子吸收损失。该方法测试更简单、耗时短、成本低，能快速、精准地实现自由载流子吸收损失的定量检测。
The present invention belongs to the technical field of solar cells, and provides a method and a battery sample for testing free carrier absorption loss, the method comprising: preparing a battery sample of a specific structure, the battery sample comprising a first region where both the front surface and the rear surface are partially undoped, a second region where the front surface partially has a first heavily doped layer and the rear surface partially has no doping, and a third region where the front surface partially has no doping and the rear surface partially has a second heavily doped layer; testing the external quantum efficiency of the first region, the second region, and the third region in the near-infrared band; obtaining the integrated current density values of the first region, the second region, and the third region based on the external quantum efficiency of the first region, the second region, and the third region and the AM1.5G spectrum; obtaining the free carrier absorption loss based on the integrated current density values of the first region, the second region, and the third region. The method is simpler to test, less time-consuming, and less costly, and can quickly and accurately achieve quantitative detection of free carrier absorption loss.
Description
Technical Field
The invention relates to the technical field of solar cells, in particular to a method for testing free carrier absorption loss and a cell sample.
Background
Crystalline silicon solar cells are currently common type of solar cells. Optical losses in crystalline silicon solar cells mainly include metal gate line shading losses, reflection losses, escape losses, transmission losses, recombination losses, and free carrier absorption losses. The free carrier absorption refers to photons (the band-to-band absorption is weak) approaching to the band gap energy of the semiconductor, the photons are absorbed by free electrons or holes in the semiconductor material to generate in-band transition, and the energy of the photons is finally dissipated in the form of heat energy, so that the photons do not contribute to the photoelectric current, and the photons belong to parasitic absorption. In crystalline silicon solar cells, free carrier absorption is particularly pronounced due to the abundance of free electrons or holes in the heavily doped semiconductor. Furthermore, the need for heavily doping the silicon wafer to form the emitter or back field is unavoidable in crystalline silicon solar cells. On one hand, the built-in potential difference of the p-n junction is improved through heavy doping, the strength of a built-in electric field is enhanced, the separation of carriers and the output of high open-circuit voltage are facilitated, and on the other hand, the semiconductor is required to be heavily doped into a degenerate state to ensure the collection of carriers in order to form good ohmic contact between the metal electrode and the semiconductor. The existence of heavy doping in crystalline silicon solar cells results in the optical loss of free carrier absorption in crystalline silicon solar cells at all times.
In recent years, crystalline silicon solar cells with passivation contact structures such as TOPCon and HJT are favored in the market due to the advantages of high open voltage and high conversion efficiency, and are expected to become the main stream crystalline silicon solar cells following P-type PERC solar cells. The passivation contact structure, such as an ultrathin tunneling oxide layer and a heavily doped polysilicon layer of TOPCon solar cells, and an ultrathin intrinsic amorphous silicon layer and a heavily doped amorphous silicon layer of HJT solar cells, has excellent interface passivation performance and excellent contact performance. However, the heavily doped polysilicon layer and the heavily doped amorphous silicon layer both strengthen the heavy doping in the crystalline silicon solar cell, and therefore, there is a serious free carrier absorption, resulting in a reduction of the short-circuit current of the passivation contact solar cell, which restricts the further improvement of the cell efficiency.
With the continuous optimization of the performance of crystalline silicon solar cells, such as continuous reduction of reflection loss, escape loss and recombination loss, the free carrier absorption loss becomes increasingly prominent. However, there is currently no method to obtain free carrier absorption loss directly by experimental means. The internationally reported conventional method comprises the following steps of 1) firstly obtaining a refractive index n value and an extinction coefficient k value of a doped layer through a full-spectrum ellipsometer (the wavelength coverage range is 300-1200 nm), 2) preparing a battery sample with the doped layer, testing data of reflectivity, transmissivity and spectral response, 3) establishing a corresponding optical model according to the structure of the battery sample by adopting commercial semiconductor simulation software such as Sentaurus (such as "Efficiency Roadmap for Evolutionary Upgrades of PERC Solar Cells by TOPCon:Impact of Parasitic Absorption",Christoph Messmer and the like, pages 1-2, IEEE JOURNAL OF PHOTOVOLTAICS and 2019), inputting the n value and the k value of optical constant data collected in 1) and the data of the measured reflectivity, transmissivity and spectral response in 2) into the optical model for optical fitting, and 4) after multiple operations, obtaining the data of the reflectivity, the transmissivity and the spectral response after fitting and the measured data in 2) after forming self-consistency, measuring the absorption loss of free carriers.
However, this conventional method is extremely complicated and takes a long time and the test costs are high, for example, steps 1) and 2) each require preparation of battery samples of different structures to acquire optical constants (i.e., n-value and k-value) and measured data (i.e., data of reflectance, transmittance and spectral response), respectively, which makes the test method complicated and cumbersome, and takes a long time, and step 1) requires acquisition of n-value and k-value with a special apparatus-full spectrum ellipsometer, which increases the investment of the test costs, extraction of n-value and k-value, and acquisition of a plurality of measured data of reflectance, transmittance and spectral response, which also makes the test method more complicated and takes a long time, and, furthermore, the investment of simulation software such as Sentaurus, and the simulation and fitting process of step 3) usually require operation with a large server, which further increases the cost investment of the test method and makes the test method more cumbersome and takes a long time. Based on the method, a method for testing the free carrier absorption loss is developed, which is simple, short in time consumption and low in cost, so that quantitative calculation of the free carrier absorption loss is rapidly and accurately realized, and the method has important significance for structural design (such as design of a doped structure and materials used by the doped structure), process optimization and improvement of the cell efficiency of the solar cell.
Disclosure of Invention
One of the purposes of the invention is to provide a method for testing the free carrier absorption loss, which is simple, short in time consumption and low in cost, aiming at the defects of the prior art, so as to rapidly and accurately realize quantitative calculation of the free carrier absorption loss.
It is a second object of the present invention to provide a battery sample for testing free carrier absorption loss, which addresses the deficiencies of the prior art.
Based on this, the invention discloses a method for testing free carrier absorption loss, comprising the following steps:
Step S1, preparing a battery sample with a specific structure, wherein local doping is carried out on the front surface and the rear surface of a silicon wafer to form a first heavily doped layer and a second heavily doped layer with opposite conductivity types respectively, the battery sample comprises a first area with no doping on the front surface part and the rear surface part, which correspond to each other up and down, a second area with no doping on the rear surface part, which corresponds to each other up and down, a third area with no doping on the front surface part and the rear surface part, which corresponds to each other up and down, and a second heavily doped layer, which corresponds to each other up and down;
S2, respectively testing the external quantum efficiency of the first region, the second region and the third region of the battery sample in a near infrared band by adopting a quantum efficiency tester;
Step S3, acquiring free carrier absorption loss of a battery sample:
Step S31, respectively obtaining integrated current density values of the first region, the second region and the third region according to the external quantum efficiency of the first region, the second region and the third region in the near infrared band and the AM1.5G spectrum;
Step S32, acquiring the free carrier absorption loss of the battery sample according to the integrated current density values of the first region, the second region and the third region.
Preferably, the near infrared band is 900-1200 nm;
In the step S31, the step of obtaining the integrated current density values of the first region, the second region and the third region according to the external quantum efficiency of the first region, the second region and the third region in the near infrared band and the am1.5g spectrum respectively includes:
and integrating the external quantum efficiency EQE (lambda) of the first region, the external quantum efficiency EQE (lambda) of the second region and the external quantum efficiency EQE (lambda) of the third region with the AM1.5G spectrum in a wave band of 900-1200 nm through the following formula so as to respectively calculate integrated current density values J of the first region, the second region and the third region:
In the formula, EQE (lambda) is external quantum efficiency, AM1.5G is a standard solar spectrum when the air quality is 1.5, q is unit charge, the value of the unit charge is 1.6X10 -19 C, h is Planck constant, the value of the unit charge is 6.6X10 -34 J.s, C is the light speed in vacuum, the value of the unit charge is 3.0X10 8 m/s, lambda is wavelength, and the integral range is 900-1200 nm.
Further preferably, in the step S32, the step of obtaining the free carrier absorption loss of the battery sample according to the integrated current density values of the first region, the second region and the third region is:
The difference value of the integrated current density values of the first region and the second region is the free carrier absorption loss of the first heavily doped layer on the front surface of the battery sample, and the difference value of the integrated current density values of the first region and the third region is the free carrier absorption loss of the second heavily doped layer on the rear surface of the battery sample.
Preferably, the first heavily doped layer and/or the second heavily doped layer is of a homojunction structure.
Further preferably, the homojunction structure is a single crystal doped layer with N-type or P-type conductivity formed by thermal diffusion, ion implantation or printing of doping paste;
the square resistance value of the monocrystalline doped layer is 10-500 omega/sq, and the junction depth is 0.3-3 mu m.
Preferably, the first heavily doped layer and/or the second heavily doped layer is a passivation contact structure.
Further preferably, the passivation contact structure comprises a tunneling oxide layer and a heavily doped polysilicon layer which are stacked;
the thickness of the tunneling oxide layer is 0.5-3.0 nm;
The conductivity type of the heavily doped polysilicon layer is N type or P type, the thickness is 30-600 nm, and the doping concentration is 0.1-8.0E+20cm -3.
Preferably, in the step S1, the preparation step of the battery sample includes:
s11, respectively forming a front heavily doped layer and a rear heavily doped layer with opposite conductivity types on the front surface and the rear surface of a silicon wafer;
Step S12, locally removing a front heavily doped layer on the front surface of the silicon wafer to obtain a first heavily doped layer, locally removing a rear heavily doped layer on the rear surface of the silicon wafer to obtain a second heavily doped layer, alternately arranging undoped regions on the front surface of the silicon wafer and doped regions of the first heavily doped layer, alternately arranging undoped regions on the rear surface of the silicon wafer and doped regions of the second heavily doped layer, and vertically staggered the first heavily doped layer and the second heavily doped layer, so that the second region and the third region exist on the front surface part and the rear surface part which are vertically corresponding, and the first region which is vertically partially overlapped is formed on the undoped regions on the front surface of the silicon wafer and the undoped regions on the rear surface of the silicon wafer;
step S13, respectively depositing a first antireflection film and a second antireflection film on the front surface and the rear surface of the silicon wafer;
And S14, preparing a first metal grid line on the front surface of the silicon wafer so that the end part of the first metal grid line passes through the first anti-reflection film and then is positioned on the first heavily doped layer, and preparing a second metal grid line on the rear surface of the silicon wafer so that the end part of the second metal grid line passes through the second anti-reflection film and then is positioned on the second heavily doped layer.
Further preferably, before the step S11, the method further comprises the steps of cleaning the silicon wafer, removing the damaged layer, and then texturing or polishing the silicon wafer.
Preferably, the conductivity type of the silicon wafer is N type or P type, the resistivity is 5-100 ohm cm, and the thickness is 150-200 mu m.
The invention also discloses a battery sample for testing the free carrier absorption loss, which comprises a silicon wafer, wherein a first heavily doped layer and a second heavily doped layer with opposite conductivity types are locally arranged on the front surface and the rear surface of the silicon wafer respectively, the first heavily doped layer and the second heavily doped layer are vertically staggered, and a front surface undoped region and a rear surface undoped region of the silicon wafer are vertically overlapped locally, so that the battery sample comprises a first region with no doping on the front surface locally and the rear surface locally which are vertically corresponding, a second region with no doping on the front surface locally and the rear surface locally which are vertically corresponding, and a third region with a second heavily doped layer on the front surface locally and the rear surface locally which are vertically corresponding;
The undoped region and the doped region on the front surface of the silicon wafer are provided with a first antireflection film, the undoped region and the doped region on the rear surface of the silicon wafer are provided with a second antireflection film, the front surface of the silicon wafer is provided with a first metal grid line with the end part positioned in the first heavily doped layer, and the rear surface of the silicon wafer is provided with a second metal grid line with the end part positioned in the second heavily doped layer.
Compared with the prior art, the invention at least comprises the following beneficial effects:
1. The method has the advantages of simple test process, short time consumption and low cost, and is suitable for the requirement of mass rapid test of enterprises. The method for testing the free carrier absorption loss of the invention only needs 27 hours in total, and the internationally reported conventional method (hereinafter referred to as conventional method) needs at least 72 hours, so that the time consumption of the method is obviously shortened, the test is faster, the conventional method needs more full spectrum ellipsometers and simulation software such as Sentaurus than the method of the invention, so that the method of the invention can greatly save the investment of equipment cost, the method of the invention only needs to prepare a battery sample with a specific structure in the step 1, compared with the conventional method, the preparation process of a primary battery sample is omitted, a plurality of data such as n value and k value are not required to be acquired, and the simulation and fitting processes of the simulation software such as Sentaurus and the complex operation amount of the simulation software are omitted, so that the test process of the method of the invention is simpler.
2. The method has high accuracy, precision and repeatability. Compared with the values obtained by testing by the conventional method, the method has the advantages that the difference of the free carrier absorption loss data obtained by testing is very small, the difference is within 0.03mA/cm 2, the accuracy is high, the value difference of the free carrier absorption loss data obtained by testing a plurality of battery samples with the same structure is controlled within 0.03mA/cm 2, and the battery samples prepared at different time (such as the current week and the last week) have basically the same test result, so the repeatability is high.
3. The method has wide test range, and is not only suitable for the crystalline silicon solar cell with the conventional homojunction structure, but also suitable for the crystalline silicon solar cell with the passivation contact structure.
4. The method can quantitatively calculate the current density loss caused by free carrier absorption in the crystalline silicon solar cell.
In summary, the method of the invention can rapidly and accurately test the free carrier absorption loss of the crystalline silicon solar cell, and lays an important foundation for cell structure design (such as design of doping structure and materials used by the doping structure), process optimization and cell efficiency improvement of the crystalline silicon solar cell.
Drawings
Fig. 1 is a schematic structural view of a battery sample prepared in example 1 of the present invention.
Fig. 2 is an external quantum efficiency response chart of a specific region of the battery sample prepared in example 1 of the present invention.
Fig. 3 is a schematic structural view of a battery sample prepared in example 2 of the present invention.
Fig. 4 is an external quantum efficiency response chart of a specific region of the battery sample prepared in example 2 of the present invention.
Fig. 5 is a schematic structural view of a battery sample prepared in example 3 of the present invention.
Fig. 6 is an external quantum efficiency response chart of a specific region of the battery sample prepared in example 3 of the present invention.
The reference numbers illustrate a silicon wafer 1, a first heavily doped layer 2, a second heavily doped layer 3, a 31 tunneling oxide layer, a 32 heavily doped polysilicon layer, a4 first antireflection film, a 5 second antireflection film, a 6 first metal gate line, a7 second metal gate line, a ① first region, a ② second region, and a ③ third region.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will become more apparent, a more particular description of the invention will be rendered by reference to specific embodiments thereof.
The method for testing the free carrier absorption loss comprises the following steps:
step 1, preparation of a battery sample of a specific structure (see fig. 1 and 3):
And 11, selecting a silicon wafer 1 with the conductivity type of N type or P type, wherein the resistivity of the silicon wafer 1 is 5-100 omega cm and the thickness of the silicon wafer is 150-200 mu m, cleaning the silicon wafer 1 to remove a damaged layer, and then texturing or polishing the silicon wafer 1.
And step 12, forming a front heavily doped layer and a rear heavily doped layer with opposite conductivity types on the front surface and the rear surface of the silicon wafer 1 respectively. For example, if the conductivity type of the front heavily doped layer is P-type, the conductivity type of the rear heavily doped layer is N-type, and vice versa.
Step 13, locally removing the front heavily doped layer on the front surface of the silicon wafer 1 to obtain a locally arranged first heavily doped layer 2, locally removing the rear heavily doped layer on the rear surface of the silicon wafer 1 to obtain a locally arranged second heavily doped layer 3, alternately arranging the undoped region on the front surface of the silicon wafer 1 and the doped region of the first heavily doped layer 2, alternately arranging the undoped region on the rear surface of the silicon wafer 1 and the doped region of the second heavily doped layer 3, and vertically staggered the first heavily doped layer 2 and the second heavily doped layer 3, wherein the conductivity types of the first heavily doped layer 2 and the second heavily doped layer 3 are opposite, and the undoped region on the front surface of the silicon wafer 1 and the undoped region on the rear surface of the silicon wafer 1 are locally overlapped up and down.
In this way, through steps S12 and 13, the front surface and the rear surface of the silicon wafer 1 are locally doped to form the first heavily doped layer 2 and the second heavily doped layer 3 with opposite conductivity types, respectively, so that the battery sample includes the first region ① where the front surface and the rear surface are locally undoped, the second region ② where the front surface is locally undoped, and the third region ③ where the front surface is locally undoped, and the rear surface is locally undoped, respectively, the second region ② and the third region ③ are locally present, and the first region ① where the undoped region of the front surface of the silicon wafer 1 is locally overlapped with the undoped region of the rear surface of the silicon wafer 1 is locally present.
An example of the invention is that the first heavily doped layer 2 and/or the second heavily doped layer 3 is of a homojunction structure (see figure 1), the homojunction structure is a single crystal doped layer with N type or P type conductivity formed by thermal diffusion, ion implantation or printing doping slurry, the square resistance value of the single crystal doped layer is 10-500 Ω/sq, and the junction depth is 0.3-3 μm.
Another example of the invention is that the first heavily doped layer 2 and/or the second heavily doped layer 3 are passivation contact structures, the passivation contact structures are tunneling oxide layers 31 and heavily doped polysilicon layers 32 (see fig. 3) which are arranged in a stacked manner, the thickness of the tunneling oxide layers 31 is 0.5-3.0 nm, the conductivity type of the heavily doped polysilicon layers 32 is N-type or P-type, the thickness is 30-600 nm, and the doping concentration is 0.1-8.0e+20cm -3.
Step 14, depositing a first antireflection film 4 on the undoped region on the front surface of the silicon wafer 1 and the doped region corresponding to the first heavily doped layer 2, and then depositing a second antireflection film 5 on the undoped region on the rear surface of the silicon wafer 1 and the doped region corresponding to the second heavily doped layer 3, that is, depositing the first antireflection film 4 and the second antireflection film 5 on the front surface and the rear surface of the silicon wafer 1, respectively.
The first antireflection film 4 is one or a combination of more than one of aluminum oxide, silicon dioxide, silicon nitride and silicon oxynitride, the second antireflection film 5 is one or a combination of more than one of aluminum oxide, silicon dioxide, silicon nitride and silicon oxynitride, and the thickness of the first antireflection film 4 and the second antireflection film 5 is 50-150 nm.
And 15, preparing a first metal grid line 6 on the front surface of the silicon wafer 1 so that the end part of the first metal grid line 6 passes through the first anti-reflection film 4 and then is positioned on the first heavily doped layer 2, and preparing a second metal grid line 7 on the rear surface of the silicon wafer 1 so that the end part of the second metal grid line 7 passes through the second anti-reflection film 5 and then is positioned on the second heavily doped layer 3.
The first metal grid line 6 is made of silver, silver aluminum or aluminum, the second metal grid line 7 is made of silver, silver aluminum or aluminum, the grid line materials are printed in a screen printing mode, the width of the first metal grid line 6 and the second metal grid line 7 is 30-50 mu m, the height of the first metal grid line and the second metal grid line 7 is 5-20 mu m, high-temperature rapid sintering is conducted after printing, the sintering peak temperature is 760-820 ℃, and the sintering belt speed is 4.0-10.0 m/min.
A battery sample for testing free carrier absorption loss prepared in the step 1 is seen in fig. 1 and 3, and comprises a silicon wafer 1, wherein a first heavily doped layer 2 is locally arranged on the front surface of the silicon wafer 1, so that undoped regions on the front surface of the silicon wafer 1 and doped regions corresponding to the first heavily doped layer 2 are alternately arranged, a second heavily doped layer 3 is locally arranged on the rear surface of the silicon wafer 1, so that undoped regions on the rear surface of the silicon wafer 1 and doped regions corresponding to the second heavily doped layer 3 are alternately arranged, the first heavily doped layer 2 and the second heavily doped layer 3 are vertically staggered, the conductivity types of the first heavily doped layer 2 and the second heavily doped layer 3 are opposite, the undoped regions on the front surface and the undoped regions on the rear surface are vertically overlapped, the battery sample comprises a first region ① with no doping on the upper and lower surfaces, a second region ② with no doping on the first heavily doped layer 2 and a rear surface, a second region with no doping on the upper and lower surfaces, a second metal line is arranged on the first heavily doped layer 2 and the rear surface, the first heavily doped layer 2 and the second heavily doped layer 2 and a second metal line is arranged on the front surface of the first heavily doped layer 2 and the second heavily doped layer 3 and the second heavily doped layer 2 and the second metal line is arranged at the end portion of the first heavily doped layer 1 and the second metal film is arranged at the end portion of the first metal film 5 and the second metal film is arranged at the end portion of the first heavily doped layer 1 and the second metal film 5 and the second metal film is arranged at the end portion of the first metal film. Step 1a battery sample having the above-described specific structures of the first region ①, the second region ②, and the third region ③ was prepared to achieve a subsequent test of free carrier absorption loss of the battery sample.
Step 2, the external quantum efficiency EQE (λ) of the first region ①, the second region ②, and the third region ③ of the battery sample in the near infrared band were tested, respectively.
In actual operation, the battery sample is placed on a platform of the quantum efficiency tester, and external quantum efficiency EQE (λ) response maps (as shown in fig. 2 and 4) of the first region ①, the second region ② and the third region ③ are respectively tested, where the tested band range is 900-1200 nm.
Step 3, obtaining free carrier absorption loss of a battery sample:
Step 31, according to the external quantum efficiency and the am1.5g spectrum of the first region ①, the second region ② and the third region ③ in the near infrared band (i.e. 900-1200 nm), the integrated current density values of the first region ①, the second region ② and the third region ③ are obtained respectively:
The external quantum efficiencies EQE (λ) and am1.5g spectra of the first region ①, the second region ②, and the third region ③ are integrated in the 900-1200 nm band by the following formula, respectively, to calculate integrated current density values J of the first region ①, the second region ②, and the third region ③, respectively:
In the formula, EQE (lambda) is external quantum efficiency, AM1.5G is a standard solar spectrum when the air quality is 1.5, q is unit charge, the value of the unit charge is 1.6X10 -19 C, h is Planck constant, the value of the unit charge is 6.6X10 -34 J.s, C is the light speed in vacuum, the value of the unit charge is 3.0X10 8 m/s, lambda is wavelength, and the integral range is 900-1200 nm.
Step 32, obtaining a free carrier absorption loss of the battery sample according to the integrated current density values of the first region ①, the second region ② and the third region ③:
The difference between the integrated current density values of the first region ① and the second region ② is the free carrier absorption loss of the first heavily doped layer 2 on the front surface of the battery sample, and the difference between the integrated current density values of the first region ① and the third region ③ is the free carrier absorption loss of the second heavily doped layer 3 on the rear surface of the battery sample.
The method for testing the free carrier absorption loss has the following advantages:
1. the method has the advantages of simple testing process, short time consumption and low cost, and is suitable for the requirement of mass rapid testing of enterprises.
In the method for testing the free carrier absorption loss, the preparation of the battery sample in the step 1 needs 24 hours, the testing time in the step 2 needs 2 hours, and the data processing analysis for obtaining the free carrier absorption loss of the battery sample in the step 3 needs 1 hour. Thus, the method of the present invention for testing free carrier absorption loss requires 24h+2h+1h=27 h in total.
However, in the conventional method, step 1) preparation of a battery sample specially extracting n value and k value requires 24 hours, data analysis and extraction of n value and k value require 12 hours, extraction of n value and k value requires input of a full spectrum ellipsometer, step 2) preparation of a battery sample with doped layers requires 24 hours, collection of data of reflectivity and transmissivity requires 2 hours, collection of data of spectral response requires 2 hours, wherein step 2) collection of reflectivity, transmissivity and spectral response can share the same equipment with the step 2 test of external quantum efficiency, step 3) input of simulation software such as Sentaurus, modeling requires at least 6 hours (after establishment, repeated use after establishment), simulation and fitting processes require 1-2 hours if a large server is adopted for operation, and if a personal computer is adopted for operation, because of limited calculation force, the simulation and fitting processes are conservatively predicted to be 2 hours for at least 2-3 days.
(A) Thus, the conventional process takes at least 24h+12h+24h+4h+6h+2h=72 h. Compared with the conventional method, the method provided by the invention has the advantages that the time consumption is obviously shortened, and the test is faster. (b) Moreover, compared with the method of the invention, the conventional method requires more investment of a full-spectrum ellipsometer and simulation software such as Sentaurus, so that the method of the invention can also greatly save the investment of equipment cost. (c) In addition, the method only needs to prepare the battery sample with a specific structure in the step 1, compared with the conventional method, the preparation process of the primary battery sample is omitted, the method only needs to test the external quantum efficiency of the first region ①, the second region ② and the third region ③ of the battery sample in the near infrared band in the step 2, a plurality of data such as n value and k value are not required to be acquired, the simulation and fitting process of simulation software such as Sentaurus and the complex operation amount are omitted, and therefore, the test process of the method is simpler.
2. The method has high accuracy, precision and repeatability.
The method comprises the steps of (a) measuring the free carrier absorption loss of a battery sample by the method to be accurate to two positions after decimal point, namely to be accurate to 0.01mA/cm 2, and has high accuracy, (b) comparing with the values measured by the conventional method, the method has the advantages that the free carrier absorption loss data of the battery sample obtained by the method are very small in difference, the difference is within 0.03mA/cm 2, and the accuracy is high, (c) the inventor prepares 6 battery samples with the same structure each time, the value difference of the free carrier absorption loss data measured by each battery sample is controlled within 0.03mA/cm 2, and the battery samples prepared at different time (such as the current week and the last week) have basically the same measuring result, so that the repeatability is high.
3. The method has wide test range, and is not only suitable for the crystalline silicon solar cell with the conventional homojunction structure, but also suitable for the crystalline silicon solar cell with the passivation contact structure.
4. The method can quantitatively calculate the current density loss caused by free carrier absorption in the crystalline silicon solar cell.
In summary, the method of the invention can rapidly and accurately test the free carrier absorption loss of the crystalline silicon solar cell, and lays an important foundation for cell structure design, process optimization and cell efficiency improvement of the crystalline silicon solar cell.
The following are given as 3 examples of a method for testing free carrier absorption loss according to the present invention, and examples 1 to 3 below refer to a method for testing free carrier absorption loss according to the present invention and a battery sample thereof unless otherwise specified.
Example 1
A method of testing free carrier absorption loss of the present embodiment includes the steps of:
step 1, preparation of a battery sample of a specific structure (see fig. 1):
and 11, selecting a silicon wafer 1 with the conductivity type of N type, the resistivity of 7Ω & cm and the thickness of 160 mu m, performing damage layer removal treatment on the silicon wafer 1, texturing, and then performing single-sided polishing on the rear surface of the silicon wafer 1 to obtain the silicon wafer 1 with the textured front surface and the polished rear surface.
And step 12, forming a front heavily doped layer and a rear heavily doped layer with opposite conductivity types on the front surface and the rear surface of the silicon wafer 1 respectively. In actual operation, the front surface of the silicon wafer 1 is subjected to boron ion implantation by means of ion implantation, while the rear surface of the silicon wafer 1 is subjected to phosphorus ion implantation, followed by annealing treatment to activate doped boron ions or phosphorus ions, after annealing, a boron doped emitter, i.e., a front heavily doped layer, is formed on the front surface of the silicon wafer 1, and a phosphorus doped rear surface field, i.e., a rear heavily doped layer, is formed on the rear surface of the silicon wafer 1.
Wherein the sheet resistance of the front heavily doped layer (corresponding to the first heavily doped layer 2) is 100-150 Ω/sq, the junction depth is 0.7-0.9 μm, the peak concentration is 1.0-2.0E+19cm -3, the sheet resistance of the rear heavily doped layer (corresponding to the second heavily doped layer 3) is 80-90 Ω/sq, the junction depth is 0.4-0.6 μm, and the peak concentration is 8.0-10.0E+19cm -3.
Step 13, depositing masks on the front surface and the rear surface of the silicon wafer 1, locally removing the front heavily doped layer on the front surface of the silicon wafer 1 to obtain a locally arranged first heavily doped layer 2, locally removing the rear heavily doped layer on the rear surface of the silicon wafer 1 to obtain a locally arranged second heavily doped layer 3, wherein the surface morphology of the removed region is consistent with that of the removed region (namely, the front surface of the silicon wafer 1 is textured, the rear surface is polished), after the removal, the undoped region on the front surface of the silicon wafer 1 and the doped region corresponding to the first heavily doped layer 2 are alternately arranged, the undoped region on the rear surface of the silicon wafer 1 and the doped region corresponding to the second heavily doped layer 3 are alternately arranged, the first heavily doped layer 2 and the second heavily doped layer 3 are alternately arranged up and down, the undoped region on the front surface and the undoped region on the rear surface are locally overlapped up and down, and the prepared battery sample has three different regions, namely, a first region ① where the upper and lower corresponding front surface local undoped regions are locally, a second undoped region ② where the upper and lower local undoped regions ③ of the first heavily doped layer 2 and the lower local undoped regions are locally arranged.
And 14, respectively depositing a first antireflection film 4 and a second antireflection film 5 on the front surface and the rear surface of the silicon wafer 1. In actual operation, an ALD method is adopted to deposit an alumina film with a thickness of 0.5-5.0 nm on an undoped region on the front surface of the silicon wafer 1 and a doped region corresponding to the first heavily doped layer 2, then a PECVD method is adopted to deposit a SiNx antireflection film with a thickness of 60-85 nm so as to form a first antireflection film 4 formed by stacking the alumina film and the SiNx antireflection film, and then a PECVD method is adopted to deposit a SiNx antireflection film with a thickness of 60-85 nm on the undoped region on the rear surface of the silicon wafer 1 and the doped region corresponding to the second heavily doped layer 3 so as to form a second antireflection film 5.
And 15, printing grid line materials on the front surface and the rear surface of the silicon wafer 1 through screen printing, wherein the grid line material on the front surface is positioned on the first heavily doped layer 2, the grid line material on the rear surface is positioned on the second heavily doped layer 3, and then performing high-temperature rapid sintering to obtain the first metal grid line 6 and the second metal grid line 7.
The preparation of the battery sample for testing the free carrier absorption loss is completed, and the structure of the battery sample is shown in the figure 1, wherein the battery sample comprises a silicon wafer 1, a first heavily doped layer 2 and a second heavily doped layer 3 which are opposite in conductivity type are locally arranged on the front surface and the rear surface of the silicon wafer 1 respectively, the first heavily doped layer 2 and the second heavily doped layer 3 are vertically staggered, the front surface undoped region and the rear surface undoped region of the silicon wafer 1 are vertically overlapped locally, the battery sample comprises a first region ① which is vertically corresponding to the front surface undoped region and the rear surface undoped region, a second region ② which is vertically corresponding to the front surface undoped region and is provided with the first heavily doped layer 2 and the rear surface undoped region, and a third region ③ which is vertically corresponding to the front surface undoped region and the rear surface undoped region of the second heavily doped layer 3, a first antireflection film 4 is arranged on the undoped region and the doped region of the front surface of the silicon wafer 1, a second antireflection film 5 is arranged on the undoped region and the doped region of the rear surface of the silicon wafer 1, a first metal gate line 6 of the front surface of the silicon wafer 1 is arranged on the front surface of the first heavily doped layer 2, and a second metal gate line 7 is arranged on the rear surface of the silicon wafer 3.
Step 2, placing the battery sample on a platform of a quantum efficiency tester, and testing external quantum efficiency EQE (λ) response maps (see fig. 2) of the first region ①, the second region ② and the third region ③ respectively, wherein the tested wave band ranges from 900 nm to 1200nm.
Step 3, obtaining free carrier absorption loss of a battery sample:
Step 31, integrating the external quantum efficiencies EQE (λ) and am1.5g spectra of the first region ①, the second region ② and the third region ③ in the 900-1200 nm band by the following formula to calculate the integrated current density values J of the first region ①, the second region ② and the third region ③ respectively:
In the formula, EQE (lambda) is external quantum efficiency, AM1.5G is a standard solar spectrum when the air quality is 1.5, q is unit charge, the value of the unit charge is 1.6X10 -19 C, h is Planck constant, the value of the unit charge is 6.6X10 -34 J.s, C is the light speed in vacuum, the value of the unit charge is 3.0X10 8 m/s, lambda is wavelength, and the integral range is 900-1200 nm.
Step 32, subtracting the integrated current density value of the first region ① from the integrated current density value of the second region ② to obtain the free carrier absorption loss of the first heavily doped layer 2 on the front surface of the battery sample, and subtracting the integrated current density value of the third region ③ from the integrated current density value of the first region ① to obtain the free carrier absorption loss of the second heavily doped layer 3 on the rear surface of the battery sample.
The integrated current density values and differences of the first region ①, the second region ②, and the third region ③ of the battery sample measured by the method of the present example are shown in table 1 below:
TABLE 1
Referring to Table 1, in this example, the free carrier absorption loss of the first heavily doped layer 2 on the front surface of the battery sample was measured to be 0.15mA/cm 2, and the free carrier absorption loss of the second heavily doped layer 3 on the rear surface of the battery sample was measured to be 0.26mA/cm 2. And the free carrier absorption loss of the heavy doped layer on the front surface of the battery sample is 0.13mA/cm 2 by adopting a conventional method, and the free carrier absorption loss of the heavy doped layer on the rear surface of the battery sample is 0.27mA/cm 2. It can be seen that the difference between the method of this example and the conventional method is within 0.03mA/cm 2.
Example 2
A method for testing free carrier absorption loss of this embodiment, the specific steps of which refer to embodiment 1, differs from embodiment 1 as follows:
in step 11, the resistivity of the selected silicon wafer 1 is 5Ω·cm.
In step 12, referring to fig. 3, the preparation process of the front heavily doped layer on the front surface of the silicon wafer 1 is the same as that of embodiment 1, and the back surface of the silicon wafer 1 is sequentially deposited with an ultra-thin tunnel oxide layer 31 and an in-situ phosphorus doped polysilicon layer (i.e. heavily doped polysilicon layer 32), so that after annealing, a passivation contact structure composed of the tunnel oxide layer 31 and the phosphorus doped polysilicon layer is formed on the back surface of the silicon wafer 1 as a back heavily doped layer.
In the embodiment, the sheet resistance of the front heavily doped layer (corresponding to the first heavily doped layer 2) is 130-170 Ω/sq, the junction depth is 0.8-1.0 μm, the peak concentration is 0.7-1.0E+19cm -3, the tunneling oxide layer 31 is made of silicon dioxide in the rear heavily doped layer (corresponding to the second heavily doped layer 3), the thickness is 1.0-2.0 nm, the thickness of the phosphorus doped polysilicon layer is 100-150 nm, and the doping concentration is 1.0-3.0E+20cm -3.
A structure of a battery sample for testing free carrier absorption loss of this embodiment is shown in fig. 3, and the structure of the battery sample is referred to as a battery sample of embodiment 1, which is different from the battery sample of embodiment 1 in that the second heavily doped layer 3 is a tunneling oxide layer 31 and a phosphorus doped polysilicon layer which are locally disposed and laminated.
In step 2, the external quantum efficiency EQE (λ) response maps (see fig. 4) of the first region ①, the second region ②, and the third region ③ are respectively tested, and the tested band ranges from 900 nm to 1200nm.
The integrated current density values and differences of the first region ①, the second region ②, and the third region ③ of the battery sample measured by the method of the present example are shown in table 2 below:
Referring to Table 2, in this example, the free carrier absorption loss of the first heavily doped layer 2 on the front surface of the battery sample was measured to be 0.12mA/cm 2, and the free carrier absorption loss of the second heavily doped layer 3 on the rear surface of the battery sample was measured to be 0.32mA/cm 2. And the free carrier absorption loss of the heavy doped layer on the front surface of the battery sample is 0.12mA/cm 2 by adopting a conventional method, and the free carrier absorption loss of the heavy doped layer on the rear surface of the battery sample is 0.35mA/cm 2. It can be seen that the difference between the method of this example and the conventional method is within 0.03mA/cm 2.
Example 3
A method for testing free carrier absorption loss of this embodiment, the specific steps of which refer to embodiment 1, differs from embodiment 1 as follows:
In the step 11, the resistivity of the selected silicon wafer 1 is 5Ω·cm, and the conductivity type is P-type.
In step 12, referring to fig. 5, the front surface of the silicon wafer 1 is subjected to phosphorus ion implantation, so that after annealing, a phosphorus doped emitter, i.e., a front heavily doped layer, is formed on the front surface of the silicon wafer 1, and the rear surface of the silicon wafer 1 is not doped, so that the rear heavily doped layer of example 1 is omitted. Wherein, the sheet resistance of the front heavily doped layer (corresponding to the first heavily doped layer 2) is 90-120 Ω/sq, the junction depth is 0.4-0.6 μm, and the peak concentration is 6.0-8.0E+19cm -3.
In step 13, the locally arranged second heavily doped layer 3 and the preparation process thereof are omitted, so that the battery sample prepared in this embodiment only has the first region ① and the second region ②.
In step 14, a SiNx antireflection film with a thickness of 60-85 nm is deposited on an undoped region on the front surface of the silicon wafer 1 and a doped region corresponding to the first heavily doped layer 2 by adopting a PECVD method to form a first antireflection film 4, an alumina film with a thickness of 5-20 nm is deposited on the rear surface of the silicon wafer 1 by adopting an ALD method, and a SiNx antireflection film with a thickness of 80-100 nm is deposited by adopting a PECVD method to form a second antireflection film 5 formed by stacking the alumina film and the SiNx antireflection film.
In step 15, the gate wire material of the first metal gate wire 6 is silver, the end portion of the second metal gate wire 7 passes through the second anti-reflective film 5 and then is located on the silicon wafer 1, and the gate wire material of the second metal gate wire 7 is aluminum.
A structure of a battery sample for testing free carrier absorption loss of the present embodiment is shown in fig. 5, and the structure thereof is referred to the battery sample of embodiment 1, which is different from the battery sample of embodiment 1 in that the second heavily doped layer 3 is omitted, the second antireflection film 5 is directly provided on the rear surface of the silicon wafer 1, and the battery sample of the present embodiment contains only the first region ① and the second region ②.
In step 2, referring to fig. 6, the external quantum efficiency EQE (λ) response maps of the first region ① and the second region ② of the battery sample are tested respectively (the tested band range is 900-1200 nm).
In step 31, integrated current density values for the first region ① and the second region ② are obtained.
In step 32, the integrated current density value of the first region ① is subtracted from the integrated current density value of the second region ② to obtain the free carrier absorption loss of the first heavily doped layer 2 on the front surface of the cell sample.
The integrated current density values and differences of the first region ① and the second region ② of the battery sample measured by the method of this example are shown in table 3 below:
TABLE 3 Table 3
Referring to Table 3, in this example, the free carrier absorption loss of the first heavily doped layer 2 on the front surface of the battery sample was measured to be 0.13mA/cm 2. And the free carrier absorption loss of the heavily doped layer on the front surface of the cell sample was measured to be 0.12mA/cm 2 by a conventional method. It can be seen that the difference between the method of this example and the conventional method is within 0.03mA/cm 2.
In summary, the method can rapidly and accurately test the free carrier absorption loss of the crystalline silicon solar cell, and lays an important foundation for cell structure design, process optimization and cell efficiency improvement of the crystalline silicon solar cell.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.
While the foregoing has been provided to illustrate the principles and embodiments of the present invention, specific examples have been provided herein to assist in understanding the principles and embodiments of the present invention, and are intended to be in no way limiting, for those of ordinary skill in the art will, in light of the above teachings, appreciate that the principles and embodiments of the present invention may be varied in any way.
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