CN114726450A - Dispersion tolerant clock recovery method and system - Google Patents

Abstract

The invention discloses a dispersion-tolerant clock recovery method and system. The invention proposes an improved squared timing error detection based on a signal-based cyclic autocorrelation function (CAF), generalizes its classical correspondence function and exhibits greater dispersion Tolerance, which provides a time-domain solution for dispersion-tolerant timing error detection, the equivalence between time-domain and frequency-domain time error detection is re-established in the framework of spectral correlation. The present invention analyzes the common squared timing error detection from the perspective of cyclostationary theory, thereby naturally solving the problem of dispersion fault-tolerant timing error detection. Through this solution, a generalized squared timing error detection is obtained, which can tolerate large dispersion without prior dispersion equalization, and can be widely used in the field of signal processing technology.

Description

Dispersion tolerant clock recovery method and system

technical field

The invention relates to the technical field of signal processing, in particular to a dispersion-tolerant clock recovery method and system.

Background technique

Coherent optical receivers equipped with analog-to-digital converters (ADCs) and digital signal processing (DSPs) have been the subject of intensive research. Coherent detection of optical signals provides excellent sensitivity and supports the use of complex modulation formats such as polarization division multiplexing (PDM) quadrature phase shift keying (QPSK) and hexadecimal quadrature amplitude modulation (16QAM). These modulation formats allow for exponential increases in optical communication capacity. Meanwhile, in coherent detection, linear transmission impairments such as chromatic dispersion (CD) and polarization mode dispersion (PMD) of the fiber can be equalized by digital signal processing. One of the core tasks of digital signal processing is to synchronize receivers and transmitters, since in practice they use separate clock signals. The independent clock signals generated by the crystal oscillator are not related to each other, and a little frequency and phase jitter will cause the clocks of the transceivers to be out of sync in high-speed coherent optical communication. A coherent receiver, on the other hand, must correctly resample the input data so that a symbol-spaced or fractionally-spaced equalizer can be implemented correctly. The coherent receiver relies on the local clock to collect the incoming optical signal. A common situation in digital signal processing is to sample data using a nominal clock, but at a sampling rate that is close to an integer multiple of the baud rate. Sampling errors are corrected by timing error detection (TED) and by eg feedback loops and digital interpolators. This process is then equivalent to timing phase recovery (TPR) of the sampling clock at the receiver. Some timing phase recovery implementations also support extracting the clock directly as a clock reference for other blocks of the receiver. Therefore, accurate and robust timing error detection is at the heart of clock recovery and has long been recognized as a key issue in digital signal processing. However, conventional timing error detection is sensitive to other optical channel distortions, such as chromatic dispersion and polarization mode dispersion. To reduce the impact, it is common practice to perform blind equalization of dispersion and polarization mode dispersion before the timing phase recovery module. Nonetheless, residual dispersion may still exist and cause jitter in timing recovery.

SUMMARY OF THE INVENTION

In view of this, embodiments of the present invention provide a dispersion-tolerant clock recovery method and system, which can tolerate larger dispersion without prior dispersion equalization.

In a first aspect, an embodiment of the present invention provides a dispersion-tolerant clock recovery method, including:

Over-sampling the input dual-polarization optical signal to obtain sampled data;

Perform signal autocorrelation processing according to the sampled data to determine delay data points;

According to the delayed data points, the sampling data is shifted to obtain a first sequence and a second sequence;

The first autocorrelation sequence is determined by the first sequence, the second autocorrelation sequence is determined by the second sequence, combined with the length of the delayed data sequence, the third sequence is determined according to the first autocorrelation sequence, and the second autocorrelation sequence is determined according to the second sequence length. The autocorrelation sequence determines the fourth sequence; the length of the delayed data sequence is confirmed according to the delayed data points, the frequency resolution of the length of the delayed data sequence is divided according to the target number of shares, and the frequency resolution of the length of the delayed data sequence is The number of shares is increased from 1 to the target number of shares;

determining a fifth sequence according to the third sequence and the fourth sequence;

Determine the distance points from the target sampling point in the time domain according to the fifth sequence;

Clock recovery is performed according to the distance points.

Optionally, the method further includes:

Clock recovery quality assessment is performed based on clock component strength and clock jitter variance.

Optionally, performing oversampling on the input dual-polarization optical signal to obtain sampled data, including:

Oversampling the first polarization state signal according to the resample function to obtain first sampling data;

and, performing oversampling on the second polarization state signal according to the resample function to obtain second sampling data.

Optionally, the performing signal autocorrelation processing according to the sampled data to determine the delayed data point includes:

Determine signal autocorrelation data according to the sampled data;

Introduce delayed data time, and perform cyclic processing on the signal autocorrelation data;

Delay data points are determined from the loop-processed signal autocorrelation data.

Optionally, the determining the fifth sequence according to the third sequence and the fourth sequence includes:

summing and adding elements of the third sequence and the fourth sequence to obtain a fifth sequence;

Wherein, the number of the fifth sequence is the target share number range.

Optionally, the determining the number of distance points from the target sampling point in the time domain according to the fifth sequence includes:

When the value of the fifth sequence is zero, the number of distance points from the target sampling point in the time domain is determined according to the share of the frequency resolution of the length of the delayed data sequence;

Wherein, the number of distance points is the ratio of the frequency resolution share of the length of the delay data sequence to the target share number.

Optionally, the method further includes:

The simulation verification is carried out according to the simulation system of numerical simulation of optical communication system.

In a second aspect, an embodiment of the present invention provides a dispersion-tolerant clock recovery system, including:

The first module is used for over-sampling the input dual-polarization optical signal to obtain sampling data;

a second module, configured to perform signal autocorrelation processing according to the sampled data to determine delayed data points;

a third module, configured to perform shift processing on the sampled data according to the delayed data points to obtain a first sequence and a second sequence;

a fourth module, configured to determine a first autocorrelation sequence by using the first sequence, determine a second autocorrelation sequence by using the second sequence, and determine a third sequence based on the first autocorrelation sequence in combination with the length of the delayed data sequence , determine the fourth sequence according to the second autocorrelation sequence; the length of the delayed data sequence is confirmed according to the delayed data point, the frequency resolution of the length of the delayed data sequence is divided according to the target number of shares, the delayed data sequence The share of the frequency resolution of the sequence length is incremented from 1 to the target share number;

a fifth module, configured to determine a fifth sequence according to the third sequence and the fourth sequence;

The sixth module is used to determine the distance points from the target sampling point in the time domain according to the fifth sequence;

The seventh module is configured to perform clock recovery according to the distance points.

In a third aspect, an embodiment of the present invention provides an electronic device, including a processor and a memory;

the memory is used to store programs;

The processor executes the program to implement the method according to the first aspect of the embodiment of the present invention.

In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, where the storage medium stores a program, and the program is executed by a processor to implement the aforementioned method.

The embodiment of the present invention also discloses a computer program product or computer program, where the computer program product or computer program includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. The computer instructions can be read from the computer-readable storage medium by a processor of the computer device, and the processor executes the computer instructions to cause the computer device to perform the foregoing method.

In the embodiment of the present invention, the input dual-polarization optical signal is first oversampled to obtain sampled data; then, signal autocorrelation processing is performed according to the sampled data to determine delayed data points; then, according to the delayed data points, the sampled data is Shift processing is performed to obtain a first sequence and a second sequence; then the first autocorrelation sequence is determined by the first sequence, the second autocorrelation sequence is determined by the second sequence, combined with the length of the delayed data sequence, according to the first autocorrelation sequence An autocorrelation sequence determines the third sequence, and the second autocorrelation sequence determines the fourth sequence; the length of the delayed data sequence is confirmed according to the delayed data points, and the frequency resolution of the length of the delayed data sequence is determined according to the target share The frequency resolution share of the length of the delayed data sequence is increased from 1 to the target share number; then a fifth sequence is determined according to the third sequence and the fourth sequence; then a fifth sequence is determined according to the fifth sequence The number of distance points from the target sampling point in the time domain; finally, clock recovery is performed according to the number of distance points. The present invention analyzes the common squared timing error detection from the angle of cyclostationarity theory based on signal autocorrelation, can tolerate larger dispersion, and does not need to perform dispersion equalization in advance.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort.

1 is a schematic flowchart of a dispersion-tolerant clock recovery method provided by an embodiment of the present invention;

FIG. 2 is a schematic diagram of the principle of a dispersion-tolerant clock recovery method provided by an embodiment of the present invention;

3 is an autocorrelation spectrogram of a phase recovery compensation signal sending a 32G baud rate provided by an embodiment of the present invention;

FIG. 4 is a schematic diagram of a curve comparison between an embodiment of the present invention and a traditional algorithm in timing jitter variance;

FIG. 5 is a schematic diagram showing the comparison of the curves of the clock component strength between the embodiment of the present invention and the traditional algorithm.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

In a first aspect, referring to FIG. 1 , an embodiment of the present invention provides a dispersion-tolerant clock recovery method, including:

Over-sampling the input dual-polarization optical signal to obtain sampled data;

Perform signal autocorrelation processing according to the sampled data to determine delay data points;

According to the delayed data points, the sampling data is shifted to obtain a first sequence and a second sequence;

The first autocorrelation sequence is determined by the first sequence, the second autocorrelation sequence is determined by the second sequence, combined with the length of the delayed data sequence, the third sequence is determined according to the first autocorrelation sequence, and the second autocorrelation sequence is determined according to the second sequence length. The autocorrelation sequence determines the fourth sequence; the length of the delayed data sequence is confirmed according to the delayed data points, the frequency resolution of the length of the delayed data sequence is divided according to the target number of shares, and the frequency resolution of the length of the delayed data sequence is The number of shares is increased from 1 to the target number of shares;

determining a fifth sequence according to the third sequence and the fourth sequence;

Determine the distance points from the target sampling point in the time domain according to the fifth sequence;

Clock recovery is performed according to the distance points.

Optionally, the method further includes:

Clock recovery quality assessment is performed based on clock component strength and clock jitter variance.

Optionally, performing oversampling on the input dual-polarization optical signal to obtain sampled data, including:

Oversampling the first polarization state signal according to the resample function to obtain first sampling data;

and, performing oversampling on the second polarization state signal according to the resample function to obtain second sampling data.

Optionally, the performing signal autocorrelation processing according to the sampled data to determine the delayed data point includes:

Determine signal autocorrelation data according to the sampled data;

Introduce delayed data time, and perform cyclic processing on the signal autocorrelation data;

Delay data points are determined from the loop-processed signal autocorrelation data.

Optionally, the determining the fifth sequence according to the third sequence and the fourth sequence includes:

summing and adding elements of the third sequence and the fourth sequence to obtain a fifth sequence;

Wherein, the number of the fifth sequence is the target share number range.

Optionally, the determining the number of distance points from the target sampling point in the time domain according to the fifth sequence includes:

When the value of the fifth sequence is zero, the number of distance points from the target sampling point in the time domain is determined according to the share of the frequency resolution of the length of the delayed data sequence;

Wherein, the number of distance points is the ratio of the frequency resolution share of the length of the delay data sequence to the target share number.

Optionally, the method further includes:

The simulation verification is carried out according to the simulation system of numerical simulation of optical communication system.

In a second aspect, an embodiment of the present invention provides a dispersion-tolerant clock recovery system, including:

The first module is used for over-sampling the input dual-polarization optical signal to obtain sampling data;

a second module, configured to perform signal autocorrelation processing according to the sampled data to determine delayed data points;

a third module, configured to perform shift processing on the sampled data according to the delayed data points to obtain a first sequence and a second sequence;

a fourth module, configured to determine a first autocorrelation sequence by using the first sequence, determine a second autocorrelation sequence by using the second sequence, and determine a third sequence based on the first autocorrelation sequence in combination with the length of the delayed data sequence , determine the fourth sequence according to the second autocorrelation sequence; the length of the delayed data sequence is confirmed according to the delayed data point, the frequency resolution of the length of the delayed data sequence is divided according to the target number of shares, the delayed data sequence The share of the frequency resolution of the sequence length is incremented from 1 to the target share number;

a fifth module, configured to determine a fifth sequence according to the third sequence and the fourth sequence;

The sixth module is used to determine the distance points from the target sampling point in the time domain according to the fifth sequence;

The seventh module is configured to perform clock recovery according to the distance points.

The contents of the method embodiments of the present invention are all applicable to the system embodiments, and the specific functions implemented by the system embodiments are the same as the above-mentioned method embodiments, and the beneficial effects achieved are also the same as those achieved by the above-mentioned methods.

Another aspect of the embodiments of the present invention further provides an electronic device, including a processor and a memory;

the memory is used to store programs;

The processor executes the program to implement the method as described above.

The contents of the method embodiments of the present invention are all applicable to the electronic device embodiments, the specific functions implemented by the electronic device embodiments are the same as the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above methods.

Another aspect of the embodiments of the present invention further provides a computer-readable storage medium, where the storage medium stores a program, and the program is executed by a processor to implement the aforementioned method.

The contents of the method embodiments of the present invention are all applicable to the computer-readable storage medium embodiments, and the specific functions implemented by the computer-readable storage medium embodiments are the same as the above-mentioned method embodiments, and the beneficial effects achieved are the same as those achieved by the above-mentioned methods. The effect is also the same.

The embodiment of the present invention also discloses a computer program product or computer program, where the computer program product or computer program includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. The computer instructions can be read from the computer-readable storage medium by a processor of the computer device, and the processor executes the computer instructions to cause the computer device to perform the foregoing method.

The present invention will be further described in detail below with reference to some specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

First of all, it should be noted that the timing error detection principle:

The types of modulated signals commonly used in coherent optical communication systems (such as QPSK and 16QAM) can be modeled as cyclostationary random processes because of the periodicity in the mean and autocorrelation function (ACF) of these modulated signals, as in Equation (1):

m _x (t+T ₀ )=m _x (t)

R _x (t+τ/2+T ₀ ,τ)=R _x (t+τ/2,τ)

Where, R _x (t,τ)=E{x(t)x ^* (t-τ)}, m _x (t) represents the signal sequence, T ₀ represents the period, τ is the delay time, and E{.} represents the mathematical Desirably, the same as the symbol interval of the modulated signal.

The Fourier coefficient of the autocorrelation function is shown in formula (2):

where the harmonic frequency α=k/T ₀ is non-zero and the harmonic frequency is cyclic for the time-varying signal m _x (t), hence the term cyclic autocorrelation function (CAF). The zeroth coefficient with α=0 is regarded as the time-averaged autocorrelation function. It can be shown that the non-zero cyclic autocorrelation function means the correlation between the two frequency shifted signals of the sequence m _x (t), the relative frequency shift amount α=k/T ₀ .

Furthermore, the correlation can be characterized in the frequency domain by using the Fourier transform of the cyclic autocorrelation function, as in equations (3) and (4):

称为谱相关函数(SCF)，它是正常功率谱密度(PSD)的推广。功率谱密度也仅在谐波频率α＝k/T₀时为非零，并且在α＝0时降低到功率谱密度。in,

Known as the spectral correlation function (SCF), it is a generalization of the normal power spectral density (PSD). The power spectral density is also non-zero only at the harmonic frequency α=k/T ₀ and decreases to the power spectral density at α=0.

where X _W represents the short-time Fourier transform of a signal segment of duration W. It gives the frequency distribution of the correlation between two frequency shifted versions of the original signal m _x (t). A digital QAM signal with uncorrelated symbols [an ] and timing error τ _{0 is written as x(t)=Σa n g} (t-τ ₀ -nT ₀ ), where g(t) is the pulse shaping function.

Using the cyclic characteristics of the cyclic autocorrelation function, the spectral correlation function of the signal is as formula (5):

That is, the information of the timing error is contained in the spectral correlation function. For a G(f) signal bandwidth limited to ±1/T ₀ , the spectral correlation function is non-zero only at the first two harmonic frequencies, ie when α=0 and α=1/T ₀ . The timing error can be estimated from the frequency-averaged spectral correlation function, and when α=1/T ₀ , the estimated timing error is as in formula (6):

Among them, the first equation is called Godard's timing error detection. The integration can be completed in a small frequency range around f=0, which is equivalent to a weighting function for the spectral correlation function. This is considered a pre-filtering technique to improve the jitter performance of such timing error detection. The second equation in equation (5) is derived from the relationship in equation (2) and is also a direct result of the spectral correlation function and the cyclic autocorrelation function being a pair of Fourier transforms. Using a non-probabilistic expression, the second part is as Equation (6):

This is known as squared timing error detection. In effect, it uses the baud rate of the signal to evaluate the phase of the spectral lines. Kikuchi thinks that this is the second-order periodicity of the cyclostationary random process x(t) converted to the first-order periodicity (harmonic frequency of the baud rate) by a quadratic transformation. Here, the descriptions using the cyclic autocorrelation function and the spectral correlation function are equivalent because α=1/T ₀ .

The dispersion effect of fiber is known to reduce spectral correlation and therefore timing error detection, as it introduces a quadratic phase response into the signal spectrum. Therefore, the spectral correlation function (considering equation (3)) acquires an additional linear phase term due to dispersion. A straightforward way to mitigate the effects of dispersion and restore spectral correlation is of course to compensate for the linear phase term in the spectral correlation function. On the other hand, the frequency domain linear phase term in the spectral correlation function due to chromatic dispersion is equivalent to a constant time offset in the cyclic autocorrelation function. The shift is proportional to the accumulated dispersion, ie, Δτ=λ2DL/(cT ₀ ), where λ is the wavelength of light, D is the dispersion coefficient, L is the fiber length, and c is the speed of light. Δτ is the amount of signal delay due to dispersion. Therefore, one way to recover spectral correlation without compensating for chromatic dispersion is to set an appropriate delay in the cyclic autocorrelation function that is the same as Δτ.

The present invention proposes a new timing error detection calculation formula, such as formula (7):

in,

In practice, the clock phase delay in timing error detection can be quickly located based on linear search, thereby achieving optimal estimation of timing errors. The proposed architecture for dispersion fault-tolerant timing error detection is shown in Figure 2. Let N be the block size of the data samples used to calculate one cyclic autocorrelation function value in equation (7), corresponding to a particular delay τ, and let M be the number of cyclic autocorrelation function points required to search for the maximum value. Additional complexities of the proposed timing error detection include a multiplier of length 2NM for evaluating the modulo square, M comparators for maximization, and N sample buffer space. The block size N can be 512 samples and is proportional to the maximum amount of dispersion to scan.

Specifically, the embodiment of the present invention implements a clock recovery algorithm at the receiving end of the coherent optical communication system, which is specifically implemented through the following process steps:

First of all, it should be noted that the input signal is X(t) and Y(t), X(t) and Y(t) represent the input dual polarization state signal, where X(t)=Ix+i*Qx; Y(t) too. i is an imaginary number, where Ix is the in-phase signal and Qx is the quadrature signal, so both X(t) and Y(t) are complex signals. But individually Ix and Qx are real numbers. The following operations operate on X and Y at the same time, but for simplicity, the description of Y is omitted, because X and Y polarizations undergo the same impairment in the channel, and only the process of X polarization state is described.

first step:

Oversampling both polarization states of the input optical signal, that is, x(t)=resample(X(t)), y(t)=resample(Y(t)) where X(t) is the received original data , x(t) is the oversampled data. At this time, the number of sampling points for each symbol is greater than 2 points. That is, the SPS is greater than 2. The same is true for Y(t).

Step 2:

Calculate P=x(t)*x*(t), Q=y(t)*y*(t). Both x(t) and y(t) are each a sequence of complex numbers. The meaning of P and Q here is the signal autocorrelation. Since x(t) and y(t) are higher order modulations, there are in-phase and quadrature components. Contains phase information, but multiplied by its own conjugate becomes a real number. At this time, both P and Q have no phase information, and they are both real numbers. And P and Q are only positive and negative, because several data points (ie SPS) in x(t) and y(t) represent a symbol of 32G baud rate, the P and Q obtained after autocorrelation are equal to the frequency in the frequency domain. There will be two very high peaks at the baud rate, as shown in Figure 3 is the spectrum of P. The secondary phase of dispersion acts on the intensity, making the two peaks weaker. Therefore, it cannot be determined whether the peak intensity at this time is the maximum. Dispersion causes signal delays at different frequencies in the signal, so do the loop P=x(t)*x*(tt ₀ ), Q=y(t)*y*(tt ₀ ) to find the point with the highest peak intensity, and at the same time This method is also a method of compensating for dispersion, because when the peak is the largest, the dispersion is the smallest. Here t ₀ is the delayed sequence x(t) data time (but the corresponding digital signal processing can only be an integer number of points in the sequence). When P and Q are calculated, the P and Q corresponding to the data of each t ₀ are in the memory, so the delay data point TT ₀ when P and Q are multiplied to obtain the maximum value is calculated.

third step:

Shift the TT ₀ calculated in the second step to the signal x(t), and shift the signal x(t) by TT ₀ data points, that is, x(t-TT ₀ ) to obtain the sequence m(t).

the fourth step:

(如果乘

对应时域上移动一个整数点。但是计算中取n＝32，n₀从1增加到32逐渐增加。因此频域上乘的这个相位在时域中移动不足一个点，前面第二步已经说了那一步只可以整数个点移动，但是这一步可以移动不是整数个点)两者相乘得到序列

同理Y偏振同样操作得到F(w)。对序列G(w)和F(w)中的所有元素求和并相加得到S(w)，取复数S(w)的虚部，虚部计算值就是定时误差检测的结果。其中f是信号频率，T₀是符号周期，n是把频率分辨率分成n份(频率分辨率是指数字信号处理中频域上两个点之间代表的频率差)。使用XY两个相加是为了取平均，以免单个偏振态出现偶然性。Calculate A=m(t)m*(t), this A is already an autocorrelation sequence, multiplied by the phase

(if multiplying

Move an integer point in the corresponding time domain. However, n=32 is taken in the calculation, and n ₀ increases gradually from 1 to 32. Therefore, the phase that is multiplied in the frequency domain moves by less than one point in the time domain. As mentioned in the second step above, only an integer number of points can be moved in this step, but this step can be moved by not an integer number of points) Multiply the two to obtain the sequence

In the same way, Y polarization is also operated to obtain F(w). Sum and add all elements in the sequences G(w) and F(w) to obtain S(w), take the imaginary part of the complex number S(w), and the calculated value of the imaginary part is the result of timing error detection. Where f is the signal frequency, T ₀ is the symbol period, and n is the frequency resolution divided into n parts (frequency resolution refers to the frequency difference represented by two points on the frequency domain in digital signal processing). The XY two additions are used to average and avoid chance of a single polarization state.

the fifth step:

The fourth step is a repeated process, n ₀ repeats 32 times and gradually increases, (as mentioned earlier, if there is no time shift, there will be no phase in the frequency domain. At this time, the co-belief and quadrature signals satisfy the signal (Ix) ² =(Qx) ^2Because Ix and Qx are respectively loaded on the laser expressed by sine and cosine functions, and Ix and Qx are random sequences.And if sampling at the best time, the above formula is satisfied, but the frequency domain is introduced due to the clock error phase results in not satisfying the equation) resulting in 32 S(w). If the calculated S(w) is zero at this time, it means sampling at the best sampling point. If S(w) is not zero, there is a clock error. Therefore, the method of judging the clock error is the abscissa of S(w)=0. Because the abscissa is the value of n ₀ . That is, first multiply the frequency domain signal by a phase, and then check whether it is the best sampling point at this time. If not, continue to multiply the next phase.

Step 6:

则时域上距离最佳采样点的距离点数是L/32。The abscissa obtained in the fifth step is one of the 32 points moved in the fifth step, let's say the Lth point. Then the phase introduced due to the clock error is

Then the number of distance points from the optimal sampling point in the time domain is L/32.

It should be noted that the clock recovery quality can be evaluated through performance indicators such as clock component strength and clock jitter variance.

In some embodiments, a simulation verification method is also included. The method is based on a simulation system for numerical simulation of an optical communication system. The simulation system includes: an optical transmitter, a dispersion introduction module, a receiving part, and a signal processing part; the method includes: The following steps:

A) The optical transmitter electro-optically modulates the laser light emitted by the laser, and adopts a modulation format such as quadrature amplitude modulation to generate an emission optical signal carrying the modulated signal;

B) When the transmitted optical signal passes through the optical transmission link, the dispersion effect in the optical fiber causes the signal to be distorted. Signal distortion caused by fiber dispersion effects will affect the strength of the clock component related to the signal baud rate;

C) The output optical signal after passing through the optical transmission link will be photoelectrically detected in the receiving part, and then quantized and converted into a digital signal at a suitable sampling rate through an analog-to-digital conversion circuit;

D) The digital signal output by the receiving part is used for timing error detection by the signal processing part through the clock recovery algorithm.

The specific simulation verification of the system scheme is as follows:

In the simulation, MATLAB software is used to numerically simulate the dispersion tolerant clock recovery algorithm system. The system consists of four parts: optical transmitter, dispersion introduction module, receiving part and signal processing part. Among them, the signal processing part will include three functions: oversampling module, timing detection part, and timing performance evaluation.

In this simulation system, the cumulative dispersion (CD) value of the optical transmission link is set in the range of 0-10 ns/nm. For the digital signal obtained by the receiving part, the signal is resampled to different signal baud rate multiples based on digital interpolation. Then, the dispersion-tolerant timing detection method proposed by the present invention is applied to the oversampled digital signal to perform timing detection to obtain the timing phase. The timing phase obtained by timing detection of the dispersion-tolerant timing detection method proposed by the present invention is compared with the performance of the traditional timing detection method under different cumulative dispersion conditions, and the clock component strength, timing jitter variance and S-curve performance of the two are compared. When the accumulated dispersion in optical fiber transmission exceeds a certain amount, the traditional clock recovery in signal processing at the receiving end cannot lock and determine the optimal sampling time. The dispersion-tolerant timing detection method proposed by the present invention can still obtain an accurate timing phase under the cumulative dispersion amount of 10ns/nm, the clock component strength is kept at a high level, the timing jitter variance is kept at a low level, and the maximum value indicated by the S curve The best sampling phase accuracy is high. The simulation results are shown in Figures 3 and 4. It can be seen that the timing jitter variance and clock component strength of the algorithm of the present invention in 2.1 times, 3 times and 4 times oversampling are smaller than those of the traditional algorithm, and the performance of the algorithm of the present invention is better than that of the traditional algorithm .

In summary, clock recovery algorithms play an important role in digital signal processing (DSP) in modern coherent optical communication systems. Reference signal baud rate and local sampling clock at the receiving end, and find the best sampling moment through continuous timing error correction. Among the algorithms for clock recovery, timing error detection (TED) is primarily used to provide instantaneous error tracking. However, the usual timing error detection suffers from effects such as chromatic dispersion (CD) and rotation of polarization (ROP), so additional compensation algorithms are required to remove the effects of these linear impairments before timing error detection. In view of the problems in the prior art, the embodiments of the present invention propose an improved squared timing error detection based on a signal-based cyclic autocorrelation function (CAF), which generalizes its classical correspondence function and exhibits a larger dispersion tolerance. It provides a dispersion-tolerant timing error detection time domain solution. The equivalence between temporal error detection in the time and frequency domains is re-established in the framework of spectral correlation. The modified squared timing error detection requires minimal additional complexity. Numerical simulations are performed to investigate the performance of the proposed timing error detection. Specifically, the present invention analyzes the common squared timing error detection from the perspective of cyclostationarity theory, thereby naturally solving the problem of dispersion fault-tolerant timing error detection. With this solution, a generalized squared timing error detection is obtained, which can tolerate large dispersion without prior dispersion equalization.

In some alternative implementations, the functions/operations noted in the block diagrams may occur out of the order noted in the operational diagrams. For example, two blocks shown in succession may, in fact, be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/operations involved. Furthermore, the embodiments presented and described in the flowcharts of the present invention are provided by way of example in order to provide a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of the various operations are altered and in which sub-operations described as part of larger operations are performed independently.

Furthermore, although the invention has been described in the context of functional modules, it is to be understood that, unless stated to the contrary, one or more of the described functions and/or features may be integrated in a single physical device and/or or software modules, or one or more functions and/or features may be implemented in separate physical devices or software modules. It will also be appreciated that a detailed discussion of the actual implementation of each module is not necessary to understand the present invention. Rather, given the attributes, functions, and internal relationships of the various functional modules in the apparatus disclosed herein, the actual implementation of such modules will be within the routine skill of the engineer. Accordingly, those skilled in the art, using ordinary skill, can implement the invention as set forth in the claims without undue experimentation. It is also to be understood that the specific concepts disclosed are illustrative only and are not intended to limit the scope of the invention, which is to be determined by the appended claims along with their full scope of equivalents.

The functions, if implemented in the form of software functional units and sold or used as independent products, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention can be embodied in the form of a software product in essence, or the part that contributes to the prior art or the part of the technical solution. The computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, Read-Only Memory (ROM, Read-Only Memory), Random Access Memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program codes .

The logic and/or steps represented in flowcharts or otherwise described herein, for example, may be considered an ordered listing of executable instructions for implementing the logical functions, may be embodied in any computer-readable medium, For use by, or in conjunction with, an instruction execution apparatus, apparatus, or apparatus (such as a computer-based apparatus, an apparatus including a processor, or other apparatus that can fetch and execute instructions from an instruction execution apparatus, apparatus, or device) or equipment. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport the program for use by or in connection with an instruction execution apparatus, apparatus, or apparatus.

More specific examples (non-exhaustive list) of computer readable media include the following: electrical connections with one or more wiring (electronic devices), portable computer disk cartridges (magnetic devices), random access memory (RAM), Read Only Memory (ROM), Erasable Editable Read Only Memory (EPROM or Flash Memory), Fiber Optic Devices, and Portable Compact Disc Read Only Memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program may be printed, as the paper or other medium may be optically scanned, for example, followed by editing, interpretation, or other suitable medium as necessary process to obtain the program electronically and then store it in computer memory.

It should be understood that various parts of the present invention may be implemented in hardware, software, firmware or a combination thereof. In the above-described embodiments, various steps or methods may be implemented in software or firmware stored in memory and executed by suitable instruction execution means. For example, if implemented in hardware, as in another embodiment, it can be implemented by any one or a combination of the following techniques known in the art: Discrete logic circuits, application specific integrated circuits with suitable combinational logic gates, Programmable Gate Arrays (PGA), Field Programmable Gate Arrays (FPGA), etc.

In the description of this specification, description with reference to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples", etc., mean specific features described in connection with the embodiment or example , structure, material or feature is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that various changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, The scope of the invention is defined by the claims and their equivalents.

The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the described embodiments, and those skilled in the art can also make various equivalent deformations or replacements on the premise of not violating the spirit of the present invention, These equivalent modifications or substitutions are all included within the scope defined by the claims of the present invention.

Claims (10)

1. A dispersion tolerant clock recovery method, comprising:

oversampling the input dual-polarized optical signal to obtain sampling data;

performing signal autocorrelation processing according to the sampling data to determine a delay data point;

according to the delay data points, carrying out shift processing on the sampling data to obtain a first sequence and a second sequence;

determining a first autocorrelation sequence by the first sequence, determining a second autocorrelation sequence by the second sequence, determining a third sequence from the first autocorrelation sequence in combination with a delayed data sequence length, determining a fourth sequence from the second autocorrelation sequence; the length of the delay data sequence is determined according to the delay data points, the frequency resolution of the length of the delay data sequence is divided according to the target quota number, and the quota of the frequency resolution of the length of the delay data sequence is increased from 1 to the target quota number;

determining a fifth sequence from the third sequence and the fourth sequence;

determining the number of distance points from the target sampling point in the time domain according to the fifth sequence;

and recovering the clock according to the distance points.

2. A dispersion-tolerant clock recovery method as recited in claim 1, further comprising:

and performing clock recovery quality evaluation according to the clock component strength and the clock jitter variance.

3. The dispersion-tolerant clock recovery method of claim 1, wherein oversampling the input dual-polarized optical signal to obtain sampled data comprises:

oversampling the first polarization state signal according to a sample function to obtain first sampling data;

and oversampling the second polarization state signal according to a response function to obtain second sampling data.

4. A dispersion-tolerant clock recovery method as claimed in claim 1, wherein said performing signal autocorrelation processing on said sampled data to determine delay data points comprises:

determining signal autocorrelation data according to the sampling data;

introducing delay data time, and performing cycle processing on the signal autocorrelation data;

determining a delay data point from the cyclically processed signal autocorrelation data.

5. A dispersion-tolerant clock recovery method according to claim 1, wherein said determining a fifth sequence from said third sequence and said fourth sequence comprises:

summing and adding elements of the third sequence and the fourth sequence to obtain a fifth sequence;

wherein the number of the fifth sequences is a target volume number.

6. A dispersion-tolerant clock recovery method according to claim 1, wherein said determining the number of distance points in the time domain from a target sample point from said fifth sequence comprises:

when the value of the fifth sequence is zero, determining the number of distance points from a target sampling point in a time domain according to the frequency resolution share of the length of the delay data sequence;

wherein the number of distance points is a ratio of a share of the frequency resolution of the length of the delayed data sequence to the target share number.

7. A dispersion tolerant clock recovery method according to any one of claims 1 to 6, further comprising:

and carrying out simulation verification according to a simulation system of the optical communication system numerical simulation.

8. A dispersion tolerant clock recovery system comprising:

the device comprises a first module, a second module and a third module, wherein the first module is used for oversampling an input dual-polarization optical signal to obtain sampling data;

the second module is used for carrying out signal autocorrelation processing according to the sampling data and determining a delay data point;

a third module, configured to perform shift processing on the sampled data according to the delayed data point to obtain a first sequence and a second sequence;

a fourth module, configured to determine a first autocorrelation sequence by the first sequence, determine a second autocorrelation sequence by the second sequence, determine a third sequence according to the first autocorrelation sequence in combination with a length of a delayed data sequence, and determine a fourth sequence according to the second autocorrelation sequence; the length of the delay data sequence is determined according to the delay data points, the frequency resolution of the length of the delay data sequence is divided according to the target quota number, and the quota of the frequency resolution of the length of the delay data sequence is increased from 1 to the target quota number;

a fifth module for determining a fifth sequence from the third sequence and the fourth sequence;

a sixth module, configured to determine, according to the fifth sequence, a number of distance points from a target sampling point in a time domain;

and the seventh module is used for carrying out clock recovery according to the distance point number.

9. An electronic device comprising a processor and a memory;

the memory is used for storing programs;

the processor executing the program realizes the method of any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that the storage medium stores a program, which is executed by a processor to implement the method according to any one of claims 1 to 7.

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