CN114731205B

CN114731205B - A clock synchronization method and device

Info

Publication number: CN114731205B
Application number: CN201980102220.6A
Authority: CN
Inventors: 黄天强; 刘威; 邱贤文
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2019-11-21
Filing date: 2019-11-21
Publication date: 2025-05-16
Anticipated expiration: 2039-11-21
Also published as: WO2021097769A1; CN114731205A

Abstract

A clock synchronization method and device are used to solve the problem of inaccurate time synchronization. The method includes: a first device sends first data, adds a timestamp to the first data, and determines the position of the data corresponding to the timestamp in the first data, and the first time of sending the data corresponding to the timestamp; determines the transmission delay generated by the data at the position during the format conversion process; sends a first message to the second device, the first message indicates the time after compensation for the first time; receives a second message sent by the second device at a third time; sends a third message containing the third time to the second device, so that the second device performs clock synchronization. The method pre-compensates for the determined transmission delay, effectively solves the impact of data format conversion of the transmitted data on clock synchronization, and improves the accuracy of time synchronization.

Description

Clock synchronization method and device

Technical Field

The present invention relates to the field of wireless communications technologies, and in particular, to a clock synchronization method and apparatus.

Background

In order to improve the transmission efficiency of data, data clock synchronization is required between a sender and a receiver of data. At present, clock synchronization between devices is mainly performed based on the precision clock synchronization protocol standard (IEEE 1588 protocol) of a network measurement and control system.

As shown in fig. 1, a specific clock synchronization process between a data sender and a data receiver is as follows:

And when the data transmission is carried out on the data receiver by the data transmission, a synchronous (sync) message carrying data is transmitted to the data receiver, and the data receiver records the receiving time T2 for receiving the sync message. Then, the data transmitting party transmits a follow-up (follow-up) message carrying the real time T1 of the data transmission to the data receiving party, and the data receiving party acquires the T1 in the follow-up message. After receiving the Sync message, the data receiving party sends a Delay request (delay_req) message to the data sending party, and records a sending time T3 for sending the delay_req message. After receiving the delay_req message, the data sender records the accurate receiving time T4 of the delay_req message, then sends a Delay response (delay_resp) message carrying the T4 to the data receiver, and the data receiver acquires the T4 in the delay_resp message. Thus, the data receiving side determines the time difference between the data transmitting side and the data receiving side and the path delay of the data transmission process according to four time points T1, T2, T3 and T4 based on the IEEE1588 protocol. And the data receiver realizes clock synchronization between the data sender and the data receiver according to the determined time difference and the path delay.

In communication services, however, the data format of the transmission data often needs to be processed when the data sender performs data transmission. For example, when the data sender and the data receiver use a clock data recovery (Clock data recovery, CDR) system for data transmission, the transmission data is typically processed in a data format using a forward error correction coding technique (Forward error correction, FEC). And the data format change of the transmission data generates larger delay jitter.

When the prior art cannot change the data format aiming at the data, the accurate clock synchronization between the data sender and the data receiver is realized, so that the data transmission efficiency between the data sender and the data receiver is reduced.

Disclosure of Invention

The embodiment of the application provides a clock synchronization method and device, which are used for solving the problem that clock synchronization is not accurate enough when data format processing exists in the prior art.

In a first aspect, an embodiment of the present application provides a method for clock synchronization, where the method is used in a network environment including a first device, a conversion device and a second device, where the conversion device is configured to obtain second data after format conversion of first data of the first device, and send the second data to the second device, where the method includes:

The first device sends first data, marks a time stamp in the first data, determines the data position of the data corresponding to the time stamp in the first data, and sends first time of the data corresponding to the time stamp, the first device determines transmission delay generated in the format conversion process of the data position according to the data position, the first device sends first information to the second device, the first information is used for indicating second time, the second time is time after the first time is compensated according to the transmission delay, the first device receives second information sent by the second device at third time, the first device sends third information to the second device, and the third information comprises the third time, so that clock synchronization between the second device and the first device is carried out according to the second time, the third time and fourth time for sending the second information.

Based on the scheme, in the communication transmission process, a first device determines transmission delay generated in the process of converting a data format of transmission data and first time for transmitting data recorded with a timestamp in the first data, then indicates second time for clock synchronization of a second device according to the transmission delay and the first time, wherein the second time is time after the first time is compensated according to the transmission delay, so that the second device performs clock synchronization according to the compensated transmission time, delay jitter generated in the process of converting the data format of the transmission data is effectively solved, influence on clock synchronization is caused, and accuracy of the time synchronization is improved.

In one possible implementation manner, the first message includes the first time and the transmission delay, so that the second device compensates the first time according to the transmission delay to obtain a second time, or the first message includes the second time.

In one possible implementation, the first message is a follow-up message, the second message is a Delay request delay_req message, and the third message is a Delay response delay_resp message.

In one possible implementation manner, the alignment mark in the second data is unchanged from the data relative to the second data during the transmission process of the second data.

In a second aspect, an embodiment of the present application provides a clock synchronization method, configured to be used in a network environment including a first device, a conversion device, and a second device, where the conversion device is configured to convert a format of first data of the first device to obtain second data, and send the second data to the second device, where the method includes:

The method comprises the steps that a second device receives second data sent by a conversion device, the second device receives a first message sent by the first device, the first message is used for indicating second time, the second time is time after first time is compensated according to transmission delay, the transmission delay is generated in a format conversion process of time-stamped data in the first data, the first time is time for sending data corresponding to the time stamp to the first device, the second device sends the second message to the first device at fourth time, the second device receives a third message sent by the first device, the third message comprises third time for the first device to receive the second message, and the second device performs clock synchronization with the first device according to the second time, the third time and the fourth time.

Based on the scheme, in the communication transmission process, the second device receives the first message sent by the first device and indicating the second time, wherein the second time is the time after the first time is compensated according to the transmission delay, so that the second device performs clock synchronization according to the compensated sending time, the influence on clock synchronization caused by delay jitter generated in the data format conversion process of the transmission data is effectively solved, and the accuracy of the time synchronization is improved.

In one possible implementation, before the second device performs clock synchronization with the first device according to the second time, the third time and the fourth time, the method further includes determining, by the second device, the second time according to the transmission delay and the first time included in the first message.

In a third aspect, an embodiment of the present application provides a method for clock synchronization, where the method is used in a network environment including a first device, a conversion device and a second device, where the conversion device is configured to obtain second data after format conversion of first data of the first device, and send the second data to the second device, where the method includes:

The method comprises the steps that a second device receives second data sent by a conversion device, the second device determines transmission delay generated in a format conversion process of time-stamped data in the second data, the second device receives a first message sent by a first device, the first message comprises the first time, the second device sends a second message to the first device at a fourth time, the second device receives a third message sent by the first device, the third message comprises a third time when the first device receives the second message, and the second device performs clock synchronization with the first device according to the first time, the transmission delay, the third time and the fourth time.

Based on the scheme, in the communication transmission process, the second device determines the transmission delay generated in the data format conversion process of the data, and then compensates the received first time from the first device according to the transmission delay to obtain the second time, so that clock synchronization is performed according to the second time, the influence of the data format processing of the transmission data on the clock synchronization is effectively solved, and the accuracy of the time synchronization is improved.

In one possible implementation manner, the second device compensates the first time according to the transmission delay to obtain a second time, and the second device performs clock synchronization with the first device according to the second time, the third time and the fourth time.

In a fourth aspect, an embodiment of the present application provides a communication apparatus having a function of implementing the device in the first to third aspects in the above-described embodiments. The functions can be realized by hardware, and can also be realized by executing corresponding software by hardware. The hardware or software includes one or more units or modules corresponding to the functions described above.

In a possible implementation manner, the communication apparatus may be the first device in the first aspect, or may be a component, such as a chip or a chip system or a circuit, that may be used in the first device, where the communication apparatus may include a transceiver and a processor. The processor may be configured to support the communication apparatus to perform the respective functions of the first device described above, the transceiver being for supporting communication between the communication apparatus and other devices (e.g. second devices) or the like. Optionally, the communication device may further comprise a memory, which may be coupled to the processor, which holds the necessary program instructions and data for the communication device. The transceiver may be a stand-alone receiver, a stand-alone transmitter, a transceiver with integrated transceiver functions, or an interface circuit.

In another possible implementation manner, the communication apparatus may be the second device in the second aspect or the third aspect, or may be a component, such as a chip or a chip system or a circuit, that may be used in the second device, where the communication apparatus may include a transceiver and a processor. The processor may be configured to support the communication apparatus to perform the respective functions of the second device described above, the transceiver being for supporting communication between the communication apparatus and other devices (e.g. the first device) or the like. Optionally, the communication device may further comprise a memory, which may be coupled to the processor, which holds the necessary program instructions and data for the communication device. The transceiver may be a stand-alone receiver, a stand-alone transmitter, a transceiver with integrated transceiver functions, or an interface circuit.

In a fifth aspect, an embodiment of the present application provides a communications device configured to implement any one of the first aspect or the method of the first aspect.

In one possible implementation manner, when the communication apparatus is a first device, the communication apparatus may include a processing unit and a communication unit:

the communication unit is used for sending the first data;

The processing unit is used for marking a time stamp in the first data, determining the data position of the data corresponding to the time stamp in the first data and transmitting the first time of the data corresponding to the time stamp;

The communication unit is used for sending a first message to the second equipment, the first message is used for indicating a second time, the second time is the time after the first time is compensated according to the transmission delay, the second message sent by the second equipment is received at a third time, the third message is sent to the second equipment, and the third message comprises the third time, so that the second equipment performs clock synchronization with the first equipment according to the second time, the third time and a fourth time for sending the second message.

In a sixth aspect, an embodiment of the present application provides a communications device configured to implement any one of the second aspect or the second aspect.

In one possible implementation manner, when the communication apparatus is a second device, the communication apparatus may include a processing unit and a communication unit:

The communication unit is used for receiving second data sent by conversion equipment, receiving first information sent by the first equipment, wherein the first information is used for indicating second time, the second time is time after first time is compensated according to transmission delay, the transmission delay is generated in a format conversion process of data with time stamps in the first data, the first time is the sending time of the data corresponding to the time stamps sent by the first equipment, and the second information is sent to the first equipment at fourth time;

The processing unit is configured to perform clock synchronization with the first device according to the second time, the third time and the fourth time.

In a seventh aspect, an embodiment of the present application provides a communications device configured to implement any one of the above third aspect or the third aspect.

the communication unit is used for receiving the second data sent by the conversion equipment;

the processing unit is used for determining transmission delay generated in the format conversion process of the data marked with the time stamp in the second data;

The communication unit is used for receiving a first message sent by the first device, wherein the first message comprises the first time, sending a second message to the first device at a fourth time, receiving a third message sent by the first device, wherein the third message comprises a third time when the second message is received by the first device, and performing clock synchronization with the first device according to the first time, the transmission delay, the third time and the fourth time.

In an eighth aspect, an embodiment of the present application provides a communication system including a first device and a second device. The first device may be configured to perform any one of the above first aspects, or perform any one of the above methods of the first aspect;

the second device is configured to perform any one of the second aspect or the third aspect, or is configured to perform any one of the methods of the first aspect or the third aspect.

In a ninth aspect, the present application provides a system on a chip, comprising a processor. Optionally, a memory may be further included, the memory being configured to store a computer program, the processor being configured to call and run the computer program from the memory, so that the communication device on which the chip system is mounted performs any one of the first to third aspects described above, or performs any one of the methods of the first to third aspects described above.

In a tenth aspect, embodiments of the present application provide a computer storage medium having instructions stored therein, which when run on a communications device, cause the communications device to perform any one of the above first to third aspects, or to perform any one of the above methods of the first to third aspects.

In an eleventh aspect, embodiments of the present application provide a computer program product comprising instructions which, when run on a communications apparatus, cause the communications apparatus to perform any one of the above first to third aspects, or to perform any one of the above methods of the first to third aspects.

Drawings

Fig. 1 is a schematic diagram of a conventional message transmission between a transmitting device and a receiving device based on IEEE 1588;

FIG. 2 is a schematic diagram of a conventional timestamp marking method in a data transmission process;

FIG. 3 is a schematic diagram of a system architecture according to an embodiment of the present application;

fig. 4 is a flow chart corresponding to a time synchronization method according to an embodiment of the present application;

fig. 5 is a schematic diagram of determining transmission delay by performing FEC encoding according to an embodiment of the present application;

fig. 6 is a schematic diagram of compensation of a transmission time T1 according to an embodiment of the present application;

Fig. 7 is a flow chart corresponding to another clock synchronization method according to an embodiment of the present application;

Fig. 8 is a schematic structural diagram of a first device according to an embodiment of the present application;

Fig. 9 is a schematic structural diagram of a second first device according to an embodiment of the present application;

fig. 10 is a schematic structural diagram of a first second device according to an embodiment of the present application;

Fig. 11 is a schematic structural diagram of a second device according to an embodiment of the present application;

fig. 12 is a schematic structural diagram of a third second device according to an embodiment of the present application;

fig. 13 is a schematic structural diagram of a fourth second device according to an embodiment of the present application.

Detailed Description

The present application will be described in detail with reference to the accompanying drawings.

In the communication service, when the data sender performs data transmission, in order to improve the data transmission efficiency and reduce the error rate, it is often necessary to convert the data format of the transmission data. For example, when the data sender and the data receiver use CDR/Retimer system to perform data transmission, FEC encoding technology is generally used to perform data format conversion on the transmission data. The data format conversion of the transmission data generates a larger delay jitter, wherein the delay jitter generated by the data format conversion is referred to as transmission delay in the embodiment of the present application.

For example, as shown in fig. 2, it is assumed that, in the data transmission process, the data of the position a in the transmission data is used as a reference of a time stamp, that is, the transmission device uses the transmission time of the data of the position a as the transmission time of the transmission data.

Case 1: data transmitted by a first device to a second device does not require data format conversion.

For example, the first device directly sends the data to be transmitted to the second device, and then the first device sends a sync message carrying the data to be transmitted to the second device, marks a time stamp in the data to be transmitted, and determines a data position of the data corresponding to the time stamp in the data to be transmitted and a first time for sending the data corresponding to the time stamp. The second device records that the time of receiving the sync message is 1:10 (i.e., time T2).

Assuming that the sending time of the position a data is determined to be 1:00 by the first device, the first device determines that the timestamp in the low_up message is 1:00 according to the sending time of 1:00, that is, after the sending time of the position a data is determined by the first device, generates a timestamp according to the sending time, and carries the timestamp in the low_up message. And the first device sends the follow_up message to the second device. The second device receives the follow_up message and obtains a timestamp 1:00 (i.e., time T1) in the follow_up message.

From this, the second device can derive the sum of the time difference Offset between the first device and the second device and the network transmission Delay according to the following formula 1 and the known T1 and T2.

T2—t1=offset +Delay equation 1

Substituting 1:00 for T1 and 1:10 for T2 into equation 1 above can determine that the sum of the Offset and the Delay is 10.

In the embodiment of the present application, the "time stamping in the transmission data" refers to that after determining the sending time of the data of the location a, the first device generates a credential document (i.e. a time stamp), and the sending time of the data of the location a can be known through the time stamp. Further, the first device may record the credential document (i.e. the timestamp) in the follow_up message, and send the follow_up message to the second device, so that the second device obtains the sending time of the data of the location a.

It should be noted that the above explanation of "time stamping in the transmission data" is not limited to the embodiment of the present application. Since the time of occurrence of certain events is often determined or proven by means of time stamping during communication transmission, the meaning of "the first device time stamps the transmission data" as described in embodiments of the present application will be understood by a person skilled in the art.

And 2, the data transmitted from the first equipment to the second equipment need to be subjected to data format conversion.

For example, the first device sends the sync message carrying the transmission data to the second device through a conversion device (for example, the conversion device is CDR/re-timer), where the transmission data is subjected to data format conversion in the conversion device.

The first device determines the sending time of the transmission data (i.e. the data of the position a), and if the sending time of the transmission data is 1:00, the first device determines that the timestamp in the flush_up message is 1:00 according to the sending time of 1:00. And then, the first device sends the follow_up message to the second device. The second device receives the follow_up message and obtains a timestamp 1:00 (i.e., time T1) in the follow_up message.

However, the transmission delay is generated when the data format of the transmission data is converted by the conversion device, and the transmission delay is assumed to be 5 minutes when the data format of the transmission data is converted by the conversion device. Thus, the second device records that the sync message is received for a time of 1:15 (i.e., time T2).

From this, the second device can derive the sum of the time difference Offset between the first device and the second device and the network transmission Delay according to the above formula 1 and the known T1 and T2.

Substituting 1:00 for T1 and 1:15 for T2 into equation 1 above may determine that the sum of the Offset and the Delay is 15.

Obviously, as is apparent from the description of the case 1 and the case 2, it is known that the sum of the Offset and the Delay determined in the case 2 is not the sum of the Offset and the Delay in the data transmission process of the first device and the second device, and therefore, the clock synchronization of the second device with the first device based on the Offset and the Delay obtained in the case 2 may generate a larger error, and cannot achieve accurate clock synchronization.

Therefore, in the prior art, when the transmitted data needs to be processed in a data format, clock synchronization between the first device and the second device cannot be accurately realized, so that the data transmission efficiency between the first device and the second device is reduced.

On the other hand, when data format conversion is performed by the encoding technique, delay jitter generated by FEC encoding can be compensated for according to a similar table 1 as described below. The delay time generated by the FEC encoding provided in the prior art is the maximum delay time that can be generated. Assuming that the FEC (528,541) in table 1 is taken as an example, it is known that when the port is 25, the maximum transmission delay that may occur is 5.6ns. In each data transmission process, the data at a certain position in the transmission data is used as a reference to determine a time stamp, the transmission delay generated by data format conversion of the data at the position is not necessarily 5.6ns, and in the clock synchronization process, the prior art cannot compensate for the data at a specific position, so that the problems of large clock synchronization error and incapability of realizing accurate clock synchronization still exist.

FEC algorithm	Port (port)	Check bit	Uncertainty propagation delay (ns)
				(528,514)	25	140	5.6
(528,514)	100	140	1.4
				(544,514)	50	300	6
(544,514)	100	300	3
				(544,514)	200	300	1.5
(544,514)	400	300	0.75

Table 1 FEC transmission delay of uncertainty resulting from encoding

In order to solve the above-mentioned problems, the technical solution of the present application may be applied to various communication systems, such as a long term evolution (long term evolution, LTE) system, a worldwide interoperability for microwave access (worldwide interoperability for microwave access, wiMAX) communication system, a future fifth generation (5th Generation,5G) system, such as a new generation radio access technology (new radio access technology, NR), and a future communication system, such as a 6G system.

Taking a 5G system (also referred to as a New Radio system) as an example, specifically, in order to accurately solve the problem of transmission delay generated in the data format conversion process, in the embodiment of the present application, the transmission delay generated in the data format conversion of the transmission data is determined, and the transmission delay is compensated to the sending time, such as the sending time T1, of the data sent by the first device to the second device. By the method, when the second device performs clock synchronization with the first device, the sending time T1 for performing clock synchronization is the compensated time, so that the transmission delay generated by data format conversion of the transmission data is eliminated, the influence of the data format conversion process of the transmission data on clock synchronization is effectively solved, and the accuracy of time synchronization is improved.

It should be noted that, the time synchronization in the embodiment of the present application may also be referred to as clock synchronization.

Fig. 3 is a schematic diagram of a system architecture to which an embodiment of the present application is applicable. As shown in fig. 3, the system architecture includes one or more first devices 301, e.g., a gNB, eNodeB, or WLAN access point, one or more second devices 302, one or more translation devices 303 (e.g., CDR/re), and a core network 304.

In an embodiment of the present application, the first device 301 may include a base transceiver station (Base Transceiver Station), a wireless transceiver, a Basic service set (Basic SERVICE SET, BSS), an Extended service set (Extended SERVICE SET, ESS), nodeB, eNodeB, gNB, and so on.

Among other things, several different types of first devices 301 may be included in the system architecture, such as macro base stations (macro base station), micro base stations (micro base station), and so on. The first device 301 may apply different radio technologies, such as a cell radio access technology, or a WLAN radio access technology.

The second device 302 may be a device with wireless transceiver capability, which may be deployed on land, including indoor or outdoor, hand-held or vehicle-mounted, on water (e.g., ship, etc.), or in air (e.g., airplane, balloon, satellite, etc.). The terminal device may be a mobile phone (mobile phone), a tablet (Pad), a computer with a wireless transceiving function, a Virtual Reality (VR) terminal device, an augmented reality (augmented reality, AR) terminal device, a wireless terminal device in industrial control (industrial control), a wireless terminal device in unmanned (SELF DRIVING), a wireless terminal device in remote medical (remote medical), a wireless terminal device in smart grid (SMART GRID), a wireless terminal device in transportation security (transportation safety), a wireless terminal device in smart city (SMART CITY), a wireless terminal device in smart home (smart home), or the like.

The core network device 304 may be a mobility management entity (mobility MANAGEMENT ENTITY, MME) in an LTE system, or a mobility management function (ACCESS AND mobility management function, AMF) network element and a session management function (session management function, SMF) network element in a 5G communication system, which is not specifically limited.

The embodiment of the present application is mainly described by taking the system architecture illustrated in fig. 3 as an example, but is not limited thereto.

Communication systems for which the above system architecture is applicable include, but are not limited to, wideband code division multiple access mobile communication systems (wideband code division multiple access, WCDMA), evolved universal terrestrial radio access network (evolved universal terrestrial radio access network, E-UTRAN) systems, long term evolution (long term evolution, LTE) systems, future fifth generation (5th Generation,5G) systems, such as new generation radio access technologies (new radio access technology, NR), and future communication systems, such as 6G systems, etc.

Some terms involved in the embodiments of the present application are explained below to facilitate understanding.

1) FEC, which is a coding technique, is an error control method and a method for increasing the reliability of data communication. The method mainly refers to a technology that signals are coded in advance according to a certain algorithm before being sent into a transmission channel, redundant codes with the characteristics of the signals are added, and received signals are decoded at a receiving end according to the corresponding algorithm, so that error codes generated in the transmission process are found out and corrected.

2) The precision clock synchronization protocol standard (IEEE 1588 Precision Clock Synchronization Protocol) of the network measurement and control system, namely precision time protocol (Precision Timing Protocol, PTP) is mainly based on the principle that clocks of all nodes in a network are periodically corrected and synchronized through a synchronization signal, so that the distributed system based on the Ethernet can achieve the precise synchronization, and the distributed system based on the Ethernet has the characteristics of easiness in configuration, rapid convergence, low consumption of network bandwidth and resources and the like. The IEEE 1588 clock synchronization technique in the embodiment of the present application may be applied to any multicast network.

3) The message is a data unit exchanged and transmitted in the network, namely, a data block to be sent by the station at one time. The message contains the complete data information to be sent, and the length of the message is not consistent, and the length of the message is unlimited and variable.

In the IEEE1588 time synchronization system, the message mainly includes a sync synchronization message, a follow_up follow message, a delay_req delay request message, a delay_resp delay response message, and the like. The sync message is periodically sent from the master clock, and includes a timestamp for accurately describing the expected sending time of the data packet sent by the master clock, where the expected sending time is not the real sending time.

The follow-up message is sent from the master clock after determining the real sending time of the sync synchronous message, and the follow-up message comprises a real sending time T1 for accurately describing the sending of the sync synchronous message by the master clock. The slave clock may determine a time difference (T2-T1) between the master clock and the slave clock according to a receiving time T2 when the sync message is received and the real sending time T1 in the follow message.

The time difference calculated at this time includes the Delay caused by the network transmission, so the delay_req message is used to define the transmission Delay of the network.

The delay_req message is sent by a slave clock after the slave clock receives the Sync message, and the slave clock records the accurate sending time T3 of the delay_req message, and the master clock records the accurate receiving time T4 of the delay_req message as the Sync message. After the master clock receives the delay_req message, recording the accurate receiving time T4 of the delay_req message, carrying the T4 in a delay_resp message sent to a slave clock, and informing the slave clock of the T4 through the delay_resp message, thereby enabling the slave clock to calculate network Delay and clock error.

4) The Reed-solomon codes (RS), which is a channel coding for forward error correction, is effective for correcting polynomials generated by oversampled data. When the receiver correctly receives enough points, the receiver can restore the original polynomial, and even if a plurality of points on the received polynomial are distorted by noise interference, the receiver can restore the polynomial.

5) The re-timing (re-timer) chip is mainly used for reconstructing signals through an internal clock when the signals pass through the re-timer, so that the signal transmission energy is increased, and then the signals are continuously transmitted, so that the jitter of the signals can be reduced.

6) A timestamp, which is a piece of complete verifiable data that can represent that a piece of data already exists at a particular point in time, primarily provides a piece of electronic evidence to the user to prove the time of generation of certain data by the user.

In general, the time stamp is an encrypted document of certificates, which includes three parts, namely a summary of the document to be time stamped, a date and time when the document is received by the authentication unit, and a digital signature of the authentication unit.

In addition, the term "at least one" in the embodiments of the present application means one or more, and "a plurality" means two or more. "and/or" describes an association relationship of associated objects, meaning that there may be three relationships, e.g., A and/or B, and that there may be A alone, A and B together, and B alone, where A, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. At least one term (a) or the like, as used herein, refers to any combination of such terms, including any combination of single term (a) or plural terms (a). For example, at least one (a, b, or c) of a, b, c, a-b, a-c, b-c, or a-b-c may be represented, wherein a, b, c may be single or plural.

Unless stated to the contrary, references to "first," "second," etc. ordinal words of embodiments of the present application are used to distinguish between multiple objects, and are not used to define a sequence, timing, priority, or importance of the multiple objects.

Furthermore, the terms "comprising" and "having" in the embodiments of the application and in the claims and drawings are not exclusive. For example, a process, method, system, article, or apparatus that comprises a list of steps or modules is not limited to only those steps or modules but may include other steps or modules not listed.

By introducing the application scenario in the embodiment of the present application, a process of clock synchronization based on IEEE1588 protocol is specifically described below for the case where data format conversion is required for transmitting data.

When the embodiment of the application performs clock synchronization, the main mode is to compensate the transmission delay generated in the data format conversion process of the data into the sending time, and then perform clock synchronization according to the compensated sending time. The compensation may be performed in various ways according to the execution device, and the description will be made below.

In the embodiment of the present application, it is assumed that the data at the position a in the transmission data is used as a reference, and for convenience of description to follow, the sending time of the data sent by the first device to the second device is denoted as T1, the receiving time of the data received by the second device is denoted as T2, the transmission delay generated by performing data format conversion on the data is Δt, the data not processed in the data format is simply referred to as first data, and the data obtained by performing data format processing on the first data is simply referred to as second data.

The first device compensates the sending time T1 according to the transmission delay delta T generated in the data format conversion process of the transmission data.

As shown in fig. 4, when the performing device for compensation is a first device, the step of clock synchronization according to the present application includes:

s400, the first device transmits the first data to the conversion device, and records a transmission time T1 for transmitting the first data.

In this embodiment of the present application, the data of the position a in the transmission data is taken as a reference, so it can be understood that the transmission time T1 is specifically the time when the first device transmits the data of the position a in the first data.

Optionally, the first device may carry the first data through a sync packet, that is, the first device sends the sync packet carrying the first data to the conversion device.

S401, the conversion device performs data format conversion on the first data to generate second data.

And S402, the conversion device sends the second data to a second device.

S403, the second device receives the second data, and records a time T2 when the second data is received.

In this embodiment of the present application, the data of the position a in the transmission data is taken as a reference, so it can be understood that the receiving time T2 is specifically the time of the data of the position a in the second data received by the second device.

S404, the first device determines delay jitter delta t generated in the data format conversion process according to the first data and the second data.

Further, the first device may determine the Δt according to a data transmission rate of the first data and a data transmission rate of the second data.

The first device may determine a data transmission rate of the first data according to the first data to be transmitted, and the first device may determine a transmission rate of the second data according to a rule that the conversion device performs data conversion.

Optionally, in the embodiment of the present application, the first device may determine the transmission delay Δt according to a transmission rate of the first data and a transmission rate of the second data.

In this embodiment of the present application, because the data of the position a in the transmission data is taken as a reference, the Δt determined by the first device is a difference between the transmission time of the position a data in the first data and the transmission time of the position a data in the second data.

For example, in the embodiment of the present application, the data format conversion of the first data is implemented by using FEC technology to describe the data in detail, and it should be noted that other ways of changing the data format may be applied to the embodiment of the present application.

As shown in fig. 5, it is assumed that, during data transmission, when the first device and the second device perform data transmission, clock synchronization is performed with reference to the 3000 th bit of the transmission data. The first data format is RS (528,514), the data transmission rate based on a 100GE port is 4 x 25.78125Gbps, the second data format is RS (544,514), the data transmission rate based on a 100GE port is 4 x 26.5625Gbps, the transmission start bit of the first data and the transmission start bit of the second data are the same, for example, the first data start bit and the second data start bit are both bit0, and the delay jitter of the first data start bit and the second data start bit is 0.

The delay jitter generated by converting the data format of the 3000 th bit of the transmission data can be determined according to the following formula 2.

Δt (bitX) = (a)/Y (Gbps) - (a)/Z (Gbps) formula 2

In the above formula 2, Y (Gbps) represents a data transmission rate of the first data, Z (Gbps) represents a data transmission rate of the second data, X represents a bit used as a reference of the time stamp, a represents a bit number corresponding to 0~X bits, for example, a represents data of 1 bit length when the bit is bit0, a represents data of 2 bits length when the bit is bit1, a represents data of 3001 bit length when the bit is bit3000, and Δt represents delay jitter generated when the first data is subjected to data format conversion.

Thus, Δt (bit 3000) = (3001)/4/25.78125 Gbps- (3001)/4/26.5625 gbps=0.855 ps can be obtained based on the above formula 2.

It should be noted that, except for the above method for determining the transmission delay generated in the data format conversion process of the transmission data, any method for determining the transmission delay generated in the data format conversion process of the transmission data, which is applicable to the embodiment of the present application, belongs to the protection scope of the present application.

Further, the first device determines the direction of Δt, that is, the positive and negative of Δt, so as to determine whether delay is increased or reduced after data format processing according to the direction of Δt.

And S405, the first equipment compensates the T1 according to delta T to obtain the second time T1'.

Wherein if the Δt direction is right, that is, if the Δt is a positive value, it means that the Δt is a transmission delay increased on the basis of the first data transmission, then T1 '=t1+Δt, and if the Δt direction is left, that is, if the Δt is a negative value, it means that the Δt is a transmission delay decreased on the basis of the first data transmission, then T1' =t1- Δt.

For example, as shown in fig. 6, when the transmission data sent by the first device to the second device needs to be subjected to data format conversion, assuming that the transmission delay Δt determined by the first device is increased by 5ns, the first device sends a sync message to the second device through the conversion device at 1:00 (i.e., the T1). The second device receives the sync message at 1:15 (i.e., the T2).

The first device compensates the T1 according to the Δt to obtain the T1', i.e., the T1' =1:00+0:05=1:05.

Similarly, when the data format conversion is required for the transmission data sent by the first device to the second device, assuming that the generated transmission delay Δt is determined to be reduced by 2ns by the first device, the first device sends a sync message to the second device through the conversion device at 1:02 (i.e. T1). The second device receives the sync message at 1:00 (i.e., the T2).

The first device compensates the T1 according to the Δt to obtain the T1', i.e., the T1' =1:02-0:02=1:00.

S406, the first device sends a first message (e.g. a follow_up message) to the second device, where the first message is used to indicate the second time T1'.

Optionally, in the embodiment of the present application, the step S404 may be omitted, that is, the first device does not need to compensate the T1 according to the Δt, to obtain the second time T1'. The first device may directly send the T1 and the Δt carried in the first message to the second device, so that after the second device obtains the first message, the second device determines T1' according to the T1 and the Δt in the first message.

S407, the second device receives the first message and acquires the T1' in the first message.

Optionally, if the information carried in the first message is the T1 and the Δt, the second device determines T1' by itself according to the T1 and the Δt in the first message after obtaining the first message.

S408, the second device sends a second message (for example, delay_req message) to the first device, and records a sending time T3 of the second message.

S409, the first device receives the second message and records a time T4 when the second message is received.

S410, the first device sends a third message (e.g. delay_resp message) to the second device, where the third message includes the T4.

S411, the second device receives the third message and obtains the T4 in the third message.

S412, the second device performs clock synchronization with the first device according to the T1', T2, T3 and T4.

For example, in the embodiment of the present application, when the first device and the second device achieve time synchronization through the IEEE1588 protocol, it is necessary to determine a time difference Offset and a path transmission Delay of the first device and the second device, so that the second device achieves time synchronization with the first device according to the calculated time difference Offset and the path transmission Delay.

Wherein the second device performs the calculation according to the following equations 3 and 4:

T2—t1=offset + Delayms equation 3

T4-t3= -offset+ Delaysm equation 4

Wherein T2 in the formula 3 represents time when the second device receives the transmission data sent by the first device, T1 represents time when the first device actually sends the transmission data, offset represents time difference between devices in a communication process between the first device and the second device, and Delayms represents network path transmission delay when the first device transmits the data to the second device.

T3 in the formula 4 represents time when the second device sends the delay request message to the first device, T4 represents time when the first device receives the delay request message, -offset represents time difference between devices in a communication transmission process between the second device and the first device, and Delaysm represents network path transmission delay when the second device transmits data to the first device.

Since the transmission data to be transmitted is subjected to data format conversion, the Δt is still present, and the transmission time of the transmission data calculated by substituting the formula 3 by the second device should be the time after compensation, i.e., T1'.

After substituting the T1', T2, T3, T4 into the formula 3 and the formula 4, the second device may obtain the formula 5.

Offset= [ (T2-T1') - (T4-T3) - (Delayms-Delaysm) ]/2 equation 5

In the embodiment of the application, the T1 is compensated in advance according to the Δt, so that the interference of the Δt on the clock synchronization can be reduced when the clock synchronization is performed in the subsequent step.

For example, the Offset at the time of the existing output transmission includes Δt, see the following equation 6:

Offset= [ (T2-T1) - (T4-T3) - (Delayms + Δt-Delaysm) ]/2 equation 6

Whereas the Offset obtained by the present application is shown in the following equation 7:

Offset= [ (T2-T1') - (T4-T3) - (Delayms + Δt-Delaysm) ]/2 equation 7

Further, since T1' =t1+Δt, it can be seen from the above equation 7 that the Offset obtained by the present application is:

Offset=[(T2-T1+Δt)-(T4-T3)-(Delayms+Δt-Delaysm)]/2

=[(T2-T1)-(T4-T3)-(Delayms-Delaysm)]/2

therefore, the embodiment of the application can ensure that the second equipment accurately performs clock synchronization on the premise of ensuring no other precision loss by compensating the sending time T1.

Further, in the embodiment of the present application, when the first device transmits data to the second device, the first device transmits the data to the second device, and in the transmission process, the relative position of the Alignment Mark (AM) in the data and the data in the second data is unchanged, that is, the first device transparently transmits the data to be transmitted to the second device.

Wherein, when the transmitted data is converted into data format, the network path transmission delay mainly comprises a path delay d and a transmission delay delta t generated in the data format conversion process, when the first device passes the transmission data through to the second device, the relative position of the data at the FEC code is fixed, so the path delay d is also fixed. Therefore, in the data transmission process, only the fixed path delay d of the path transmission is needed to be determined, so that the accuracy of the clock synchronization of the first device by the second device can be effectively ensured.

It should be noted that, in the interaction flow shown in fig. 4 in the embodiment of the present application, the sequence of some steps is not limited, for example, S404 may be executed before S402.

And the execution device 2 for compensation compensates the transmission time T1 according to the transmission delay delta T generated in the data format conversion process of the data.

As shown in fig. 7, when the performing device for compensation is a second device, the step of clock synchronization according to the present application includes:

s700, the first device transmits the first data to the conversion device, and records a time T1 at which the first data is transmitted.

S701, the conversion equipment performs data format processing on the first data to generate second data.

S702, the conversion device sends the second data to a second device.

S703, the second device receives the second data and records a time T2 when the second data is received.

S704, the second device determines a transmission delay of the data of the second data record timestamp generated in the format conversion process.

Optionally, in the embodiment of the present application, after the second device acquires the second data, the first data may be determined according to a data format conversion rule of the conversion device and the second data, and then the transmission delay Δt may be determined according to the first data and the second data.

The specific manner of determining the transmission delay Δt is referred to S404, and is not described herein.

S705, the first device sends a first message (e.g. a follow_up message) to the second device, where the first message is used to indicate the T1.

S706, the second device receives the first message and acquires the T1 in the first message.

And S707, the second device compensates the T1 according to the delta T, and determines compensated T1'.

S708, the second device sends a second message (e.g. delay_req message) to the first device, and records a sending time T3 of the second message.

S709, the first device receives the second message and records a time T4 when the second message is received.

S710, the first device sends a third message (e.g. delay_resp message) to the second device, wherein the third message contains the T4.

S711, the second device receives the third message, and acquires the T4 in the third message.

S712, the second device performs clock synchronization with the first device according to the T1', T2, T3, and T4.

The specific clock synchronization method is shown in the above step S412, and will not be described herein.

It should be noted that, in the interaction flow shown in fig. 7 in the embodiment of the present application, the sequence of some steps is not limited, for example, S704 may be executed before S702.

From the foregoing description of the embodiments of the present application, it will be appreciated that, in order to achieve the above functions, each device includes a hardware structure and/or a software module that performs the corresponding functions. Those of skill in the art will readily appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is implemented as hardware or computer software driven hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

Based on the above embodiments, as shown in fig. 8, a first device for performing clock synchronization according to the present application includes a processor 800, a memory 801, and a communication interface 802.

The processor 800 is responsible for managing the bus architecture and general processing, and the memory 801 may store data used by the processor 800 in performing operations. The transceiver communication interface 802 is used to receive and transmit data in data communication with the memory 801 under the control of the processor 800.

The processor 800 may be a central processing unit (central processing unit, CPU), a network processor (network processor, NP) or a combination of CPU and NP. The processor 800 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (programmable logic device, PLD), or a combination thereof. The PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (FPGA) GATE ARRAY, generic array logic (GENERIC ARRAY logic, GAL), or any combination thereof. The memory 701 may include a usb disk, a removable hard disk, a read-only memory (ROM), a random access memory (random access memory, RAM), a magnetic disk, or an optical disk, etc. various media that may store program codes.

The processor 800, the memory 801 and the communication interface 802 are interconnected. Alternatively, the processor 800, the memory 801, and the communication interface 802 may be interconnected via a bus 803. The bus 803 may be a peripheral component interconnect standard (PERIPHERAL COMPONENT INTERCONNECT, PCI) bus or an extended industry standard architecture (extended industry standard architecture, EISA) bus, etc. The buses may be classified as address buses, data buses, control buses, etc. For ease of illustration, only one thick line is shown in fig. 8, but not only one bus or one type of bus.

Specifically, the processor 800 is configured to read a program in the memory 801 and execute:

The method comprises the steps of obtaining first data, marking a time stamp in the first data, determining the data position of the data corresponding to the time stamp in the first data, sending first time of the data corresponding to the time stamp, determining transmission delay generated in a format conversion process of the data position according to the data position, sending first information to second equipment, wherein the first information is used for indicating second time, the second time is time after the first time is compensated according to the transmission delay, receiving second information sent by the second equipment at third time, and sending third information to the second equipment, wherein the third information comprises the third time, so that the second equipment performs clock synchronization with the first equipment according to the second time, the third time and fourth time for sending the second information.

In one possible implementation method, the first message includes the first time and the transmission delay, so that the second device compensates the first time according to the transmission delay to obtain a second time, or the first message includes the second time.

In one possible implementation method, the relative positions of the alignment marks in the second data and the data in the second data are unchanged during the transmission process of the second data.

As shown in fig. 9, the present invention provides a first device for clock synchronization, the device comprising a processing unit 900 and a communication unit 901:

The communication unit 901 is configured to send the first data;

the processing unit 900 is configured to mark a time stamp in the first data, determine a data position of the data corresponding to the time stamp in the first data, and send a first time of the data corresponding to the time stamp;

The communication unit 901 is configured to send a first message to the second device, where the first message is used to indicate a second time, where the second time is a time after the first time is compensated according to the transmission delay, receive the second message sent by the second device at a third time, and send a third message to the second device, where the third message includes the third time, so that the second device performs clock synchronization with the first device according to the second time, the third time, and a fourth time when the second message is sent.

As shown in fig. 10, an embodiment of the present application further provides a second device for clock synchronization, the device comprising a processor 1000, a memory 1001 and a communication interface 1002.

The processor 1000 is responsible for managing the bus architecture and general processing, and the memory 1001 may store data used by the processor 1000 in performing operations. The transceiver communication interface 1002 is for receiving and transmitting data in data communication with the memory 1001 under the control of the processor 1000.

The processor 1000 may be a central processing unit (central processing unit, CPU), a network processor (network processor, NP) or a combination of CPU and NP. The processor 1000 may further comprise a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (programmable logic device, PLD), or a combination thereof. The PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (FPGA) GATE ARRAY, generic array logic (GENERIC ARRAY logic, GAL), or any combination thereof. The memory 1001 may include a usb disk, a removable hard disk, a read-only memory (ROM), a random access memory (random access memory, RAM), a magnetic disk, or an optical disk, etc. various media that may store program codes.

The processor 1000, the memory 1001 and the communication interface 1002 are connected to each other. Alternatively, the processor 1000, the memory 1001, and the communication interface 1002 may be connected to each other through a bus 1003, and the bus 1003 may be a peripheral component interconnect standard (PERIPHERAL COMPONENT INTERCONNECT, PCI) bus or an extended industry standard architecture (extended industry standard architecture, EISA) bus, or the like. The buses may be classified as address buses, data buses, control buses, etc. For ease of illustration, only one thick line is shown in fig. 10, but not only one bus or one type of bus.

Specifically, the processor 1000 is configured to read a program in the memory 1001 and execute:

The method comprises the steps of receiving second data sent by conversion equipment, receiving first information sent by first equipment, wherein the first information is used for indicating second time, the second time is time after first time is compensated according to transmission delay, the transmission delay is generated in a format conversion process of time-stamped data in the first data, the first time is the sending time of the data corresponding to the time stamp sent by the first equipment, the second information is sent to the first equipment at fourth time, the second equipment receives third information sent by the first equipment, the third information comprises third time when the second information is received by the first equipment, and clock synchronization with the first equipment is carried out according to the second time, the third time and the fourth time.

In one possible implementation, the processor 1000 is further configured to:

The second device determines the second time according to the transmission delay and the first time contained in the first message.

As shown in fig. 11, the present invention provides a second apparatus for clock synchronization, the apparatus including a processing unit 1100 and a communication unit 1101:

The communication unit 1101 is configured to receive second data sent by a conversion device, receive a first message sent by the first device, where the first message is used to indicate a second time, the second time is a time after compensating a first time according to a transmission delay, where the transmission delay is generated in a format conversion process of time-stamped data in the first data, and the first time is a sending time of the first device to send data corresponding to the time stamp;

The processing unit 1100 is configured to perform clock synchronization with the first device according to the second time, the third time, and the fourth time.

As shown in fig. 12, an embodiment of the present application also provides another clock-synchronized second device comprising a processor 1200, a memory 1201 and a communication interface 1202.

The processor 1200 is responsible for managing the bus architecture and general processing, and the memory 1201 may store data used by the processor 1200 in performing operations. The transceiver communication interface 1202 is for receiving and transmitting data in data communication with the memory 1201 under the control of the processor 1200.

The processor 1200 may be a central processing unit (central processing unit, CPU), a network processor (network processor, NP) or a combination of CPU and NP. The processor 1200 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (programmable logic device, PLD), or a combination thereof. The PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (FPGA) GATE ARRAY, generic array logic (GENERIC ARRAY logic, GAL), or any combination thereof. The memory 1201 may include a U disk, a removable hard disk, a read-only memory (ROM), a random access memory (random access memory, RAM), a magnetic disk or an optical disk, etc. various media in which program codes may be stored.

The processor 1200, the memory 1201 and the communication interface 1202 are interconnected. Alternatively, the processor 1200, the memory 1201, and the communication interface 1202 may be interconnected by a bus 1203, where the bus 1203 may be a peripheral component interconnect standard (PERIPHERAL COMPONENT INTERCONNECT, PCI) bus or an extended industry standard architecture (extended industry standard architecture, EISA) bus, etc. The buses may be classified as address buses, data buses, control buses, etc. For ease of illustration, only one thick line is shown in fig. 12, but not only one bus or one type of bus.

Specifically, the processor 1200 is configured to read a program in the memory 1201 and execute:

The method comprises the steps of receiving second data sent by conversion equipment, determining transmission delay generated in a format conversion process of time stamped data in the second data, receiving first information sent by first equipment, sending second information to the first equipment at fourth time, receiving third information sent by the first equipment, wherein the third information comprises third time when the first equipment receives the second information, and carrying out clock synchronization with the first equipment according to the first time, the transmission delay, the third time and the fourth time.

In one possible implementation, the processor 1200 is further configured to:

The second device compensates the first time according to the transmission delay to obtain a second time, and the second device performs clock synchronization with the first device according to the second time, the third time and the fourth time.

As shown in fig. 13, another clock synchronization first device provided by the present invention includes a processing unit 1300 and a communication unit 1301:

The communication unit 1301 is configured to receive second data sent by the conversion device;

The processing unit 1300 is configured to determine a transmission delay generated in a format conversion process of the time-stamped data in the second data;

The communication unit 1301 is configured to receive a first message sent by the first device, where the first message includes the first time, send a second message to the first device at a fourth time, receive a third message sent by the first device, where the third message includes a third time when the first device receives the second message, and perform clock synchronization with the first device according to the first time, the transmission delay, the third time, and the fourth time.

In some possible implementations, aspects of the clock synchronization method provided by the embodiments of the present invention may also be implemented in the form of a program product including program code for causing a computer device to perform the steps of the clock synchronization method according to the various exemplary embodiments of the present invention as described herein, when the program code is run on the computer device.

The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. Examples (a non-exhaustive list) of one implementation of the more inventive embodiments of the readable storage medium include an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

A program product for clock synchronization according to an embodiment of the present invention may employ a portable compact disc read-only memory (CD-ROM) and include program code and may run on a server device. However, the program product of the present invention is not limited thereto, and in this document, a readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an information transmission, apparatus, or device.

The readable signal medium may include a data signal propagated in baseband or as part of a carrier wave with readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. The readable signal medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with a periodic network action system, apparatus, or device.

Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Program code for carrying out operations of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server. In the case of remote computing devices, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device.

The embodiment of the application also provides a computer readable storage medium for the clock synchronization method, namely, the content is not lost after power failure. The storage medium has stored therein a software program comprising program code which, when executed on a computing device, when read and executed by one or more processors, implements any of the above aspects of clock synchronization of embodiments of the application.

The present application is described above with reference to block diagrams and/or flowchart illustrations of methods, apparatus (systems) and/or computer program products according to embodiments of the application. It will be understood that one block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, and/or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer and/or other programmable data processing apparatus, create means for implementing the functions/acts specified in the block diagrams and/or flowchart block or blocks.

Accordingly, the present application may be embodied in hardware and/or in software (including firmware, resident software, micro-code, etc.). Still further, the present application may take the form of a computer program product on a computer-usable or computer-readable storage medium having computer-usable or computer-readable program code embodied in the medium for use by or in connection with an instruction execution system. In the context of the present application, a computer-usable or computer-readable medium may be any medium that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.

Although the application has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the application. Accordingly, the specification and drawings are merely exemplary illustrations of the present application as defined in the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the application. It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A method for clock synchronization, which is used in a network environment composed of a first device, a conversion device and a second device, wherein the conversion device is used for obtaining second data after format conversion of first data of the first device and sending the second data to the second device, and the method is characterized in that the method comprises the following steps:

The first device sends the first data, marks a time stamp in the first data, determines the data position of the data corresponding to the time stamp in the first data, and sends the first time of the data corresponding to the time stamp;

the first device determines transmission delay generated in the format conversion process of the data position according to the data position;

the first device sends a first message to the second device, wherein the first message is used for indicating a second time, and the second time is the time after the first time is compensated according to the transmission delay;

The first device receives a second message sent by the second device at a third time;

The first device sends a third message to the second device, wherein the third message comprises the third time, so that the second device performs clock synchronization with the first device according to the second time, the third time and a fourth time for sending the second message;

The first device determines transmission delay generated in the format conversion process of the data position according to the data position, and the method comprises the following steps:

And the first equipment determines the transmission delay generated in the format conversion process of the data position according to the data transmission rate of the first data and the data transmission rate of the second data.

2. The method of claim 1, wherein the first message is used to indicate a second time, comprising:

the first message contains the first time and the transmission delay, so that the second device compensates the first time according to the transmission delay to obtain a second time, or

The first message includes the second time.

3. The method according to claim 1 or 2, wherein the first message is a follow-up message, the second message is a Delay request delay_req message, and the third message is a Delay response delay_resp message.

4. A method according to claim 1 or 2, wherein the alignment mark in the second data is unchanged from the data relative to the second data during transmission.

5. A method for clock synchronization, which is used in a network environment composed of a first device, a conversion device and a second device, wherein the conversion device is used for obtaining second data after format conversion of first data of the first device and sending the second data to the second device, and the method is characterized in that the method comprises the following steps:

The second device receives second data sent by the conversion device;

the second device receives a first message sent by the first device, wherein the first message is used for indicating a second time, the second time is the time after the first time is compensated according to a transmission delay, the transmission delay is generated in the format conversion process of time-stamped data in the first data, the transmission delay is determined by the data transmission rate of the first data and the data transmission rate of the second data, and the first time is the sending time of the data corresponding to the time stamp sent by the first device;

the second device sending a second message to the first device at a fourth time;

The second device receives a third message sent by the first device, wherein the third message comprises a third time when the first device receives the second message;

the second device performs clock synchronization with the first device according to the second time, the third time and the fourth time.

6. The method of claim 5, wherein the second device further comprises, prior to synchronizing the clock with the first device based on the second time, the third time, and the fourth time:

7. The method of claim 5 or 6, wherein the first message is a follow-up message, the second message is a Delay request delay_req message, and the third message is a Delay response delay_resp message.

8. The method of claim 5 or 6, wherein the alignment mark in the second data is unchanged from the data relative to the second data during the transmission of the second data.

9. A method for clock synchronization, which is used in a network environment composed of a first device, a conversion device and a second device, wherein the conversion device is used for obtaining second data after format conversion of first data of the first device and sending the second data to the second device, and the method is characterized in that the method comprises the following steps:

The second device receives second data sent by the conversion device;

the second device determines transmission delay generated in the format conversion process of the data marked with the time stamp in the second data;

The second device receives a first message sent by the first device, wherein the first message comprises a first time, and the first time is the sending time of the data corresponding to the timestamp sent by the first device;

the second device performs clock synchronization with the first device according to the first time, the transmission delay, the third time and the fourth time;

The second device determining a transmission delay generated in a format conversion process of time-stamped data in the second data, including:

and the second equipment determines the transmission delay generated in the format conversion process of the data marked with the time stamp in the second data according to the data transmission rate of the first data and the data transmission rate of the second data.

10. The method of claim 9, wherein the second device performs clock synchronization with the first device according to the first time, the transmission delay, the third time, and the fourth time, comprising:

the second equipment compensates the first time according to the transmission delay to obtain a second time;

11. The method according to claim 9 or 10, wherein the first message is a follow-up message, the second message is a Delay request delay_req message, and the third message is a Delay response delay_resp message.

12. A method according to claim 9 or 10, wherein the alignment mark in the second data is unchanged from the data relative to the second data during transmission.

13. A communication device is characterized by comprising a processing unit and a communication unit;

the communication unit is used for sending first data;

The communication unit is configured to send a first message to a second device, where the first message is used to indicate a second time, and the second time is a time after the first time is compensated according to the transmission delay; transmitting a third message to the second device, wherein the third message comprises the third time, so that the second device performs clock synchronization with the first device according to the second time, the third time and a fourth time for transmitting the second message;

the processing unit is specifically configured to:

And determining transmission delay generated in the format conversion process of the data position according to the data transmission rate of the first data and the data transmission rate of the second data, wherein the second data is obtained after the format conversion of the first data by the conversion equipment.

14. A communication device is characterized by comprising a processing unit and a communication unit;

The communication unit is used for receiving second data sent by conversion equipment, receiving first information sent by first equipment, wherein the first information is used for indicating second time, the second time is time after first time is compensated according to transmission delay, the transmission delay is generated in a format conversion process of time-stamped data in the first data, the transmission delay is determined by the data transmission rate of the first data and the data transmission rate of the second data, the first time is the sending time of the data corresponding to the time stamp sent by the first equipment, the second information is sent to the first equipment at fourth time, and the third information sent by the first equipment is received, wherein the third information comprises third time when the second information is received by the first equipment;

15. A communication device is characterized by comprising a processing unit and a communication unit;

The communication unit is used for receiving a first message sent by first equipment, wherein the first message comprises a first time, the first time is the sending time of data corresponding to the timestamp sent by the first equipment, sending a second message to the first equipment at a fourth time, receiving a third message sent by the first equipment, the third message comprises a third time when the second message is received by the first equipment, and performing clock synchronization with the first equipment according to the first time, the transmission delay, the third time and the fourth time;

the processing unit is specifically configured to:

According to the data transmission rate of the first data, the data transmission rate of the second data is determined, the transmission delay generated in the format conversion process of the data marked with the time stamp in the second data is obtained after the format conversion of the first data sent by the first device through the conversion device.

16. A communication device comprising one or more processors, memory, one or more programs, wherein the one or more programs are stored in the memory, the one or more programs comprising instructions, which when executed by the processor, cause the communication device to perform the method of any of claims 1-4.

17. A communication device comprising one or more processors, memory, one or more programs, wherein the one or more programs are stored in the memory, the one or more programs comprising instructions, which when executed by the processor, cause the communication device to perform the method of any of claims 5-12.

18. A clock synchronization system is characterized by comprising a first device, a second device and a conversion device;

The first device being configured to perform the method of any one of claims 1-4;

The second device being configured to perform the method of any one of claims 5 to 12;

The conversion device is configured to convert the first data of the first device into second data, and send the second data to the second device.

19. A computer readable storage medium comprising computer instructions which, when run on a first device, cause the first device to perform the method of any of claims 1-4.

20. A computer readable storage medium comprising computer instructions which, when run on a second device, cause the second device to perform the method of any of claims 5-12.