CN114749359B - Signal generating circuit and ultrasonic fingerprint identification device - Google Patents
Signal generating circuit and ultrasonic fingerprint identification device Download PDFInfo
- Publication number
- CN114749359B CN114749359B CN202210665485.0A CN202210665485A CN114749359B CN 114749359 B CN114749359 B CN 114749359B CN 202210665485 A CN202210665485 A CN 202210665485A CN 114749359 B CN114749359 B CN 114749359B
- Authority
- CN
- China
- Prior art keywords
- transistor
- voltage
- gate driver
- circuit
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000013016 damping Methods 0.000 claims abstract description 51
- 239000003990 capacitor Substances 0.000 claims description 63
- 238000010586 diagram Methods 0.000 description 16
- 238000000034 method Methods 0.000 description 7
- 230000010355 oscillation Effects 0.000 description 7
- 230000008859 change Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
- 238000005859 coupling reaction Methods 0.000 description 5
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910000831 Steel Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000010959 steel Substances 0.000 description 2
- 238000007599 discharging Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000003909 pattern recognition Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
- B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
- B06B1/00—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
- B06B1/02—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy
- B06B1/0207—Driving circuits
- B06B1/0223—Driving circuits for generating signals continuous in time
- B06B1/0269—Driving circuits for generating signals continuous in time for generating multiple frequencies
- B06B1/0276—Driving circuits for generating signals continuous in time for generating multiple frequencies with simultaneous generation, e.g. with modulation, harmonics
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Engineering & Computer Science (AREA)
- Mechanical Engineering (AREA)
- Image Input (AREA)
- Electronic Switches (AREA)
Abstract
The application provides a signal generating circuit and an ultrasonic fingerprint identification device, which can improve the residual vibration of generated sine wave signals. The signal generating circuit includes: a resonant circuit for generating a sine wave signal; the control circuit is used for generating the pulse signal, and the pulse signal is used for driving the resonance circuit to generate the sine wave signal; and the brake circuit comprises a damping resistor, the damping resistor is connected between the resonant circuit and the control circuit, and the damping resistor is used for absorbing redundant signal energy generated by the resonant circuit after the control circuit stops generating the preset duration of the pulse signal.
Description
Technical Field
The embodiment of the application relates to the field of circuits, in particular to a signal generating circuit and an ultrasonic fingerprint identification device.
Background
In the field of electronic communications and sensors, sinusoidal signals are often used. When the amplitude of the required sine wave signal is high and the frequency of the sine wave signal is required to be adjustable, the sine wave signal can be generated by utilizing a resonant circuit. However, when the output of the sine wave signal needs to be stopped, the energy on the resonant circuit does not stop immediately, but slowly decreases to zero in a free resonance manner, so that so-called "ringing" occurs. Therefore, how to improve the residual oscillation of the sine wave signal is called the problem to be solved urgently.
Disclosure of Invention
The embodiment of the application provides a signal generating circuit and an ultrasonic fingerprint identification device, which can improve the residual vibration of generated sine wave signals.
In a first aspect, a signal generating circuit is provided, including: a resonant circuit for generating a sine wave signal; the control circuit is used for generating a pulse signal, and the pulse signal is used for driving the resonance circuit to generate the sine wave signal; and the brake circuit comprises a damping resistor, the damping resistor is connected between the resonant circuit and the control circuit, and the damping resistor is used for absorbing redundant signal energy generated by the resonant circuit after the control circuit stops generating the preset duration of the pulse signal.
In the embodiment of the application, the signal generating circuit comprises a resonant circuit, a control circuit and a brake circuit, wherein the control circuit is used for generating a pulse signal so as to drive the resonant circuit to generate a sine wave signal through the pulse signal. The brake circuit comprises a damping resistor, wherein the damping resistor is connected between the resonant circuit and the control circuit so as to absorb redundant signal energy generated by the resonant circuit when the resonant circuit is expected to stop outputting the sine wave signal, thereby improving the residual vibration of the sine wave signal output by the resonant circuit and improving the quality of the sine wave signal.
In one implementation manner, the resonant circuit includes an inductor and a first capacitor connected in series, one end of the inductor is connected to the first capacitor through a first resistor, and the other end of the inductor is connected to the damping resistor, wherein a resistance of the damping resistorR0And the resistance value of the first resistorR1Satisfies the following conditions:R1+R0=1.4*Z，Zis the characteristic impedance of the resonance circuit,
，LandCthe values of the inductance and the first capacitance, respectively. Therefore, when the control circuit controls the resonance circuit to stop outputting the sine wave signal, redundant signal energy generated by the resonance circuit can be quickly zeroed, and the brake circuit achieves the optimal brake effect.
In one form of implementation, the first and second electrodes are,R0at 0.8%ZTo 2ZIn the meantime.
In one implementation, the brake circuit further includes a third switch module connected in parallel with the damping resistor, and the third switch module is configured to be turned on when the control circuit generates the pulse signal and turned off after the control circuit stops generating the pulse signal for a preset time.
In the embodiment, the third switch module is arranged in parallel with the damping resistor in the brake circuit, and the third switch module is conducted when the control circuit generates a pulse signal so as to short-circuit the damping resistor, so that the generated sine wave signal cannot be influenced; the third switch module is disconnected when the resonant circuit is expected to stop outputting the sine wave signal, so that the damping resistor is connected with the resonant circuit, and redundant signal energy generated by the resonant circuit is absorbed. Therefore, residual oscillation of the sine wave signal is effectively improved, and the circuit has the characteristics of simple structure, small size and low power consumption.
In one implementation, the control circuit includes a first switch module and a second switch module, the first switch module is connected between a power supply and the damping resistor, the second switch module is connected between the damping resistor and ground, and the first switch module and the second switch module are alternately turned on to generate the pulse signal.
In one implementation, the first switch module includes a first transistor and a first gate driver connected to the first transistor, the second switch module includes a second transistor and a second gate driver connected to the second transistor, and the third switch module includes a third transistor and a third gate driver connected to the third transistor. For example, the first transistor is one of an NMOS transistor and a PMOS transistor, the second transistor is an NMOS transistor, and the third transistor is one of an NMOS transistor and a PMOS transistor.
In this embodiment, the functions of the switch modules are implemented by using transistors such as NMOS transistors and PMOS transistors and using corresponding gate drivers as their driving circuits, which is easy to operate and low in cost.
In one implementation, the first transistor and the third transistor are NMOS transistors, the damping resistor is connected in parallel with the third transistor, a source of the first transistor, a drain of the second transistor and a source of the third transistor are connected, a gate of the first transistor, a gate of the second transistor and a gate of the third transistor are respectively connected to an output terminal of the first gate driver, an output terminal of the second gate driver and an output terminal of the third gate driver, a source of the second transistor is grounded, a drain of the first transistor is connected to a first voltage, and a drain of the third transistor is connected to the resonant circuit.
In this embodiment, when the first transistor, the second transistor, and the third transistor are all NMOS transistors, the connection between the control circuit and the brake circuit is simple, and the complexity of the signal generating circuit is reduced. The first transistor and the second transistor are alternately turned on under the control of the first gate driver and the second gate driver to generate a pulse signal to drive the resonant circuit to output a sine wave signal, and meanwhile, when the first transistor and the second transistor are alternately turned on, the third transistor needs to be kept on under the control of the third gate driver.
In one implementation, the control circuit further includes a diode and a second capacitor, where a connection point between the source of the first transistor, the drain of the second transistor, and the source of the third transistor is connected to the first power terminal of the first gate driver, the first power terminal of the third gate driver, and the first terminal of the second capacitor, the second power terminal of the first gate driver, the second power terminal of the third gate driver, and the second terminal of the second capacitor are connected to the output terminal of the diode, the input terminal of the diode and the second power terminal of the second gate driver are connected to a second voltage, the first power terminal of the second gate driver is grounded, and the second voltage is smaller than the first voltage.
In this embodiment, in order to maintain the third transistor in the on state when the first transistor and the second transistor are alternately turned on, a diode and a second capacitor connected to the first switch module and the third switch module are provided in the control circuit, so that the on state of the third transistor is maintained by using the characteristic that the voltage across the second capacitor cannot change abruptly.
In one implementation, the first voltage is a power supply voltage, and the second voltage is a turn-on voltage of the NMOS transistor.
In one implementation, the first voltage is between 3V and 36V, and the second voltage is between 2V and 5V.
In one implementation, the first transistor and the third transistor are PMOS transistors, the damping resistor is connected in parallel with the third transistor, a drain of the first transistor, a drain of the second transistor and a drain of the third transistor are connected, a gate of the first transistor, a gate of the second transistor and a gate of the third transistor are respectively connected to an output terminal of the first gate driver, an output terminal of the second gate driver and an output terminal of the third gate driver, a source of the second transistor is grounded, a source of the first transistor is connected to a first voltage, and a source of the third transistor is connected to the resonant circuit.
In this embodiment, when the first transistor and the third transistor are PMOS transistors and the second transistor is an NMOS transistor, the connection between the control circuit and the brake circuit is simple, which reduces the complexity of the signal generating circuit. The first transistor and the second transistor are alternately turned on under the control of the first gate driver and the second gate driver to generate a pulse signal to drive the resonant circuit to output a sine wave signal, and meanwhile, when the first transistor and the second transistor are alternately turned on, the third transistor needs to be kept on under the control of the third gate driver.
In one implementation, the control circuit further includes a diode and a second capacitor, wherein a source of the third transistor is connected to the first power terminal of the third gate driver and the first terminal of the second capacitor, the second power terminal of the third gate driver is connected to the second terminal of the second capacitor and the input terminal of the diode, an output terminal of the diode and the second power terminal of the first gate driver are connected to a third voltage, a source of the first transistor is connected to the first power terminal of the first gate driver, the first power terminal of the second gate driver is connected to the second voltage, and the second power terminal of the second gate driver is grounded.
In this embodiment, in order to maintain the third transistor in the on state when the first transistor and the second transistor are alternately turned on, a diode and a second capacitor connected to the third switching module are provided in the control circuit, so that the on state of the third transistor is maintained by using the characteristic that the voltage across the second capacitor cannot change abruptly.
In one implementation, the control circuit further includes a second resistor connected in parallel with the second capacitor, and the second resistor is configured to discharge the second capacitor to reduce a voltage boost of the second capacitor caused by an inductance in the resonant circuit.
When the second capacitor is connected with the inductor in the resonant circuit, the second capacitor can absorb the energy of the inductor in the braking process, the voltage of the inductor can be continuously increased, and the second resistor is connected with the two ends of the second capacitor in parallel and can discharge the second capacitor, so that the voltage of the second capacitor is reduced, and the safety of the circuit is improved.
In one implementation, the first voltage is a power voltage, the second voltage is a turn-on voltage of the NMOS, and the third voltage is a difference between the first voltage and an absolute value of a turn-on voltage of the PMOS transistor.
In one implementation, the first voltage is between 3V and 36V, the second voltage is between 2V and 5V, the third voltage is 2V to 5V smaller than the first voltage, and the turn-on voltage of the PMOS transistor is between-2V and-5V.
In a second aspect, an ultrasonic fingerprint identification device is provided, which includes: an ultrasonic transducer; and the signal generating circuit in the first aspect or any implementation manner of the first aspect, wherein the sine wave signal output by the signal generating circuit is used for driving the ultrasonic transducer to generate an ultrasonic signal for fingerprint identification.
Drawings
Fig. 1 is a schematic diagram of a sine wave signal.
Fig. 2 is a schematic diagram of a conventional signal generating circuit.
Fig. 3 is a schematic diagram of the switching timing of the signal generation circuit shown in fig. 2 and the waveform of a sine wave signal.
Fig. 4 is a waveform diagram of a sine wave signal and switching timing when aftervibration shown in fig. 3 is eliminated by using an inversion pulse.
Fig. 5 is a schematic block diagram of a signal generation circuit of an embodiment of the present application.
Fig. 6 is a schematic diagram of a possible specific implementation of a brake circuit in the signal generating circuit shown in fig. 5.
Fig. 7 is a schematic diagram of the switching timing of the signal generation circuit shown in fig. 5 and the waveform of a sine wave signal.
Fig. 8 is a schematic diagram of one possible implementation of the signal generating circuit shown in fig. 5.
Fig. 9 is a schematic diagram of one possible implementation of the signal generating circuit shown in fig. 5.
FIG. 10 is a schematic block diagram of an ultrasonic fingerprint identification device according to an embodiment of the present application.
Fig. 11 is a schematic diagram of the signal generating circuit shown in fig. 8 applied to an ultrasonic fingerprint identification device.
Detailed Description
The technical solution in the present application will be described below with reference to the accompanying drawings.
In the field of electronic communications and sensors, sinusoidal signals, such as that shown in fig. 1, are often used. When the required sine wave signal has a high amplitude and a tunable frequency, the signal generating circuit 100 shown in fig. 2 can be generally used to generate the sine wave signal.
As shown in fig. 2, the signal generating circuit 100 includes a resonance circuit 110, and a control circuit 120 connected to the resonance circuit 110. The control circuit 120 is used for generating a pulse signal to drive the resonant circuit 110 to generate a sine wave signal V TX 。
The resonant circuit 100 is an LC series resonant circuit composed of an inductor L, a resistor R and a capacitor C, and has a resonant frequency
In the formulaLAndCrespectively representing the magnitudes of the inductance L and the capacitance C.
The control circuit 120 includes a first switch S1 and a second switch S2, and the first switch S1 and the second switch S2 and their driving circuits form a half bridge circuit. The control signal and the signal waveform of the position SW are the same. The high level at SW is HV and the low level is ground. Frequency of control signal and resonance frequencyfApproach to make the two ends of the capacitor C resonate to generate a high-voltage sine wave signal V TX 。
As shown in fig. 3When the control signal is at a high level, the first switch S1 is turned on, and the second switch S2 is turned on; when the control signal is low, the first switch S1 is closed, and the second switch S2 is turned on. The signal generating circuit 100 has a problem of off delay, and a sine wave signal V is expected to be output after the control signal is kept at a low level TX And at the same time disappear. However, in practice, the energy of the oscillation of the resonant circuit cannot be dissipated immediately, but slowly decreases to zero in a resonant manner, called "ringing", at a rate related to the value of the resistance R.
In order to improve the residual oscillation of the sine wave signal, an inverted driving method may be adopted, that is, an inverted pulse signal is added after the control signal keeps a low level, so as to accelerate the return of the resonant energy of the resonant circuit to zero. As shown in fig. 4, in the case of increasing the inverted drive signal, the ringing of the sine wave signal is significantly reduced.
However, even when the inverted driving signal is added, the residual oscillation of the sine wave signal cannot be effectively eliminated. Therefore, the signal generating circuit provided by the application can effectively improve the residual oscillation of the sine wave signal and improve the quality of the sine wave signal, and has the characteristics of simple structure, small size and low power consumption.
Fig. 5 shows a schematic block diagram of a signal generating circuit of an embodiment of the present application. As shown in fig. 5, the signal generating circuit 200 includes a resonant circuit 210, a brake circuit 220, and a control circuit 230.
The resonant circuit 210 is used to generate a sine wave signal. The control circuit 230 is used to generate a pulse signal, which is used to drive the resonant circuit 210 to generate a sine wave signal. The brake circuit 110 includes a damping resistor R0, the damping resistor R0 is connected between the resonant circuit 210 and the control circuit 230, and the damping resistor R0 is used for absorbing the excessive signal energy generated by the resonant circuit 210 after the control circuit 230 stops generating the pulse signal for a preset time.
In the embodiment of the present application, the signal generating circuit 200 further includes a brake circuit 220 in addition to the resonant circuit 210 and the control circuit 230, the brake circuit 220 includes a damping resistor R0, and the damping resistor R0 is connected between the resonant circuit 210 and the control circuit 230 to absorb the excessive signal energy generated by the resonant circuit 210 when the resonant circuit 210 is expected to stop outputting the sine wave signal, so as to improve the residual oscillation of the sine wave signal output by the resonant circuit 210 and improve the quality of the sine wave signal.
The resonant circuit 210 includes an inductor L and a first capacitor C1 connected in series, one end of the inductor L is connected to the first capacitor C1 through a first resistor R1, and the other end of the inductor L is connected to a damping resistor R0. The brake circuit 220 absorbs the excessive signal energy generated by the resonant circuit 210 through the damping resistor R0, and the "braking" effect is related to the magnitude of the damping resistor R0.
To achieve the best "braking" effect for the braking circuit 220, in one implementation, the damping resistor R0 has a resistance valueR0And the resistance value of the first resistor R1R1Satisfies the following conditions:R1+R0=1.4*Z，Zis the characteristic impedance of the resonant circuit 210,
，LandCthe values of the inductance L and the first capacitance C1, respectively. The damping resistor R0 may be located between 0.8 × Z and 2 × Z, for example. Thereby enabling the excessive signal energy generated by the resonant circuit 210 to be rapidly zeroed when the control circuit 230 controls the resonant circuit 210 to stop outputting the sine wave signal.
In one implementation, the control circuit 230 includes a first switch module connected between the power supply and the damping resistor R0 and a second switch module connected between the damping resistor R0 and ground, the first switch module and the second switch module being configured to alternately conduct to generate the pulse signal. Therefore, the first switch module and the second switch module are alternately conducted to generate pulse signals to drive the resonant circuit to output sine wave signals, and the circuit has the characteristics of simple structure, small size and low power consumption.
In one implementation, the brake circuit 220 further includes a third switching module connected in parallel with the damping resistor R0, and the third switching module is configured to be turned on when the control circuit 230 generates the pulse signal and turned off when the control circuit stops generating the pulse signal.
For example, as shown in fig. 6, the first switch module includes a first switch S1 and a driving circuit 231 thereof, the second switch module includes a second switch S2 and a driving circuit 232 thereof, and the third switch module includes a third switch S3 and a driving circuit 221 thereof. The third switch S3 is connected in parallel with the damping resistor R0. The control signal is used for controlling the on and off of the first switch S1 and the second switch S2, and the brake signal is used for controlling the on and off of S3. As shown in the timing diagram of fig. 7, when the resonant circuit 210 is in the resonant state, the third switch S3 is controlled to be turned on, and the resonant circuit 210 generates the high-voltage sine wave signal V TX (ii) a When a sine wave signal V is desired TX When the fast zero return is completed, the third switch S3 is controlled to be opened, the damping resistor R0 is connected with the resonant circuit 220 in series, and when the resistance value of the damping resistor R0 is reducedR0When the characteristic impedance of the resonant circuit 210 is close to the characteristic impedance, the resonant energy of the resonant circuit 220 returns to zero rapidly according to the rule of LC resonance, and the sine wave signal V is realized TX The voltage of (c) is rapidly returned to zero. When the sine wave signal V TX After the voltage of the third switch S3 is reset to zero, the state of the third switch is positive sine wave signal V TX Has no effect on the waveform of (2).
Generally, the third switch S3 may be controlled to be turned off after the preset time period T0 for which the control circuit 230 stops generating the pulse signal, that is, the time period T0 elapses after the control circuit 230 stops generating the pulse signal. For example, T0 ≧ T/2, T is the resonant period of the resonant circuit 210, T =1 ≧f，
. For example, as shown in fig. 7, there is a time delay T0 between the time when the third switch S3 is turned OFF, i.e., the start time of the OFF period, and the end time of the control signal/SW.
It can be seen that the third switch is arranged in parallel with the damping resistor R0 in the brake circuit 220, and the third switch module is turned on when the control circuit 230 generates a pulse signal to short-circuit the damping resistor R0, so that the generated sine wave signal V is not affected by the third switch module TX Causing an impact; the third switch module is opened when it is desired that the resonant circuit 210 stops outputting the sine wave signal to switch the damping resistor R0 in to connect it to the resonant circuit 210 to absorb the resonant circuit210, and excess signal energy. Thereby effectively improving the sine wave signal V TX The residual vibration has the characteristics of simple circuit structure, small size and low power consumption.
In one implementation, the first switch module includes a first transistor Q1 and a first Gate Driver (GD) 231 connected to the first transistor Q1, the second switch module includes a second transistor Q2 and a second Gate Driver 232 connected to the second transistor Q2, and the third switch module includes a third transistor Q3 and a third Gate Driver 221 connected to the third transistor Q3. That is, the first switch S1, the second switch S2, and the third switch S3 described above may be implemented by transistors, and accordingly, a driving circuit thereof may be a gate driver. For example, the first transistor Q1 is one of an NMOS transistor and a PMOS transistor, the second transistor Q2 is one of an NMOS transistor and a PMOS transistor, and the third transistor Q3 is one of an NMOS transistor and a PMOS transistor. The functions of the switch modules are realized by adopting transistors such as NMOS (N-channel metal oxide semiconductor) transistors and PMOS (P-channel metal oxide semiconductor) transistors and adopting corresponding gate drivers as driving circuits of the transistors, so that the switch modules are easy to operate and low in cost.
Two possible implementations of the signal generating circuit 200 provided in the embodiment of the present application are described below by taking fig. 8 and fig. 9 as examples. In embodiment 1, the first transistor Q1 and the third transistor Q3 are both NMOS transistors, and the second transistor Q2 is an NMOS transistor. In embodiment 2, the first transistor Q1 and the third transistor Q3 are both PMOS transistors, and the second transistor Q2 is an NMOS transistor. Embodiments 1 and 2 exemplify the case where the first transistor Q1 and the third transistor Q3 are both PMOS transistors or the first transistor Q1 and the third transistor Q3 are both PMOS transistors and NMOS transistors, because the circuit structure of the signal generating circuit 200 constructed in this way is simple, and the complexity of the signal generating circuit 200 is reduced. Of course, in practical applications, the first transistor Q1 and the third transistor Q3 may also be different types of transistors, for example, the first transistor Q1 is one of an NMOS transistor and a PMOS transistor, and the third transistor Q3 is the other of the NMOS transistor and the PMOS transistor, and at this time, the circuit structure should be adjusted accordingly.
Example 1
The first transistor Q1 and the third transistor Q3 are NMOS transistors, and the second transistor Q2 is an NMOS transistor. At this time, as shown in fig. 8, the damping resistor R0 is connected in parallel with the third transistor Q3, the source of the first transistor Q1, the drain of the second transistor Q2, and the source of the third transistor Q3 are connected, the gate of the first transistor Q1, the gate of the second transistor Q2, and the gate of the third transistor Q3 are connected to the output terminal of the first gate driver 231, the output terminal of the second gate driver 232, and the output terminal of the third gate driver 221, respectively, the source of the second transistor Q2 is grounded, the drain of the first transistor Q1 is connected to the first voltage VH, and the drain of the third transistor Q3 is connected to the resonant circuit 210.
Referring to fig. 7, timing diagrams of the first transistor Q1, the second transistor Q2 and the third transistor Q3 are shown, wherein the first transistor Q1 and the second transistor Q2 are alternately turned on under the control of the first gate driver 231 and the second gate driver 232 respectively, to generate pulse signals to drive the resonant circuit 210 to output the sine wave signal V TX Meanwhile, when the first transistor Q1 and the second transistor Q2 are alternately turned on, the third transistor Q3 needs to be maintained to be turned on under the control of the third gate driver 221.
In order to realize that the third transistor Q3 can be maintained in a turned-on state when the first transistor Q1 and the second transistor Q2 are alternately turned on, a diode D1 and a second capacitor C connected to the first switching module and the third switching module may be provided in the control circuit 230 BOOT Thereby utilizing the second capacitance C BOOT The characteristic that the voltage across cannot abruptly change maintains the on state of the third transistor Q3.
For example, as shown in FIG. 8, the control circuit 230 includes a diode D1 and a second capacitor C BOOT Among them, a connection point SW between the source of the first transistor Q1, the drain of the second transistor Q2, and the source of the third transistor Q3, the first power source terminal 231a of the first gate driver 231, the first power source terminal 221a of the third gate driver 221, and the second capacitor C BOOT To the first end 233 a. A second power source terminal 231b of the first gate driver 231, a second power source terminal 221b of the third gate driver 221, and a second capacitor C BOOT And the second terminal 233b of the diode D1Furthermore, the input terminal of the diode D1 and the second power terminal 232b of the second gate driver 232 are connected to a second voltage VIN, the first power terminal 232a of the second gate driver 232 is connected to ground, and the second voltage VIN is smaller than the first voltage VH.
Optionally, the first voltage VH is a power supply voltage, and the second voltage VIN is an on voltage of NMOS transistors, i.e., the first transistor Q1, the second transistor Q2, and the third transistor Q3. For example, the first voltage is between 3V and 36V, such as 20V; the second voltage is between 2V and 5V, and further, may be between 3V and 4.5V.
The input terminals of the first gate driver 231, the second gate driver 232 and the third gate driver 221 are respectively corresponding to control signals S1, S2 and S3 for respectively controlling the first transistor Q1, the second transistor Q2 and the third transistor Q3 to be turned on and off. Since the second transistor Q2 is an NMOS transistor, when the output of the second gate driver 232 is controlled to be at a high level, i.e., VIN, by the control signal S2, the second transistor Q2 is turned on, where VIN is the turn-on voltage of the NMOS transistor; when the output of the second gate driver 232 is controlled to be at a low level, i.e., 0V, by the control signal S2, the second transistor Q2 is turned off.
The source of the first transistor Q1 and the source of the third transistor Q3 are connected to SW, the potential at SW being denoted as V SW The high level at SW is VH and the low level at SW is 0V. Since the first transistor Q1 and the third transistor Q3 are NMOS transistors, the output of the first gate driver 231 is controlled to be a high level V by the control signal S1 SW + VIN, the first transistor Q1 can be turned on; controls the output of the first gate driver 231 to be a low level V SW The first transistor Q1 can only be turned off. Likewise, the output of the third gate driver 221 is controlled to be the high level V by the control signal S3 SW At + VIN, the third transistor Q3 can be turned on; controls the output of the third gate driver 221 to be a low level V SW The third transistor Q3 can be turned off.
In generating a sine wave signal V TX In this case, the first transistor Q1 and the second transistor Q2 are turned on alternately, and at this time, the third transistor Q3 needs to be kept in a turned-on state. For this purpose, diodes D1 andsecond capacitor C BOOT To be implemented. For example, as shown in fig. 8, when the second transistor Q2 is controlled to be turned on, the first transistor Q1 is controlled to be turned off, and the third transistor Q3 is controlled to be turned on, SW is low, the diode D1 is turned on, and the voltage V is controlled to be low BOOT Is VIN-VD, wherein VD is the voltage drop of the diode D1 and the voltage V BOOT Sufficient for the turn-on of the third transistor Q3. When the second transistor Q2 is turned off, the first transistor Q1 is turned on, and the third transistor Q3 is turned on, SW is high, the diode D1 is turned off due to the second capacitor C BOOT The voltage at both ends cannot change suddenly, so the second capacitor C BOOT Voltage V across BOOT The third transistor Q3 can be maintained on.
In this way, when the third gate driver 221 is controlled to output a high level to turn on the third transistor Q3, by using the diode D1 and the second capacitor C BOOT Providing the high level V BOOT Thereby generating a sine wave signal V TX The on state of the third transistor Q3 can be maintained.
When it is desired that the resonance circuit 210 stops outputting the sine wave signal V TX In time, a sine wave signal V is required TX Fast zeroing, controlling the third gate driver 221 to output a low level to turn off the third transistor Q3, thereby connecting the damping resistor R0 between the point SW and the inductor L to absorb the excessive signal energy generated by the resonant circuit 210 and improve the sine wave signal V TX Residual vibration of the steel.
Example 2
The first transistor Q1 and the third transistor Q3 are PMOS transistors, and the second transistor Q2 is an NMOS transistor. At this time, as shown in fig. 9, the damping resistor R0 is connected in parallel with the third transistor Q3, the drain of the first transistor Q1, the drain of the second transistor Q2, and the drain of the third transistor Q3 are connected, the gate of the first transistor Q1, the gate of the second transistor Q2, and the gate of the third transistor Q3 are connected to the output terminal of the first gate driver 231, the output terminal of the second gate driver 232, and the output terminal of the third gate driver 221, respectively, the source of the second transistor Q2 is grounded, the source of the first transistor Q1 is connected to the first voltage VH, and the source of the third transistor Q3 is connected to the resonant circuit 210.
Referring to fig. 7, timing diagrams of the first transistor Q1, the second transistor Q2 and the third transistor Q3 are shown, wherein the first transistor Q1 and the second transistor Q2 are alternately turned on under the control of the first gate driver 231 and the second gate driver 232, respectively, to generate a pulse signal to drive the resonant circuit 210 to output the sine wave signal V TX Meanwhile, when the first transistor Q1 and the second transistor Q2 are alternately turned on, the third transistor Q3 needs to be maintained to be turned on under the control of the third gate driver 221.
In order to realize that the third transistor Q3 can be maintained in a turned-on state when the first transistor Q1 and the second transistor Q2 are alternately turned on, a diode D1 and a second capacitor C connected to the third switching module may be provided in the control circuit 230 BOOT Thereby utilizing the second capacitance C BOOT The characteristic that the voltage across cannot abruptly change maintains the on state of the third transistor Q3.
For example, as shown in fig. 9, the control circuit 230 further includes a diode D1 and a second capacitor C BOOT Wherein the source of the third transistor Q3 is connected to the first power terminal 221a of the third gate driver 221 and the second capacitor C BOOT And a second power terminal 221b of the third gate driver 221 is connected to the second capacitor C BOOT The output terminal of the diode D1 and the second power source terminal 231b of the first gate driver 231 are connected to a third voltage VM, the source of the first transistor Q1 is connected to the first power source terminal 231a of the first gate driver 231, the first power source terminal 232a of the second gate driver 232 is connected to the second voltage VIN, and the second power source terminal 232 of the second gate driver 232 is grounded.
Optionally, the first voltage VH is a power voltage, the second voltage VIN is an on voltage of the NMOS transistor Q2, and the third voltage VM is a difference between the first voltage VH and an absolute value of an on voltage VGS of the PMOS transistor Q1 and the third transistor Q3. For example, the first voltage VH is between 3V and 36V, such as 20V; the second voltage VIN is between 2V and 5V, and further, may be between 3V and 4.5V; the third voltage VM is 2V to 5V smaller than the first voltage VH, for example, the third voltage VM is 4V smaller than the first voltage VH; the turn-on voltage VGS of the PMOS tube is between-2V and-5V, such as-4V.
The control signals S1, S2 and S3 corresponding to the respective input terminals of the first gate driver 231, the second gate driver 232 and the third gate driver 221 are respectively used for controlling the first transistor Q1, the second transistor Q2 and the third transistor Q3 to be turned on and off. VGS requires negative voltage, for example VGS = -4V, the first gate driver 231 is powered using 20V and 16V. Since the second transistor Q2 is an NMOS transistor, when the output of the second gate driver 232 is controlled to be a high level, i.e., VIN, by the control signal S2, the second transistor Q2 is turned on, where VIN is an on-state voltage of the NMOS transistor; when the output of the second gate driver 232 is controlled to be at a low level, i.e., 0V, by the control signal S2, the second transistor Q2 is turned off. Since the first transistor Q1 is a PMOS transistor, VGS = -4V when the output of the first gate driver 231 is controlled to be at the low level VCM =16V by the control signal S1, and the first transistor Q1 is turned on; when the output of the first gate driver 231 is controlled to be at the high level VH =20V by the control signal S1, the first transistor Q1 is turned off.
In generating a sine wave signal V TX In this case, the first transistor Q1 and the second transistor Q2 are turned on alternately, and at this time, the third transistor Q3 needs to be kept in a turned-on state. For this purpose, diode D1 and second capacitor C may likewise be used BOOT In conjunction with the third gate driver 221. For example, as shown in fig. 9, when the first transistor Q1 is turned on, the second transistor Q2 is turned off, and the third transistor Q3 is turned on, the SW is low, the parasitic diode D2 of the third transistor Q3 is turned on, the diode D1 is also turned on, and the voltage V is controlled to be turned on BOOT Is VH-VM-VD1-VD2, wherein VD1 and VD2 are the voltage drop of diode D2 and diode D1 respectively, and the voltage V is BOOT Sufficient for the turn-on of the third transistor Q3. When the first transistor Q1 is controlled to be turned off, the second transistor Q2 is controlled to be turned on, and the third transistor Q3 is controlled to be turned on, the SW is at a low level, the diode D1 is turned off due to the second capacitor C BOOT The voltage at both ends cannot change suddenly, so the second capacitor C BOOT Voltage V across BOOT The third transistor Q3 can be maintained on.
Thus, when the third gate driver 221 output is controlledWhen the level is low to turn on the third transistor Q3, the second capacitor C is turned on by the diode D1 BOOT Providing the low level V BOOT Thereby generating a sine wave signal V TX The on state of the third transistor Q3 can be maintained.
When it is desired that the resonance circuit 210 stops outputting the sine wave signal V TX In time, a sine wave signal V is required TX Fast zeroing, controlling the third gate driver 221 to output a high level to turn off the third transistor Q3, thereby connecting the damping resistor R0 between the point SW and the inductor L to absorb the excessive signal energy generated by resonance and improve the sine wave signal V TX Residual vibration of the steel.
When the second capacitor C BOOT When connected to the inductor L in the resonant circuit 210, the second capacitor C during "braking" operation BOOT The voltage of the inductor L is continuously increased by absorbing the energy of the inductor L, and for this reason, in one implementation, the control circuit 230 further includes a second resistor R2, a second resistor R2 and a second capacitor C BOOT In parallel, the second resistor R2 is used to discharge the second capacitor C2 to reduce the inductance L in the resonant circuit 210 causing the second capacitor C BOOT The boosting of (2).
For example, as shown in FIG. 9, the first end 234a of the second resistor R2 is connected to the second capacitor C BOOT A first terminal 233a of the third gate driver, a first power terminal 221a of the third gate driver, and a source of a third transistor Q3, and a second terminal 234b of the second resistor R2 is connected to the second capacitor C BOOT And the second terminal 233b of the third gate driver 221, and the second power supply terminal 221b of the third gate driver 221, the second resistor R2 enables the second capacitor C BOOT Discharging, since the second resistor R2 can bear the second capacitor C BOOT The amount of discharged electricity is reduced, thereby reducing the second capacitance C BOOT The circuit safety is improved.
The signal generating circuit 200 of the embodiment of the present application can be applied to an ultrasonic fingerprint identification device. As shown in fig. 10, the ultrasonic fingerprint recognition device 300 comprises an ultrasonic transducer 310 and the signal generating circuit 200 in any of the above embodiments. Sine wave signal V output by signal generating circuit 200 TX For driving ultrasonic transducer 310 to generate a fingerUltrasonic signals for pattern recognition.
For example, taking the signal generating circuit 200 shown in fig. 8 as an example, when the signal generating circuit 200 shown in fig. 8 is applied to the ultrasonic fingerprint identification device 300, the first capacitor C1 in the resonant circuit 210 of the signal generating circuit 200 is replaced by the ultrasonic transducer 310, resulting in the circuit diagram shown in fig. 11. Wherein the sine wave signal V generated by the signal generating circuit 200 TX The ultrasonic transducer 310 is driven to generate an ultrasonic signal for fingerprint recognition. The ultrasonic transducer 310 can be regarded as an equivalent circuit 240 formed by connecting a capacitor Ceq and a resistor Req in series, as shown by the dotted line connection in fig. 11. The ultrasonic transducer 310 has an operating frequency f t Let the resonant frequency of inductor L and capacitor Ceq equal to f t The first transistor Q1 and the second transistor Q2 are alternately turned on at a frequency equal to f by controlling the first switch S1 and the second switch S2 t At this time, the sine wave signal V output from the signal generating circuit 200 TX The ultrasonic transducer 310 may be driven to emit an ultrasonic signal.
It should be noted that, without conflict, the embodiments and/or technical features in the embodiments described in the present application may be arbitrarily combined with each other, and the technical solutions obtained after the combination also fall within the protection scope of the present application.
The system, apparatus and method disclosed in the embodiments of the present application can be implemented in other ways. For example, some features of the method embodiments described above may be omitted or not performed. The above-described device embodiments are merely illustrative, the division of the unit is only one logical functional division, and there may be other divisions when the actual implementation is performed, and a plurality of units or components may be combined or may be integrated into another system. In addition, the coupling between the units or the coupling between the components may be direct coupling or indirect coupling, and the coupling includes electrical, mechanical or other connections.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes and the generated technical effects of the above-described apparatuses and devices may refer to the corresponding processes and technical effects in the foregoing method embodiments, and are not described herein again.
It should be understood that the specific examples in the embodiments of the present application are for the purpose of promoting a better understanding of the embodiments of the present application, and are not intended to limit the scope of the embodiments of the present application, and that various modifications and variations can be made by those skilled in the art based on the above embodiments and fall within the scope of the present application.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (16)
1. A signal generating circuit, comprising:
a resonant circuit for generating a sine wave signal;
the control circuit is used for generating a pulse signal, and the pulse signal is used for driving the resonance circuit to generate the sine wave signal; and the number of the first and second groups,
the brake circuit comprises a damping resistor, the damping resistor is connected between the resonant circuit and the control circuit, and the damping resistor is used for absorbing redundant signal energy generated by the resonant circuit after the control circuit stops generating the preset duration of the pulse signal;
the brake circuit further comprises a third switch module connected with the damping resistor in parallel, and the third switch module is used for being switched on when the control circuit generates the pulse signal and being switched off after the control circuit stops generating the preset duration of the pulse signal.
2. The signal generating circuit of claim 1, wherein the resonant circuit comprises an inductor and a first capacitor in series,one end of the inductor is connected with the first capacitor through a first resistor, the other end of the inductor is connected with the damping resistor, wherein the resistance value of the damping resistorR0And the resistance value of the first resistorR1Satisfies the following conditions:R1+R0=1.4*Z，Zis the characteristic impedance of the resonance circuit,
，LandCthe values of the inductance and the first capacitance, respectively.
3. The signal generating circuit of claim 2,R0at 0.8X Z to 2XZIn the meantime.
4. The signal generating circuit according to any one of claims 1 to 3, wherein the control circuit comprises a first switch module and a second switch module, the first switch module is connected between a power supply and the damping resistor, the second switch module is connected between the damping resistor and ground, and the first switch module and the second switch module are alternately turned on to generate the pulse signal.
5. The signal generating circuit according to claim 4, wherein the first switch module includes a first transistor and a first gate driver connected to the first transistor, wherein the second switch module includes a second transistor and a second gate driver connected to the second transistor, and wherein the third switch module includes a third transistor and a third gate driver connected to the third transistor.
6. The signal generating circuit according to claim 5, wherein the first transistor is one of an NMOS transistor and a PMOS transistor, the second transistor is an NMOS transistor, and the third transistor is one of an NMOS transistor and a PMOS transistor.
7. The signal generating circuit according to claim 6, wherein the first transistor and the third transistor are NMOS transistors, the damping resistor is connected in parallel with the third transistor, a source of the first transistor, a drain of the second transistor, and a source of the third transistor are connected, a gate of the first transistor, a gate of the second transistor, and a gate of the third transistor are connected to the output terminal of the first gate driver, the output terminal of the second gate driver, and the output terminal of the third gate driver, respectively, a source of the second transistor is grounded, a drain of the first transistor is connected to a first voltage, and a drain of the third transistor is connected to the resonant circuit.
8. The signal generating circuit according to claim 7, wherein the control circuit further comprises a diode and a second capacitor, wherein a connection point between the source of the first transistor, the drain of the second transistor, and the source of the third transistor is connected to the first power source terminal of the first gate driver, the first power source terminal of the third gate driver, and the first terminal of the second capacitor, the second power source terminal of the first gate driver, the second power source terminal of the third gate driver, and the second terminal of the second capacitor is connected to the output terminal of the diode, the input terminal of the diode and the second power source terminal of the second gate driver are connected to a second voltage, the first power source terminal of the second gate driver is connected to ground, and the second voltage is smaller than the first voltage.
9. The signal generating circuit of claim 8, wherein the first voltage is a power supply voltage and the second voltage is a turn-on voltage of the NMOS transistor.
10. The signal generating circuit of claim 9, wherein the first voltage is between 3V and 36V and the second voltage is between 2V and 5V.
11. The signal generating circuit according to claim 6, wherein the first transistor and the third transistor are PMOS transistors, the damping resistor is connected in parallel with the third transistor, a drain of the first transistor, a drain of the second transistor, and a drain of the third transistor are connected, a gate of the first transistor, a gate of the second transistor, and a gate of the third transistor are connected to the output terminal of the first gate driver, the output terminal of the second gate driver, and the output terminal of the third gate driver, respectively, a source of the second transistor is grounded, a source of the first transistor is connected to a first voltage, and a source of the third transistor is connected to the resonant circuit.
12. The signal generating circuit according to claim 11, wherein the control circuit further comprises a diode and a second capacitor, wherein a source of the third transistor is connected to a first power supply terminal of the third gate driver and a first terminal of the second capacitor, a second power supply terminal of the third gate driver is connected to a second terminal of the second capacitor and an input terminal of the diode, an output terminal of the diode and a second power supply terminal of the first gate driver are connected to a third voltage, a source of the first transistor is connected to the first power supply terminal of the first gate driver, a first power supply terminal of the second gate driver is connected to a second voltage, and a second power supply terminal of the second gate driver is connected to ground.
13. The signal generating circuit of claim 12, wherein the control circuit further comprises a second resistor connected in parallel with the second capacitor, the second resistor being configured to discharge the second capacitor to reduce a boost of the second capacitor caused by an inductance in the resonant circuit.
14. The signal generating circuit of claim 12, wherein the first voltage is a power supply voltage, the second voltage is a turn-on voltage of the NMOS transistor, and the third voltage is a difference between the first voltage and an absolute value of a turn-on voltage of the PMOS transistor.
15. The signal generating circuit as claimed in claim 14, wherein the first voltage is between 3V and 36V, the second voltage is between 2V and 5V, the third voltage is 2V to 5V smaller than the first voltage, and the turn-on voltage of the PMOS transistor is between-2V and-5V.
16. An ultrasonic fingerprint identification device, comprising:
an ultrasonic transducer; and the number of the first and second groups,
the signal generating circuit according to any one of claims 1 to 15, wherein the sine wave signal output by the signal generating circuit is used for driving the ultrasonic transducer to generate an ultrasonic signal for fingerprint identification.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210665485.0A CN114749359B (en) | 2022-06-14 | 2022-06-14 | Signal generating circuit and ultrasonic fingerprint identification device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210665485.0A CN114749359B (en) | 2022-06-14 | 2022-06-14 | Signal generating circuit and ultrasonic fingerprint identification device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114749359A CN114749359A (en) | 2022-07-15 |
| CN114749359B true CN114749359B (en) | 2022-09-06 |
Family
ID=82336213
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210665485.0A Active CN114749359B (en) | 2022-06-14 | 2022-06-14 | Signal generating circuit and ultrasonic fingerprint identification device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114749359B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024011519A1 (en) | 2022-07-14 | 2024-01-18 | 深圳市汇顶科技股份有限公司 | Ultrasonic fingerprint detection apparatus and electronic equipment |
| CN116140169B (en) * | 2022-06-14 | 2025-01-10 | 汇科(新加坡)控股私人有限公司 | Ultrasonic transceiver system and electronic equipment |
| US12205400B2 (en) | 2022-06-14 | 2025-01-21 | Huike (Singapore) Holding Pte.Ltd. | Ultrasonic transceiver system and electronic device |
| WO2024138393A1 (en) * | 2022-12-27 | 2024-07-04 | 深圳市汇顶科技股份有限公司 | Ultrasonic detection apparatus and electronic device |
| CN120318871B (en) * | 2025-06-11 | 2025-09-30 | 鸣芯信息科技(上海)有限公司 | A signal sending device, module and equipment for ultrasonic fingerprint recognition |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104935198A (en) * | 2014-03-19 | 2015-09-23 | 中航（重庆）微电子有限公司 | Resonance converter |
| CN109889072A (en) * | 2019-04-11 | 2019-06-14 | 广东美的制冷设备有限公司 | Drive control circuit and household appliance |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL8502338A (en) * | 1985-08-26 | 1987-03-16 | Philips Nv | SWITCHED POWER SUPPLY SWITCH WITH TWO STATES. |
| JPH08337363A (en) * | 1995-06-13 | 1996-12-24 | Toshiba Corp | Hydraulic elevator control system |
| JPH1179567A (en) * | 1997-09-11 | 1999-03-23 | Hitachi Ltd | Hydraulic elevator power outage time detection device |
| JP2002289385A (en) * | 2001-03-23 | 2002-10-04 | Harison Toshiba Lighting Corp | Discharge lamp drive |
| CN100508342C (en) * | 2006-09-15 | 2009-07-01 | 力博特公司 | An ARCP Soft Switching Circuit with Voltage Clamping Function |
| US7434948B2 (en) * | 2006-10-31 | 2008-10-14 | Northrop Grumman Space & Missions Systems Corp. | Optical architecture requiring a single tilt mirror to pass a collimated beam through an aperture stop, centered, at a desired angle, in one or two dimensions |
| JP4567762B2 (en) * | 2008-03-17 | 2010-10-20 | 株式会社日本自動車部品総合研究所 | Receiver |
| CN101585459A (en) * | 2009-04-17 | 2009-11-25 | 康力电梯股份有限公司 | Hydraulic elevator control system based on frequency converter |
| CN101807864B (en) * | 2010-03-25 | 2012-05-30 | 吉林大学 | Emission current subdivision control circuit based on magnetic source electromagnetic method |
| CN101817471B (en) * | 2010-04-27 | 2012-06-13 | 天津大学 | Super capacitor energy-storage type elevator driver |
| CN103052200B (en) * | 2011-10-13 | 2016-04-20 | 欧司朗股份有限公司 | Lighting Control Assembly and control method thereof |
| SE536142C2 (en) * | 2011-11-25 | 2013-05-28 | Comsys Ab | Active filter for resonance reduction |
| CN202424494U (en) * | 2012-02-16 | 2012-09-05 | 青岛昌盛日电太阳能科技有限公司 | LCL filter |
| CN203339946U (en) * | 2013-06-08 | 2013-12-11 | 武汉能创技术有限公司 | LCD absorption circuit |
| CN104734516B (en) * | 2015-02-11 | 2017-12-15 | 深圳市航嘉驰源电气股份有限公司 | Switching power circuit and computer power supply |
| CN206790358U (en) * | 2017-06-21 | 2017-12-22 | 成都茂源科技有限公司 | A kind of shaking platform excitation power |
| CN213754334U (en) * | 2020-12-29 | 2021-07-20 | 深圳己道科技有限公司 | Impedance and resonant frequency self-adaptive driving circuit of ultrasonic transducer |
| CN114188928B (en) * | 2021-12-13 | 2023-09-08 | 广西电网有限责任公司河池供电局 | Broken line resonance overvoltage suppression method based on intelligent switch |
-
2022
- 2022-06-14 CN CN202210665485.0A patent/CN114749359B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104935198A (en) * | 2014-03-19 | 2015-09-23 | 中航（重庆）微电子有限公司 | Resonance converter |
| CN109889072A (en) * | 2019-04-11 | 2019-06-14 | 广东美的制冷设备有限公司 | Drive control circuit and household appliance |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114749359A (en) | 2022-07-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN114749359B (en) | Signal generating circuit and ultrasonic fingerprint identification device | |
| KR101431880B1 (en) | Output driving circuit and transistor output circuit | |
| KR101387266B1 (en) | Level shift device | |
| JP2011155636A (en) | Driver for piezoelectric actuator | |
| US6570777B1 (en) | Half sine wave resonant drive circuit | |
| KR20120042641A (en) | Output circuit | |
| WO2006137221A1 (en) | Drive circuit | |
| US9871513B2 (en) | Semiconductor device | |
| US20080303586A1 (en) | Negative voltage generating circuit | |
| JP2007501544A (en) | High frequency control of semiconductor switches | |
| US6483377B2 (en) | Low slew rate charge pump | |
| US11165417B2 (en) | Efficient high-voltage digital I/O protection | |
| JPWO2002039179A1 (en) | Liquid crystal display | |
| JP7210928B2 (en) | High voltage integrated circuit | |
| JP4357698B2 (en) | Reset circuit and power supply device | |
| KR101876065B1 (en) | Drive circuit for an oscillator | |
| TWI587615B (en) | Driving circuit for power switch | |
| WO2023240430A1 (en) | Signal generation circuit and ultrasonic fingerprint recognition apparatus | |
| JP2018198504A (en) | Integrated circuit device | |
| WO2011045083A1 (en) | High voltage switch configuration | |
| US8294506B2 (en) | Driving system for switching power supply to reduce switch noise and switching loss | |
| US8618846B2 (en) | Solid-state switch driving circuit for vehicle | |
| US8067993B2 (en) | Constant current driven oscillating circuit | |
| US12218654B2 (en) | Switching device | |
| KR20110010930A (en) | Voltage multiplication circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20240802 Address after: 51 Science Park Road, Aries Tower # 04-22, Singapore Patentee after: Huike (Singapore) Holdings Private Ltd. Country or region after: Singapore Address before: 13 / F, block B, Tengfei Industrial Building, Futian Free Trade Zone, Shenzhen, Guangdong 518045 Patentee before: SHENZHEN GOODIX TECHNOLOGY Co.,Ltd. Country or region before: China |
|
| TR01 | Transfer of patent right |