CN114756200B - 64-bit adder for realizing radix-4 Booth multiplier and its implementation method - Google Patents
64-bit adder for realizing radix-4 Booth multiplier and its implementation methodInfo
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- CN114756200B CN114756200B CN202210402682.3A CN202210402682A CN114756200B CN 114756200 B CN114756200 B CN 114756200B CN 202210402682 A CN202210402682 A CN 202210402682A CN 114756200 B CN114756200 B CN 114756200B
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- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
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- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
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- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
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Abstract
The embodiment of the application provides a 64-bit adder for realizing a base 4Booth multiplier, an implementation method, an operation circuit and a chip thereof, wherein the adder comprises bits which are used for determining that 16 groups of partial products with 32 bits of base 4Booth multiplication carry weights correspond to 0-63 bit positions, compressing the partial products on the 0-63 bit positions respectively and outputting 2 groups of data with 64 bits, the carry adder with a carry chain comprises N carry modules, a preprocessing unit of each carry module, an inter-stage parameter of the carry module and a summing module, wherein the N carry modules correspond to a plurality of bits of the 2 groups of data with 64 bits, the preprocessing unit of each carry module is used for preprocessing a plurality of bits in the 2 groups of data with the 64 bits, the carry calculating unit is used for generating carry output of each bit corresponding to the N carry modules and the inter-stage parameter of the N carry modules, and the summing module is electrically connected with the N carry modules and used for processing the 2 groups of data with the 64 bits and obtaining corresponding summing results.
Description
Technical Field
The embodiment of the application relates to the field of circuits, in particular to a 64-bit adder for realizing a base 4 Booth multiplier, and an implementation method, an operation circuit and a chip thereof.
Background
The base 4 Booth multiplier is one of the common circuits in digital circuit design, for example, the base 4 Booth multiplier is often used for complex logic chips such as a central processing unit (central processing unit, CPU), a graphics processor (graphics processing unit, GPU) and the like, and is also often used for comprehensive design chips such as a micro control unit (Microcontroller Unit, MCU), a field programmable gate array (Field Programmable GATE ARRAY, FPGA) and the like. In general, the multiplication operation can be divided into three steps, partial product generation, partial product compression into two rows of vectors, and finally re-addition of the two rows of vectors. In partial product generation, base 4-Booth coding is typically used, which reduces the number of partial products in the multiplier by half.
Therefore, how to obtain a final calculation result based on partial products in the base 4-Booth coding, so as to improve the overall performance of the base 4-Booth coding multiplier becomes a technical problem to be solved.
Disclosure of Invention
In view of the above, the embodiments of the present application provide a 64-bit adder for implementing a radix-4 Booth multiplier, and an implementation method, an operation circuit and a chip thereof, so as to overcome all or part of the technical drawbacks described above.
In a first aspect, an embodiment of the present application provides a 64-bit adder for implementing a radix-4 Booth multiplier, comprising:
The multi-path carry save adder is used for determining the bit positions corresponding to the partial products of the 16 groups of 32 bits with the multiplication carry weight of the base 4 Booth on the 0 th bit to the 63 th bit, compressing the partial products on the 0 th bit to the 63 th bit respectively and outputting 2 groups of data of 64 bits, and the number of the carry save adders used for compression on the 0 th bit to the 63 th bit is the sum of the number of the partial products on the corresponding bit and the number of the sign bits minus 2;
A carry-in-chain carry adder for adding and summing the 64-bit 2 sets of data, the carry-in-chain carry adder comprising:
N carry modules, each carry module corresponds to a plurality of bits of the 64-bit 2-group data, wherein the nth carry module is connected with the nth-1 carry module and is used for receiving an inter-stage carry parameter output by the nth-1 carry module, the multiplicand and the multiplier are 32-bit binary numbers, N is an integer smaller than or equal to 7, N is an integer larger than 1 and smaller than or equal to N, each carry module comprises a preprocessing unit and a plurality of carry calculation units, one carry calculation unit corresponds to one bit of the 64-bit 2-group data, the partial product is used for representing the product of the ith+1th bit, the ith-1-th bit and the multiplicand based on 4 Booth multiplication, and i is an integer larger than or equal to 0 and smaller than or equal to 31;
the n-th carry module comprises a preprocessing unit for preprocessing a plurality of bits in the corresponding 64-bit 2-group data;
The n-th carry module comprises a plurality of carry calculation units which are used for carrying out operation according to the preprocessing result and the interstage carry parameter of the n-1-th carry module, and generating carry output of each bit corresponding to the n-th carry module and the interstage carry parameter of the n-th carry module;
The summation module is electrically connected with the N carry modules, is used for processing the 64-bit 2-group data when a sign bit gating control signal of the 64-bit 2-group data is a valid bit, and comprises the steps of inverting the highest bit of a partial product of the 64-bit 2-group data, adding 1 to the highest bit of a first partial product, adding 1 bit before the highest bit of all partial products, and enabling the bit number to be 1, and is used for calculating according to each bit in the processed 64-bit 2-group data and a corresponding carry output to obtain a corresponding summation result, wherein the sign bit gating control signal is used for representing that the partial product is multiplied by a multiplicand.
In a second aspect, the present application provides a method for implementing a 64-bit adder for implementing a radix-4 Booth multiplier, comprising:
Receiving 16 sets of 32-bit partial products with a base 4 Booth multiplication carry weight, wherein the partial products are used for representing the i+1th bit, the i-th bit and the product of the i-1 th bit and a multiplicand based on the base 4 Booth multiplication, i is an integer which is greater than or equal to 0 and less than or equal to 31;
determining the corresponding bit positions of the 16 groups of 32-bit partial products with the multiplication carry weights of the base 4 Booth on the 0 th bit to the 63 th bit, respectively compressing the partial products on the 0 th bit to the 63 th bit, and outputting 2 groups of 64-bit data, wherein the number of carry save adders used for compression on the 0 th bit to the 63 th bit is the sum of the number of the partial products on the corresponding bit and the number of the sign bits minus 2;
Dividing the compressed 64-bit 2-group data into N data groups according to the bit order from low to high, wherein each data group comprises a plurality of bits in the 64-bit 2-group data, and N is an integer less than or equal to 7, wherein the partial product is used for representing the product of the (i+1) -th bit, the (i) -th bit and the (i-1) -th bit of a multiplier and the multiplicand based on the multiplication of the base 4 Booth;
Preprocessing a plurality of bits contained in each data set;
Calculating carry output of a plurality of bits contained in each data group, wherein for an nth data group in N data groups, carrying out operation according to a preprocessing result of the nth data group and an inter-stage carry parameter of an N-1 th data group, and generating carry output of each bit corresponding to the nth data group and the inter-stage carry parameter of an N-th carry module, wherein N is an integer greater than 1 and less than or equal to N;
When the sign bit gating control signal of the 64-bit 2-group data is a valid bit, processing the partial product of the 64-bit 2-group data, wherein the processing comprises inverting the highest bit of the partial product in the 64-bit 2-group data, adding 1 to the highest bit of the first partial product, and adding 1 bit before the highest bit of all the partial products, wherein the sign bit gating control signal is used for representing that the partial product is multiplied by a multiplicand, and the value of the bit is 1;
and carrying out operation according to each bit in the processed 64-bit 2-group data and the corresponding carry output to obtain a corresponding summation result.
In a third aspect, the present application provides an arithmetic circuit comprising an adder according to any one of the embodiments of the first aspect.
In a fourth aspect, the present application provides a chip comprising an arithmetic circuit provided according to any one of the embodiments of the second aspect. The embodiment of the application provides a 64-bit adder for realizing a radix 4 Booth multiplier and an implementation method, an operation circuit and a chip thereof, wherein the multi-path carry-save adder is used for determining 16 groups of bit positions corresponding to 32-bit partial products with radix 4 Booth multiplication carry weights on 0-63 bit positions and compressing the partial products on 0-63 bit positions respectively to output 64-bit 2 groups of data, the carry adder with a carry chain is used for carrying out addition summation on the 64-bit 2 groups of data, the carry adder with the carry chain comprises N carry modules, each carry module corresponds to a plurality of bit positions in the 64-bit 2 groups of data, and comprises a preprocessing unit and a plurality of carry calculation units, the N carry module comprises a plurality of carry calculation units and is used for carrying out operation according to the preprocessed result and N-1 module parameters, the N carry module can directly calculate the output parameter between the N carry module stages by utilizing the N-bit calculation unit and the N-1 bit calculation unit to directly calculate the output parameter between the N-1-bit stages when the N-th carry module is corresponding to each carry module, and the calculation speed is improved.
Drawings
Some specific embodiments of the application will be described in detail hereinafter by way of example and not by way of limitation with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts or portions. It will be appreciated by those skilled in the art that the drawings are not necessarily drawn to scale. In the accompanying drawings:
FIG. 1 is a schematic diagram of a 64-bit adder for implementing a radix-4 Booth multiplier for summing 16 sets of 16 bits according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a carry adder with a carry chain for implementing a 64-bit adder of a radix-4 Booth multiplier according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a first preprocessing unit in a carry module of a carry adder with a carry chain for implementing a 64-bit adder of a radix-4 Booth multiplier according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a second preprocessing unit in a carry module of a carry adder with a carry chain for implementing a 64-bit adder of a radix-4 Booth multiplier according to an embodiment of the present application;
fig. 5 is a schematic flow chart of an implementation method of a 64-bit adder for implementing a base 4 Booth multiplier according to an embodiment of the present application.
Detailed Description
The implementation of the embodiments of the present invention will be further described below with reference to the accompanying drawings.
Example 1
FIG. 1 shows a 64-bit addition for implementing a radix-4 Booth multiplier according to an embodiment of the present application
The principle sketch of the device for summing 16 sets of data of 16 bits. Each data is a partial product, and is used for representing the product of the ith+1th bit, the ith bit and the i-1 th bit of the multiplier and the multiplicand based on the multiplication of the base 4 Booth, wherein i is an integer which is more than or equal to 0 and less than or equal to 31. Specifically, the multi-way carry save adder is used for determining bits corresponding to the 16 groups of partial products of 32 bits with the multiplication carry weight of the base 4 Booth on bits 0-63. Since the carry weights of the 16 groups of partial products are different, the dislocation arrangement form shown in fig. 1 is formed after the arrangement is performed according to each carry weight. And the number of the carry save adders used for compression on the 0-63 bits is the sum of the number of the partial products on the corresponding bits and the number of the sign bits minus 2.
The embodiment of the application provides a 64-bit addition method for realizing a base 4 Booth multiplier
In the multi-path carry save adder, the multi-path carry save adder is used for compressing 16 groups of 16 bits of data into 8-2 data and outputting 2 groups of 64 bits of data, and the number of the corresponding carry save adders on each bit of the 64-bit adder is the sum of the number of partial products on the corresponding bit and the number of sign bits minus 2. For example, the number of carry-save adders for the 14 th to 18 th bits is 7, the number of carry-save adders for the 15 th bit is 6, the number of carry-save adders for the 16 th bit is 8, the number of carry-save adders for the 17 th bit is 7, and the number of carry-save adders for the 18 th bit is 9.
Fig. 2 is a schematic diagram of a carry adder with a carry chain for implementing a 64-bit adder of a radix-4 Booth multiplier according to an embodiment of the present application. The carry adder with carry chain in this embodiment may be an independent hardware circuit structure, or may be a basic circuit unit structure of other devices such as a chip or a microprocessor. As shown in fig. 2, the carry adder with a carry chain for implementing the 64-bit adder of the base 4 Booth multiplier according to the embodiment of the present application includes N carry modules 10, where N is an integer less than or equal to 7. Each carry module corresponds to a plurality of bits of the 64-bit 2-set data, wherein the 64-bit 2-set data is a 16-bit binary number. For example, one carry module may correspond to 2 bits, 3 bits, or more bits, etc. of the 2 sets of 64 bits of data. It should be appreciated that the number of bits in the 64-bit 2-group data for each of the N carry modules 10 may be the same or different. The partial product is used for representing the product of the ith+1th bit, the ith bit and the i-1 th bit of the multiplier and the multiplicand based on the multiplication of the base 4 Booth, and i is an integer which is more than or equal to 0 and less than or equal to 31.
The nth carry module is connected with the (n-1) th carry module and is used for receiving the inter-stage carry parameter output by the (n-1) th carry module, so that the inter-stage carry parameter of the nth carry module and the carry output of each bit corresponding to the nth carry module are calculated based on the inter-stage carry parameter output by the (n-1) th carry module. Wherein N is an integer greater than 1 and less than or equal to N.
Each carry module includes a preprocessing unit and a plurality of carry calculation units, one carry calculation unit corresponding to one bit of the 2 sets of data of 64 bits.
In this embodiment, the nth carry module includes a preprocessing unit, configured to preprocess a plurality of bits in the corresponding 64-bit 2-group data.
Optionally, in one implementation of the application, the pre-processing results include an intra-group carry generation signal and an intra-group carry propagation signal. The n-th carry module comprises a preprocessing unit which is specifically used for calculating each bit in the corresponding 64-bit 2-group data to generate a carry generation signal and a carry propagation signal corresponding to each bit, and generating an intra-group carry generation signal and an intra-group carry propagation signal of each bit based on the carry generation signal and the carry propagation signal of at least one bit.
Specifically, each bit in the corresponding 64-bit 2 sets of data is logically and-ed, and a carry generation signal of each bit is generated, where the carry generation signal is a logical and-value operation result of the corresponding bit in the 64-bit 2 sets of data. Each bit in the corresponding 64-bit 2-group data is subjected to logical OR operation, and a carry propagation signal of each bit is generated, wherein the carry propagation signal is a logical OR value operation result of the corresponding bit in the 64-bit 2-group data. In order to facilitate the integrated layout when the circuit is implemented, in the embodiment of the present application, the result of performing the logical negation operation on the carry generation signal of each bit is sometimes referred to as a carry generation signal. Similarly, the result of logically negating the carry propagate signal for each bit is referred to as a carry propagate signal.
After the carry generation signal and the carry propagation signal of each bit corresponding to the nth carry module are obtained, the preprocessing unit contained in the nth carry module can also perform logic OR operation on the carry generation signals of the adjacent multiple bits to generate an intra-group carry generation signal, and the preprocessing unit contained in the nth carry module can also perform logic AND operation on the carry propagation signals of the adjacent multiple bits to generate an intra-group carry propagation signal. In order to facilitate the integrated layout when the circuit is implemented, in the embodiment of the present application, the result of performing the logical negation operation on the intra-group carry generation signal is sometimes referred to as an intra-group carry generation signal. Similarly, the result of the logical negation of the intra-group carry propagate signal is referred to as the intra-group carry propagate signal.
For example, for the ith bit in the first addend A and the second addend B, the carry generation signal of the ith bitCarry propagate signal for the ith bit. As described above, to facilitate an integrated layout in circuit implementation, the carry generation signal and the carry propagation signal of the ith bit are also sometimes denoted asOr (b). Group carry generation signal from jth bit to ith bit+...+Group carry propagate signal from jth bit to ith bit.... As described above, to facilitate an integrated layout in circuit implementation, the in-group carry generation signal and the carry propagation signal of the jth bit to the ith bit may also be sometimes expressed asAnd。
In addition, in the case of the optical fiber,A kind of electronic deviceWhere k is any bit located between the j-th bit and the i-th bit in the order of the bits from low to high.
In this embodiment, the nth carry module includes a plurality of carry calculation units, which are configured to perform operations according to the result of the preprocessing and the inter-stage carry parameter of the nth-1 carry module, and generate a carry output of each bit corresponding to the nth carry module and the inter-stage carry parameter of the nth carry module.
Optionally, in an embodiment of the present application, each carry calculating unit included in the nth carry module is specifically configured to perform an operation according to the intra-group carry generating signal and the intra-group carry propagating signal of the corresponding bit and the inter-stage carry parameter of the n-1 th carry module, so as to generate a carry output of the corresponding bit.
And the carry calculating unit corresponding to the highest bit in the plurality of bits corresponding to the nth carry module is also used for taking the carry parameter obtained in the calculation of the carry output of the highest bit corresponding to the nth carry module as the inter-stage carry parameter of the nth carry module.
The carry parameter is an intermediate quantity obtained in the calculation process of the carry output of each bit, and a preset relation exists between the carry parameter and the carry output. The carry output of each bit may be obtained by performing an operation based on the carry parameter of the bit and the carry propagation signal of the bit, and specifically, the carry output of each bit is a logical and operation result of the carry parameter of the bit and the carry propagation signal of the bit. For example, if the carry output of the ith bit isThe carry propagation signal of the ith bit is P i, and the carry parameter of the ith bit isThe preset relationship is:。
If the highest bit of the multiple bits corresponding to the n-1 th carry module is the nth bit A bit number, a plurality of carry calculation units in the n-1 th carry module calculate the n-1 th carryCarry out of individual bitsWhen get the carry parameterAs the n-1 st inter-stage carry parameter. If the output result of the preprocessing unit of the nth carry module comprises an intra-group carry generation signalAnd intra-group carry generation signalThe carry output of the ith bit is. In addition, due toTherefore, the method can be used for manufacturing the optical fiber,The same is true.
Due toAndCan be obtained by processing by a preprocessing unit, so that a carry calculating unit corresponding to the ith bit in the nth carry module obtains the inter-stage carry parameter of the (n-1) th carry moduleAnd in the process, the carry output or the carry parameter of the ith bit can be obtained through simple logic operation. In addition, the preprocessing unit in the nth carry module can preprocess a plurality of bits corresponding to the nth carry module to obtain a plurality of corresponding intra-group carry generation signals and a plurality of carry calculation units in the nth carry module of the intra-group carry propagation signals, and carry output of each bit can be calculated in parallel based on the corresponding intra-group carry generation signals and the intra-group carry propagation signals, so that the efficiency of carry calculation is improved.
It should be appreciated that to facilitate an integrated layout in circuit implementation, carry parametersAnd carry outAlso sometimes denoted asAnd。
In the embodiment of the application, the preprocessing unit included in the nth carry module preprocesses a plurality of bits in the corresponding 64-bit 2-group data, and the plurality of carry calculation units included in the nth carry module are used for carrying out operation according to the preprocessing result and the inter-stage carry parameter of the nth carry module to generate the carry output of each bit corresponding to the nth carry module and the inter-stage carry parameter of the nth carry module, so that when the inter-stage carry parameter output by the nth carry module is obtained, each carry calculation unit in the nth carry module can directly utilize the preprocessing result and the inter-stage carry parameter output by the nth carry module to parallelly calculate the carry output of each bit corresponding to the nth carry module, thereby basically realizing parallel calculation of the carry output of each bit in the 16-bit binary data.
In addition, as shown in fig. 2, the multi-way carry save adder in the 64-bit adder for implementing the base 4 Booth multiplier further comprises a summation module electrically connected with the N carry modules for processing the 2 groups of data of 64 bits when a sign bit gating control signal of the 2 groups of data of 64 bits is a valid bit, wherein the processing comprises inverting the highest bit of all partial products of the multiplicand and the multiplier, adding 1 to the highest bit of the first partial product, adding 1 bit before the highest bit of all partial products, and adding 1 to the bit number, and calculating according to each bit of the processed 2 groups of data of 64 bits and the corresponding carry output to obtain a corresponding summation result, wherein the sign bit gating control signal is used for representing that the partial products are multiplied by negative multiples.
For example, for the ith bit in the first addend a and the second addend B, the summation result of the ith bit may be obtained according to the following summation formula. The formula is:
Wherein, the Carry out for the i-1 th bit in the first addend A and the second addend A.
In this embodiment, since the carry output of each bit in the 16-bit binary data is calculated substantially in parallel, the result of summing each bit in the 16-bit binary data can be calculated substantially in parallel, and thus the duration of the entire calculation process can be shortened, and the calculation speed can be increased.
Optionally, in an embodiment of the present application, the number of bits in the 64-bit 2-group data corresponding to the nth carry module is equal to or greater than the number of bits in the 64-bit 2-group data corresponding to the n-1-th carry module.
Because the calculation of the carry output of each bit corresponding to the nth carry module depends on the inter-stage carry parameter of the nth-1 carry module, the carry operation time of each carry calculation unit in the nth carry module has a certain logic delay relative to the carry operation time of each carry calculation unit in the nth-1 carry module. The number of bits in the 2 groups of data with 64 bits corresponding to the nth carry module is equal to or greater than the number of bits in the 2 groups of data with 64 bits corresponding to the nth-1 carry module, so that the logic delay can be fully utilized to calculate an intra-group carry generation signal and an intra-group carry propagation signal, the situation that the nth carry module waits for the inter-stage carry parameter of the nth-1 carry module during calculation is avoided, and the time consumed by operation is further reduced.
Optionally, in an embodiment of the present application, N is equal to 7, the 1 st carry module corresponds to the 0 th to 3 rd bits of the 64-bit 2-group data, the 2 nd carry module corresponds to the 4 th to 7 th bits of the 64-bit 2-group data, the 3 rd carry module corresponds to the 8 th to 15 th bits of the 64-bit 2-group data, the 4 th carry module corresponds to the 16 th to 31 th bits of the 64-bit 2-group data, the 5 th carry module corresponds to the 32 th to 48 th bits of the 64-bit 2-group data, the 6 th carry module corresponds to the 49 th to 58 th bits of the 64-bit 2-group data, and the 7 th carry module corresponds to the 50 th to 63 th bits of the 64-bit 2-group data. Therefore, the layout of the adder is centralized, the area is small, and the overall structural layout is facilitated.
It should be understood that, in this embodiment, the number N of carry modules may be 2,4, or more, and the specific bit corresponding to each carry module may be set as required, which is not limited in this embodiment.
Example two
Further, the present embodiment provides a schematic diagram of a carry module in a multi-way carry save adder in the 64-bit adder for implementing the base 4 Booth multiplier shown in fig. 2, based on the 64-bit adder for implementing the base 4 Booth multiplier provided in the first embodiment. It should be understood that the carry module may be any one of the N carry modules in the first embodiment, and for convenience of description, the carry module will be hereinafter referred to as an nth carry module. In this embodiment, the n-th carry module includes preprocessing units including at least one first preprocessing unit and at least one second preprocessing unit alternately arranged.
In this embodiment, the first preprocessing unit is configured to perform an operation on an ith bit and an ith-1 bit in the corresponding 64-bit 2-group data, to generate a first preprocessing result, where the first preprocessing result indicates a logical or operation result of a carry generation signal of the ith bit and the ith-1 bit, and i is an odd number.
Alternatively, in a specific implementation of the present application, as shown in fig. 3, the first preprocessing unit includes a first and gate 201, a second and gate 202, and a first nor gate 203, where a first input terminal and a second input terminal of the first and gate 201 respectively receive the ith bit, an output terminal of the first and gate 201 is connected to a first input terminal of the first nor gate 203, a first input terminal and a second input terminal of the second and gate 202 respectively receive the ith-1 bit, an output terminal of the second and gate 202 is connected to a second input terminal of the first nor gate 203, and an output terminal of the first nor gate 203 outputs the first preprocessing result. For example, if the first addend is A and the second addend is B, the first preprocessing result is, wherein,AndA signal is generated for the carry of the i-th bit and a signal is generated for the carry of the i-1 th bit.
It should be understood that the first preprocessing unit may also be directly implemented by a nor gate, which is not limited in this embodiment.
In this embodiment, the second preprocessing unit is configured to perform an operation on the jth bit and the jth-1 bit in the corresponding 64-bit 2 sets of data, to generate a second preprocessing result, where the second preprocessing result indicates a logic and operation result of the carry propagation signals of the jth bit and the jth-1 bit, and j is an even number.
Alternatively, in a specific implementation manner of the present application, as shown in fig. 4, the second preprocessing unit includes a first or gate 301, a second or gate 302, and a first nand gate 303, where a first input terminal and a second input terminal of the first or gate 301 respectively receive a j-th bit, an output terminal of the first or gate 301 is connected to a first input terminal of the first nand gate, a first input terminal and a second input terminal of the second or gate 302 respectively receive a j-1-th bit, an output terminal of the second or gate 302 is connected to a second input terminal of the first nand gate 303, and an output terminal of the first nand gate 303 outputs a second preprocessing result. For example, if the first addend is A and the second addend is B, the first preprocessing result is, wherein,AndA carry propagate signal for the j-th bit and a carry propagate signal for the j-1 th bit.
It should be understood that the second preprocessing unit may also be directly implemented by a nand gate or a structure, which is not limited in this embodiment.
Correspondingly, the nth carry module comprises a plurality of carry calculation units which are used for obtaining the carry output of the corresponding bit based on at least one first preprocessing result, at least one second preprocessing result and the inter-stage carry parameter of the nth-1 carry module.
Optionally, in an embodiment of the present application, the preprocessing unit included in the nth carry module further includes a third preprocessing unit and a fourth preprocessing unit, the third preprocessing unit respectively performs an operation on at least two adjacent ones of the first preprocessing result output by the at least one first preprocessing unit and the second preprocessing result output by the at least one second preprocessing unit, so as to generate a corresponding third preprocessing result and a fourth preprocessing result, the third preprocessing result indicates a carry parameter between the corresponding adjacent bits, and the fourth preprocessing result indicates a logical and operation result of the carry propagation signal of the corresponding adjacent bits. The nth carry module comprises a plurality of carry calculation units which are used for obtaining the carry output of the corresponding bit based on the third preprocessing result, the fourth preprocessing result and the inter-stage carry parameter of the nth-1 carry module.
For example, the third preprocessing unit processes the first preprocessing resultAndSecond pretreatment resultPerforming operation to generate carry parameter GON_7_4=between 4 th bit and 7 th bit. The fourth preprocessing unit pair is based on the second preprocessing resultAnd a second pretreatment resultPerforming an operation to generate a logical OR operation result of the carry generation signal indicating the 3 rd bit to the 6 th bit, i.e. an intra-group carry propagation signal(I.e., PAN 6_3). The corresponding carry calculation unit may obtain a carry output of the 7 th bit based on the third pre-processing result gon_7_4 and the fourth pre-processing result pan_6_3 in combination with the inter-stage carry parameter of the n-1 st carry module.
Optionally, in one embodiment of the present application, the n-th carry module includes a plurality of carry calculation units including a first carry calculation unit corresponding to the i-th bit, and the first carry calculation unit includes a third or gate, a third and gate, and a second nor gate;
The first input end of the third OR gate is connected to the output end of the corresponding second preprocessing unit, the second input end of the third OR gate is connected to the inter-stage carry parameter output by the n-1 th carry module, the output end of the third OR gate is connected to the first input end of the third AND gate, the second input end of the third AND gate is connected to the output end of the corresponding first preprocessing unit, and the output end of the third AND gate outputs the carry parameter of the ith bit;
The output end of the third AND gate is connected to the first input end of the second NOR gate, the second input end of the second NOR gate receives the carry propagation signal of the ith bit, and the output end of the second NOR gate is connected to the summation module so as to output the carry output of the ith bit to the summation module.
Optionally, in an embodiment of the present application, the plurality of carry calculation units further includes a second carry calculation unit corresponding to the j-th bit, and the second carry calculation unit includes a fourth or gate and a second nand gate.
The first input end of the fourth OR gate is connected to the output end of the corresponding second preprocessing unit, the second input end of the fourth OR gate is connected to the inter-stage carry parameter or the carry parameter of the j-1 bit output by the n-1 carry module, the output end of the fourth OR gate is connected to the first input end of the second NAND gate, the second input end of the second NAND gate receives the carry generation signal corresponding to the j-th bit, and the output end of the second NAND gate is connected to the summation module so as to output the carry output of the j-th bit to the summation module.
In this embodiment, the first preprocessing unit, the second preprocessing unit, the third preprocessing unit and the fourth preprocessing unit in each carry module preprocess a plurality of bits in the 2 sets of data of 64 bits corresponding to each carry module, and each carry module includes a plurality of carry calculation units, so that when each carry module obtains the inter-stage carry parameter output by the previous carry module, the plurality of carry calculation units in each carry module can directly calculate the carry output of each corresponding bit in parallel by using the preprocessing result and the inter-stage carry parameter output by the previous carry module, thereby basically realizing parallel calculation of the carry output of each bit in the 16-bit binary data.
In the application, the 1 st carry module corresponds to the 0 th bit to the 3 rd bit of the 64-bit 2-group data, the 2 nd carry module corresponds to the 4 th bit to the 7 th bit of the 64-bit 2-group data, the 3 rd carry module corresponds to the 8 th bit to the 15 th bit of the 64-bit 2-group data, the 4 th carry module corresponds to the 16 th bit to the 23 rd bit of the 64-bit 2-group data, and the 5 th carry module corresponds to the 24 th bit to the 31 th bit of the 64-bit 2-group data.
In addition, by regularly arranging the first preprocessing unit, the second preprocessing unit, the third preprocessing unit, the fourth preprocessing unit, the first carry calculation unit, and the second carry calculation unit, it is possible to reduce the occupation area of the 64-bit adder for implementing the base 4 Booth multiplier while increasing the calculation speed of the 64-bit adder for implementing the base 4 Booth multiplier, and to make the wirings more concentrated, which is advantageous for the overall structured layout.
It should be noted that, the present application is used to illustrate a specific example of a carry chain of a multi-way carry save adder in a 64-bit adder for implementing a radix 4 Booth multiplier, the number of carry modules may be 2,4, or more according to actual needs, and specific bits corresponding to each carry module may be set according to needs, which is not limited in this embodiment.
Example III
Based on the 64-bit adder for implementing the radix 4 Booth multiplier provided in the above embodiment, the embodiment of the present application provides a method for implementing the 64-bit adder for implementing the radix 4 Booth multiplier. Fig. 5 is a flowchart of an implementation method of a 64-bit adder for implementing a radix-4 Booth multiplier according to an embodiment of the present application. As shown in fig. 5, the implementation method of the 64-bit adder for implementing the base 4 Booth multiplier includes:
S501, receiving 16 groups of 32-bit partial products with a base 4 Booth multiplication carry weight, wherein the partial products are used for representing the (i+1) th bit, the (i) th bit and the product of the (i-1) th bit and a multiplicand based on the base 4 Booth multiplication, i is an integer which is greater than or equal to 0 and less than or equal to 31;
s502, determining the corresponding bit positions of the 16 groups of 32-bit partial products with the multiplication carry weights of the base 4 Booth on the 0 th to 63 th bit positions, respectively compressing the partial products on the 0 th to 63 th bit positions, and outputting 2 groups of 64-bit data, wherein the number of carry save adders used for compression on the 0 th to 63 th bit positions is the sum of the number of the partial products on the corresponding bit positions and the number of the sign bits minus 2;
S503, dividing the compressed 64-bit 2-group data into N data groups according to the bit order from low to high, wherein each data group comprises a plurality of bits in the 64-bit 2-group data, and N is an integer less than or equal to 7, wherein the partial product is used for representing the product of the (i+1) -th bit, the (i-1) -th bit and the multiplicand of the multiplier based on the multiplication of the base 4 Booth;
s504, preprocessing a plurality of bits contained in each data group;
S505, calculating carry outputs of a plurality of bits contained in each data group, wherein for an nth data group in N data groups, according to a preprocessing result of the nth data group and an inter-stage carry parameter of an N-1 th data group, carrying out operation to generate carry outputs of each bit corresponding to the nth data group and the inter-stage carry parameter of the nth carry module, wherein N is an integer greater than 1 and less than or equal to N;
S506, when a sign bit gating control signal of the 2 groups of 64 bits is a valid bit, the 2 groups of 64 bits are processed, wherein the processing comprises inverting the highest bit of all partial products of the multiplicand and the multiplier, adding 1 to the highest bit of the first partial product, and adding 1 bit before the highest bit of all partial products, wherein the sign bit gating control signal is used for representing that the partial product is multiplied by a negative multiple;
s507, calculating according to each bit in the processed 2 groups of data with 64 bits and the corresponding carry output to obtain a corresponding summation result.
The implementation method of the 64-bit adder for implementing the radix 4 Booth multiplier provided by the embodiment of the present application is used for implementing the 64-bit adder for implementing the radix 4 Booth multiplier in the foregoing device embodiment, and has the beneficial effects of the corresponding device embodiment, which are not repeated herein.
Example IV
An embodiment of the present application provides an arithmetic circuit including a 64-bit adder for implementing a radix-4 Booth multiplier provided in accordance with any one of the first and second embodiments. The principle and effect are similar, and are not repeated here.
Example five
The embodiment of the application provides a chip, which comprises the operation circuit provided by the fourth embodiment. The principle and effect are similar, and are not repeated here.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and variations of the present application will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the application are to be included in the scope of the claims of the present application.
Claims (10)
1. A 64-bit adder for implementing a base 4Booth multiplier, the 64-bit adder for implementing a base 4Booth multiplier comprising:
A multi-path carry save adder for determining the bit positions corresponding to the 16 groups of 32-bit partial products with the basic 4Booth multiplication carry weight on the 0 th bit to the 63 th bit, compressing the partial products on the 0 th bit to the 63 th bit, and outputting 2 groups of data of 64 bits, wherein the number of the carry save adders used for compression on the 0 th bit to the 63 th bit is the sum of the number of the partial products on the corresponding bit and the number of the sign bit minus 2;
A carry-in-chain carry adder for adding and summing the 64-bit 2 sets of data, the carry-in-chain carry adder comprising:
N carry modules, each carry module corresponds to a plurality of bits of the 64-bit 2-group data, wherein the nth carry module is connected with the nth-1 carry module and is used for receiving an interstage carry parameter output by the nth-1 carry module, a multiplicand and a multiplier are 32-bit binary numbers, N is an integer smaller than or equal to 7, N is an integer larger than 1 and smaller than or equal to N, each carry module comprises a preprocessing unit and a plurality of carry computing units, one carry computing unit corresponds to one bit of the 64-bit 2-group data, the partial product is used for representing the product of the ith+1th bit, the ith bit and the product of the ith-1-th bit and the multiplicand based on the multiplication of the base 4Booth, and i is an integer larger than or equal to 0 and smaller than or equal to 31;
the n-th carry module comprises a preprocessing unit for preprocessing a plurality of bits in the corresponding 64-bit 2-group data;
The n-th carry module comprises a plurality of carry calculation units which are used for carrying out operation according to the preprocessing result and the interstage carry parameter of the n-1-th carry module, and generating carry output of each bit corresponding to the n-th carry module and the interstage carry parameter of the n-th carry module;
the summation module is electrically connected with the N carry modules and is used for processing the 64-bit 2-group data when a sign bit gating control signal of the 64-bit 2-group data is a valid bit, the processing comprises the steps of inverting the highest bit of a partial product of the 64-bit 2-group data, adding 1 to the highest bit of a first partial product, adding 1 bit number in front of the highest bit of all the partial products, and enabling the bit number to be 1, and carrying out operation according to each bit in the processed 64-bit 2-group data and a corresponding carry output to obtain a corresponding summation result, wherein the sign bit gating control signal is used for representing that the partial product is multiplied by a multiplicand.
2. The 64-bit adder for implementing a radix-4 Booth multiplier of claim 1, wherein N is equal to 7, the 1 st carry module corresponds to bits 0 to 3 of the 64-bit 2-group data, the 2 nd carry module corresponds to bits 4 to 7 of the 64-bit 2-group data, the 3 rd carry module corresponds to bits 8 to 15 of the 64-bit 2-group data, the 4 th carry module corresponds to bits 16 to 31 of the 64-bit 2-group data, the 5 th carry module corresponds to bits 32 to 48 of the 64-bit 2-group data, the 6 th carry module corresponds to bits 49 to 58 of the 64-bit 2-group data, and the 7 th carry module corresponds to bits 50 to 63 of the 64-bit 2-group data.
3. The 64-bit adder for implementing a radix-4 Booth multiplier of claim 2 wherein said pre-processing results comprise an intra-group carry generation signal and an intra-group carry propagation signal;
The n-th carry module comprises a preprocessing unit, a carry generation signal and a carry propagation signal, wherein the preprocessing unit is specifically used for calculating each bit in the corresponding 64-bit 2 groups of data and generating a carry generation signal and a carry propagation signal corresponding to each bit;
Each carry calculating unit included in the nth carry module is specifically configured to perform operation according to the intra-group carry generating signal and the intra-group carry propagating signal of the corresponding bit and the inter-stage carry parameter of the nth-1 carry module, so as to generate a carry output of the corresponding bit.
4. A 64-bit adder for implementing a radix-4 Booth multiplier according to claim 3, wherein said most significant carry calculation unit corresponding to said nth carry module is further configured to use a carry parameter obtained in calculation of a most significant carry output of a plurality of bits corresponding to said nth carry module as an inter-stage carry parameter of said nth carry module, wherein said most significant carry output is obtained by performing an operation based on said most significant carry parameter and said most significant carry propagation signal.
5. The 64-bit adder for implementing a radix-4 Booth multiplier of claim 4, wherein said nth carry module comprises preprocessing units including at least one first preprocessing unit and at least one second preprocessing unit alternately arranged;
the first preprocessing unit is used for carrying out operation on an ith bit and an ith-1 bit in the corresponding 64-bit 2-group data to generate a first preprocessing result, wherein the first preprocessing result indicates a logic OR operation result of carry generation signals of the ith bit and the ith-1 bit, and i is an odd number;
The second preprocessing unit is used for carrying out operation on a j-th bit and a j-1-th bit in the corresponding 64-bit 2-group data to generate a second preprocessing result, the second preprocessing result indicates a logic AND operation result of carry propagation signals of the j-th bit and the j-1-th bit, and j is an even number;
And the n-th carry module comprises a plurality of carry calculation units which are used for obtaining the carry output of the corresponding bit based on the first preprocessing result, the second preprocessing result and the inter-stage carry parameter of the n-1-th carry module.
6. The 64-bit adder for implementing a radix 4Booth multiplier of claim 5, wherein said nth carry module comprises a plurality of carry computation units including a first carry computation unit corresponding to said ith bit, said first carry computation unit including a third or gate, a third and gate, and a second nor gate;
The first input end of the third OR gate is connected to the output end of the corresponding second preprocessing unit or fourth preprocessing unit, the second input end of the third OR gate is connected to the inter-stage carry parameter output by the n-1 th carry module, the output end of the third OR gate is connected to the first input end of the third AND gate, the second input end of the third AND gate is connected to the output end of the corresponding first preprocessing unit or third preprocessing unit, and the output end of the third AND gate outputs the carry parameter of the ith bit;
the output end of the third AND gate is connected to the first input end of the second NOR gate, the second input end of the second NOR gate receives the carry propagation signal of the ith bit, and the output end of the second NOR gate is connected to the summation module so as to output the carry output of the ith bit to the summation module.
7. The 64-bit adder for implementing a radix-4 Booth multiplier of claim 6, wherein said plurality of carry computation units comprises a second carry computation unit corresponding to said j-th bit, said second carry computation unit comprising a fourth or gate and a second nand gate;
The first input end of the fourth OR gate is connected to the output end of the corresponding second preprocessing unit, the second input end of the fourth OR gate is connected to the inter-stage carry parameter output by the n-1 th carry module or the carry parameter of the j-1 th bit, the output end of the fourth OR gate is connected to the first input end of the second NAND gate, the second input end of the second NAND gate receives the carry generation signal corresponding to the j-th bit, and the output end of the second NAND gate is connected to the summation module so as to output the carry output of the j-th bit to the summation module.
8. A method for implementing a 64-bit adder for implementing a base 4Booth multiplier, comprising:
Receiving 16 groups of partial products with 32 bits of base 4Booth multiplication carry weight, wherein the partial products are used for representing the i+1th bit, the i bit and the product of the i-1 th bit and the multiplicand based on the base 4Booth multiplication of the multiplier, i is an integer which is more than or equal to 0 and less than or equal to 31;
determining the corresponding bit positions of the 16 groups of 32-bit partial products with the basic 4Booth multiplication carry weight on the 0 th bit to the 63 th bit, respectively compressing the partial products on the 0 th bit to the 63 th bit, and outputting 2 groups of 64-bit data;
dividing the compressed 64-bit 2-group data into N data groups according to the order of bits from low to high, wherein each data group comprises a plurality of bits in the 64-bit 2-group data, and N is an integer less than or equal to 7;
Preprocessing a plurality of bits contained in each data set;
Calculating carry output of a plurality of bits contained in each data group, wherein for an nth data group in N data groups, carrying out operation according to a preprocessing result of the nth data group and an inter-stage carry parameter of an N-1 th data group, and generating carry output of each bit corresponding to the nth data group and the inter-stage carry parameter of an N-th carry module, wherein N is an integer greater than 1 and less than or equal to N;
Processing a partial product of the 64-bit 2-group data when a sign bit gating control signal of the 64-bit 2-group data is a valid bit, wherein the processing comprises inverting a highest bit of the 64-bit 2-group data partial product, adding 1 to a highest bit of a first partial product, and adding 1 bit before the highest bit of all partial products, and the bit number is 1;
and carrying out operation according to each bit in the processed 64-bit 2-group data and the corresponding carry output to obtain a corresponding summation result.
9. An arithmetic circuit comprising a 64-bit adder for implementing a base 4Booth multiplier according to any one of claims 1 to 7.
10. A chip, characterized in that it comprises the arithmetic circuit according to claim 9.
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| US8667040B2 (en) * | 2010-12-03 | 2014-03-04 | Via Technologies, Inc. | Mechanism for carryless multiplication that employs booth encoding |
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| CN107977191A (en) * | 2016-10-21 | 2018-05-01 | 中国科学院微电子研究所 | Low-power-consumption parallel multiplier |
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