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CN114758958B - Fan-out packaging structure embedded with sensor or display chip and packaging method thereof - Google Patents

Fan-out packaging structure embedded with sensor or display chip and packaging method thereof

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Publication number
CN114758958B
CN114758958B CN202210237171.0A CN202210237171A CN114758958B CN 114758958 B CN114758958 B CN 114758958B CN 202210237171 A CN202210237171 A CN 202210237171A CN 114758958 B CN114758958 B CN 114758958B
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CN
China
Prior art keywords
fan
copper
chip
rdl
upper side
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202210237171.0A
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Chinese (zh)
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CN114758958A (en
Inventor
方立志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Espoo International Co ltd
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Espoo International Co ltd
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Application filed by Espoo International Co ltd filed Critical Espoo International Co ltd
Priority to CN202210237171.0A priority Critical patent/CN114758958B/en
Publication of CN114758958A publication Critical patent/CN114758958A/en
Application granted granted Critical
Publication of CN114758958B publication Critical patent/CN114758958B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02333—Structure of the redistribution layers being a bump
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16148—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area protruding from the surface

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本发明公开嵌入传感器或显示芯片的扇出封装结构及其封装方法，涉及半导体加工技术领域，包括步骤一：制作芯片级封装；步骤二：制作扇出型封装；步骤三：将若干个芯片级封装与第一玻璃载具进行黏附组装；步骤四：在各个扇出型封装的外侧加工第二压模树脂层，在第二压模树脂层制作若干个对应各个扇出型封装的第三RDL层，最上层第三RDL层的接点处设置有第三铜凸块，在第三铜凸块处植锡球，得到初始产品；步骤五：将第一玻璃载具分离，再将初始产品切成单颗。本发明将复数个芯片级封装嵌入于压模树脂，因为复数个芯片级封装的共面性，不会因后续制程而改变良好的共面性，并且因为多芯片封在同一封装体，可以使系统的体积缩小。

The present invention discloses a fan-out package structure and a packaging method for embedding a sensor or display chip, and relates to the field of semiconductor processing technology, including step 1: making a chip-level package; step 2: making a fan-out package; step 3: adhering and assembling a plurality of chip-level packages to a first glass carrier; step 4: processing a second mold resin layer on the outside of each fan-out package, making a plurality of third RDL layers corresponding to each fan-out package on the second mold resin layer, providing a third copper bump at the contact point of the top third RDL layer, and implanting solder balls at the third copper bump to obtain an initial product; step 5: separating the first glass carrier, and then cutting the initial product into single pieces. The present invention embeds a plurality of chip-level packages in the mold resin. Because the coplanarity of the plurality of chip-level packages is not changed by subsequent processes, and because multiple chips are encapsulated in the same package, the volume of the system can be reduced.

Description

Fan-out packaging structure embedded with sensor or display chip and packaging method thereof
Technical Field
The invention relates to the technical field of semiconductor processing, in particular to a fan-out packaging structure embedded with a sensor or a display chip and a packaging method thereof.
Background
At present, a packaging mode for a multi-chip sensor or a display is mainly to seal a single sensor or a display chip in a chip-level package, wherein the upper surface of the chip is covered with protective glass, the chip is provided with TSVs, signals on the upper layer are led to the lower layer, the lower surface of the chip is provided with RDLs and tin-copper bumps, and the chip-level package is stacked on a fan-out type package sealed with a controller or a processor. And then welding the plurality of stacked packages on the circuit board.
The display chip is provided with a light-emitting chip of red, green and blue (RGB) pixels (pixels), three light pixels are respectively emitted to a screen and blended into images of pixels of various colors, three different light-emitting chips are provided with respective driving chips and control chips, the light pixels are gathered on the screen by an optical lens in front of each light-emitting chip, coplanarity among the light chips is important, good coplanarity is achieved, and the pixels of the three colors can be correctly overlapped to present clear image quality. The pixels with three colors cannot be overlapped correctly due to poor coplanarity, the blended colors are not right, the image quality is blurred, and the image sensor chip has the same problems.
The front sensor or display package is independent of each other in three colors, so that it is difficult to control coplanarity, resulting in low yield of products.
Disclosure of Invention
The invention aims to provide a fan-out packaging structure embedded with a sensor or a display chip and a packaging method thereof, which solve the following technical problems:
how to enclose a multi-chip sensor or display chip in the same package and reduce the volume of the system.
The aim of the invention can be achieved by the following technical scheme:
The packaging method for the embedded sensor or the display chip comprises the following steps:
The first step of manufacturing chip scale package, namely gluing a specific position on the surface of a wafer, reversely bonding the wafer on one side of a third glass carrier, and pasting a protective tape on the other side of the third glass carrier to protect the third glass carrier from being scratched during the manufacturing process;
manufacturing TSVs on the side surface of the wafer as signal connection of the upper surface and the lower surface of the chip, manufacturing a plurality of fourth RDL layers on one side of the wafer far away from the third glass carrier, and finally electroplating tin-copper bumps at the joint of the uppermost RDL layers;
tearing off the protective tape, cutting the wafer and the third glass carrier into single pieces to obtain chip-scale package, and protecting the sensor or the display chip by glass;
Step two, manufacturing fan-out type packaging, namely coating an adhesive on the upper side of a second glass carrier to form a second adhesive layer, manufacturing a first tin-copper contact and a plurality of first RDL layers on the upper side of the second adhesive layer, arranging a plurality of copper columns on the upper side of the uppermost first RDL layer, adhering a wafer body, namely a driving chip or a control chip of a sensor or a display, on the upper side of the uppermost first RDL layer, arranging a first copper bump on the upper side of the wafer body, and pouring a first compression molding resin layer wrapping the copper columns and the outer sides of the wafer body on the upper side of the first RDL layer;
grinding the first die resin layer, exposing the copper column and the first copper bump to reach the designed thickness, and adjusting the exposed thickness by adjusting the thickness of the ground first die resin layer;
Manufacturing a plurality of second RDL layers on the upper side of the first die resin layer, wherein the uppermost second RDL layer is a second surface contact, a second copper bump positioned on the upper side of the second surface contact is arranged at the contact of the uppermost second RDL layer, then the second adhesive layer is dissociated, the first RDL layer is separated from a second glass carrier, the glass carrier is removed, and the fan-out type package is obtained by cutting the glass carrier into single pieces;
Assembling the chip scale package and the fan-out type package, namely adhering and assembling a plurality of third glass of the chip scale package and a first glass carrier through a first adhesive layer, wherein the thickness of the first glass carrier is standard, and the plurality of chip scale packages are positioned on the same plane, so that the chip scale package has good coplanarity, tin-copper bumps of the chip scale package are upwards distributed after the chip scale package is mounted, the first surface tin-copper joints of the fan-out type package are aligned with the tin-copper bumps of the chip scale package, electric conduction is formed through welding, and after the fan-out type package is assembled, the second copper bumps of the second surface joints of the fan-out type package are upwards;
step six, processing a second molding resin layer on the outer side of each fan-out type package, grinding the second molding resin layer, exposing a second copper bump of a second surface joint of the fan-out type package to the designed thickness, manufacturing a plurality of third RDL layers on the side surface of the second molding resin layer and corresponding to the upper side of each fan-out type package, arranging a third copper bump at the joint of the third RDL layer on the uppermost layer, and planting a tin ball at the third copper bump to obtain an initial product;
and step seven, the first adhesive layer is dissociated, the first glass carrier is removed, and the initial product is cut into single pieces, wherein the initial product comprises a plurality of assembled chip-scale packages and fan-out packages, after the initial product is cut into single pieces, the single piece internally comprises three groups of assembled chip-scale packages and fan-out packages, after the process of embedding the chip-scale packages into the fan-out packages is completed, the plurality of chip-scale packages are embedded into molding resin, and the coplanarity of the plurality of chip-scale packages cannot be changed due to the subsequent process.
The invention also discloses a fan-out packaging structure for embedding the sensor or the display chip, which comprises a first glass carrier, wherein a plurality of chip-level packages are adhered to the upper side of the first glass carrier through a first adhesive layer, after the processing, the first adhesive layer is dissociated, the first glass carrier is removed, fan-out packages are arranged on the upper sides of the plurality of chip-level packages, and a second compression molding resin layer covering the plurality of first adhesive layers and the outer sides of the plurality of chip-level packages is arranged on the upper side of the first glass carrier;
the upper side of the chip scale package is provided with tin-copper bumps which are distributed upwards;
The upper side and the lower side of the fan-out type package are respectively provided with a second surface contact and a first surface tin-copper contact, the first surface tin-copper contact is electrically connected with a tin-copper bump of the chip level package in a welding way, and the upper side of the second surface contact is provided with a plurality of second copper bumps extending to the upper side of the second compression molding resin layer;
the upper side of the second die resin layer is provided with a third RDL layer connected with the second copper bumps, the uppermost side of the third RDL layer is provided with a plurality of third copper bumps, and the outer sides of the third copper bumps are provided with tin-plated balls.
As a further scheme of the invention, the chip scale package comprises a third glass carrier, a flip-chip wafer is adhered to the upper side of the third glass carrier, TSVs (through silicon via, through silicon vias) are formed on the back surface of the wafer and used for signal connection of the upper surface and the lower surface of the chip, a plurality of fourth RDL layers are arranged on one side, far away from the third glass carrier, of the wafer, and tin-copper bumps are arranged on the uppermost side of the fourth RDL layers.
As a further scheme of the invention, a protective tape is stuck on one side of the third glass carrier far away from the wafer in the chip scale package during processing, so that the third glass carrier is protected from being scratched during processing, the protective tape is removed after processing, and the thickness of the third glass carrier adopts standard thickness.
As a further scheme of the invention, the fan-out type package comprises a plurality of first RDL layers arranged on the upper sides of the first tin-copper joints, a plurality of copper columns are arranged on the upper sides of the uppermost first RDL layers, tin-copper bumps are arranged on the lowermost first RDL layers and used for welding with the chip-level package, the plurality of copper columns form a mounting area, and a wafer body adhered to the uppermost first RDL layers is arranged in the mounting area.
As a further scheme of the invention, a plurality of first copper bumps which are distributed upwards are arranged on the side surface of the wafer body.
The upper side of the first RDL layer is provided with a first compression molding resin layer covering the outer sides of the wafer body and the copper pillars, the copper pillars and the first copper bumps extend to the outer sides of the first compression molding resin layer, when the wafer body is formed by compression molding resin filling, the wafer body is covered to the outer sides of the copper pillars and the first copper bumps, and then polishing is performed until the copper pillars and the first copper bumps are exposed to the designed thickness.
As a further proposal of the invention, the first RDL layer is adhered to the upper side of the second glass carrier through the second adhesive layer before processing, and the second adhesive layer is dissociated after processing, and the first RDL layer is separated from the second glass carrier.
As a further scheme of the invention, the thickness of the second adhesive layer is uniformly arranged on the upper side of the second glass carrier.
As a further scheme of the invention, the upper side of the first die-pressing resin layer is provided with a plurality of second RDL layers which cover the outer sides of the copper columns and the copper bumps, and the copper bumps are arranged on the upper side of the uppermost second RDL layer.
As a further scheme of the invention, the first RDL layer, the second RDL layer, the third RDL layer and the fourth RDL layer are all plural layers.
As a further scheme of the invention, the chip scale packages and the fan-out packages are the same in number, and the chip scale packages and the fan-out packages are plural.
The invention has the beneficial effects that:
The invention embeds the plurality of chip scale packages in the molding resin, because the coplanarity of the plurality of chip scale packages is not changed by the subsequent process, and because the plurality of chips are packaged in the same package, the volume of the system can be reduced;
And when the chip scale package is processed, a protective tape is stuck on one side of the first glass carrier in the chip scale package, which is far away from the wafer, so that the third glass carrier is protected from being scratched in the process, and the sensor or the display chip on the upper side of the third glass carrier can be protected through the third glass carrier.
Drawings
The invention is further described below with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a finished chip package of the present invention;
FIG. 2 is a cross-sectional view of a fan-out package of the present invention;
FIG. 3 is an assembly flow diagram of a fan-out package of the present invention;
fig. 4 is a schematic diagram of a semi-finished product of a chip package according to the present invention.
1, A first glass carrier; 2, a first adhesive layer, 3, a chip-scale package, 4, a fan-out type package, 41, a first RDL layer, 42, a wafer body, 43, copper columns, 44, a second RDL layer, 45, a first copper bump, 46, a second glass carrier, 47, a second adhesive layer, 48, a first die resin layer, 49, a second copper bump, 5, a second die resin layer, 6, a third RDL layer, 7, a third copper bump.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1-4, the fan-out package structure of the present invention for embedding a sensor or a display chip includes a first glass carrier 1, a plurality of chip scale packages 3 are adhered to an upper side of the first glass carrier 1 through a first adhesive layer 2, after processing, the first adhesive layer 2 is dissociated, the first glass carrier 1 is removed, fan-out packages 4 are mounted on upper sides of the plurality of chip scale packages 3, and a second molding resin layer 5 covering the plurality of first adhesive layers 2 and outer sides of the plurality of chip scale packages 3 is disposed on an upper side of the first glass carrier 1;
the upper side of the chip scale package 3 is provided with tin-copper bumps which are distributed upwards;
The upper side and the lower side of the fan-out type package 4 are respectively provided with a second surface contact and a first surface tin-copper contact, the first surface tin-copper contact is electrically connected with a tin-copper bump of the chip scale package 3 in a welding way, and the upper side of the second surface contact is provided with a plurality of second copper bumps 49 extending to the upper side of the second die resin layer 5;
The upper side of the second molding resin layer 5 is provided with a third RDL layer 6 connected with the second copper bumps 49, the uppermost side of the third RDL layer 6 is provided with a plurality of third copper bumps 7, and tin balls are planted outside the plurality of third copper bumps 7.
The chip scale package 3 includes a third glass carrier, a flip-chip wafer is adhered to the upper side of the third glass carrier, TSVs are fabricated on the back surface of the wafer and serve as signal connections between the upper surface and the lower surface of the chip, a plurality of fourth RDL layers are disposed on one side of the wafer away from the third glass carrier, and tin-copper bumps are disposed on the uppermost side of the plurality of fourth RDL layers.
The third glass carrier in the chip scale package 3 is stuck with a protective tape on the side far away from the wafer during processing, the protective glass carrier is not scratched during processing, and the protective tape is removed after processing.
Referring to fig. 2, the fan-out package 4 includes a plurality of first RDL layers 41 disposed on the upper sides of the first tin-copper contacts, a plurality of copper pillars 43 are disposed on the upper sides of the uppermost first RDL layers 41, the lowermost first RDL layers 41 are provided with tin-copper bumps for soldering with the chip scale package 3, the plurality of copper pillars 43 form a mounting area, and the mounting area is provided with a die body 42 adhered to the uppermost first RDL layers 41.
The side surface of the wafer body 42 is provided with a plurality of first copper bumps 45 which are distributed upwards.
The upper side of the first RDL layer 41 is provided with a first molding resin layer 48 covering the outer sides of the wafer body 42 and the plurality of copper pillars 43, the plurality of copper pillars 43 and the plurality of first copper bumps 45 each extend to the outer sides of the first molding resin layer 48, and when the wafer body 42 is molded by molding resin, the wafer body 42 is covered to the outer sides of the plurality of copper pillars 43 and the plurality of first copper bumps 45, and then the surface is polished until the plurality of copper pillars 43 and the first copper bumps 45 are exposed to a designed thickness.
Before processing, the first RDL layer 41 is adhered to the upper side of the second glass carrier 46 through the second adhesive layer 47, the thickness of the second adhesive layer 47 is uniformly arranged on the upper side of the second glass carrier 46, after processing, the second adhesive layer 47 is dissociated, and the first RDL layer 41 is separated from the second glass carrier 46.
The upper side of the first molding resin layer 48 is provided with a plurality of second RDL layers 44 covering the outer sides of the plurality of copper pillars 43 and the plurality of first copper bumps 45, and a plurality of second copper bumps 49 are provided on the upper side of the uppermost second RDL layer 44.
The first RDL layer 41, the second RDL layer 44, the third RDL layer 6 and the fourth RDL layer are all plural layers.
The number of the chip scale packages 3 and the number of the fan-out packages 4 are the same, and the number of the chip scale packages 3 and the number of the fan-out packages 4 are plural.
The packaging method of the embedded sensor or the display chip comprises the following steps:
The method comprises the steps of manufacturing a chip level package 3, gluing a specific position on the surface of a wafer, reversely bonding the wafer on one side of a third glass carrier, pasting a protective tape on the other side of the third glass carrier, and protecting the third glass carrier from being scratched during the manufacturing process;
manufacturing TSVs on the side surface of the wafer as signal connection of the upper surface and the lower surface of the chip, manufacturing a plurality of fourth RDL layers on one side of the wafer far away from the third glass carrier, and finally electroplating tin-copper bumps at the joint of the uppermost RDL layers;
tearing off the protective tape, cutting the wafer and the third glass carrier into single pieces to obtain a chip scale package 3, and protecting the sensor or the display chip by glass;
Step two, manufacturing a fan-out package 4, namely coating an adhesive on the upper side of a second glass carrier 46 to form a second adhesive layer 47, manufacturing a first tin-copper contact and a plurality of first RDL layers 41 on the upper side of the second adhesive layer 47, arranging a plurality of copper columns 43 on the upper side of the uppermost first RDL layer 41, adhering a wafer body 42, namely a driving chip or a control chip of a sensor or a display, on the upper side of the wafer body 42, arranging a first copper bump 45 on the upper side of the wafer body 42, and pouring a first compression molding resin layer 48 wrapping the copper columns 43 and the outer side of the wafer body 42 on the upper side of the first RDL layer 41;
Grinding the first die resin layer 48, exposing the copper pillars 43 and the first copper bumps 45 to a designed thickness, and adjusting the thickness of the first die resin layer 48 by adjusting the thickness of the first die resin layer;
Manufacturing a plurality of second RDL layers 44 on the upper side of the first molding resin layer 48, wherein the uppermost second RDL layer 44 is a second surface contact, a second copper bump 49 positioned on the upper side of the second surface contact is arranged at the contact of the uppermost second RDL layer 44, then the second adhesive layer 47 is dissociated, the first RDL layer 41 is separated from the second glass carrier 46, the glass carrier is removed, and the fan-out type package 4 is obtained by cutting into single pieces;
Assembling the chip scale package 3 and the fan-out package 4, namely adhering and assembling the third glass of the plurality of chip scale packages 3 and the first glass carrier 1 through the first adhesive layer 2, wherein the plurality of chip scale packages 3 are positioned on the same plane, so that the chip scale packages have good coplanarity, after the chip scale packages 3 are assembled, tin-copper bumps are upwards distributed, the first surface tin-copper joints of the fan-out package 4 are aligned with the tin-copper bumps of the chip scale packages 3, electric conduction is formed by welding, and after the fan-out package 4 is assembled, the second copper bumps 49 of the second surface joints of the fan-out package 4 are upwards;
Step six, processing a second molding resin layer 5 on the outer side of each fan-out type package 4, grinding the second molding resin layer 5, exposing a second copper bump 49 of a second surface joint of the fan-out type package 4 to the designed thickness, manufacturing a plurality of third RDL layers 6 on the side surface of the second molding resin layer 5 and corresponding to the upper side of each fan-out type package 4, arranging a third copper bump 7 at the joint of the third RDL layer 6 on the uppermost layer, and planting tin balls at the third copper bump 7 to obtain an initial product;
Step seven, the first adhesive layer 2 is dissociated, the first glass carrier 1 is removed, the initial product is cut into single pieces, the process of embedding the chip scale packages 3 into the fan-out type packages 4 is completed, the plurality of chip scale packages 3 are embedded into the compression molding resin, preferably, three groups of connected chip scale packages 3 and fan-out type packages 4 are arranged in the single initial product, and good coplanarity of the plurality of chip scale packages 3 cannot be changed due to subsequent processes.
The foregoing describes one embodiment of the present invention in detail, but the description is only a preferred embodiment of the present invention and should not be construed as limiting the scope of the invention. All equivalent changes and modifications within the scope of the present invention are intended to be covered by the present invention.

Claims (8)

1. The fan-out packaging method for embedding the sensor or the display chip is characterized by comprising the following steps of:
firstly, manufacturing a chip scale package (3), and processing a tin-copper bump on the upper side of the chip scale package (3);
Manufacturing a fan-out type package (4), respectively processing a second surface contact and a first surface tin-copper contact on the upper side and the lower side of the fan-out type package (4), and processing a second copper bump (49) on the upper side of the second surface contact;
Adhering and assembling a plurality of chip scale packages (3) and a first glass carrier (1), aligning the tin-copper joints of the first surface of each fan-out package (4) with the tin-copper bumps of the corresponding chip scale packages (3), and welding to form electrical conduction;
Processing a second compression molding resin layer (5) on the outer sides of each chip-scale package (3) and each fan-out package (4), and manufacturing a plurality of third RDL layers (6) corresponding to each fan-out package (4) on the second compression molding resin layer (5);
And fifthly, separating the first glass carrier (1), cutting the plurality of chip-scale packages (3) and the fan-out type packages (4) into a group of units, wherein the single unit internally comprises three groups of assembled chip-scale packages (3) and fan-out type packages (4), and after finishing the process of embedding the chip-scale packages (3) into the fan-out type packages (4), embedding the plurality of chip-scale packages (3) into compression molding resin.
2. The fan-out packaging method of the embedded sensor or the display chip according to claim 1, wherein a third copper bump (7) is arranged at a joint of the uppermost third RDL layer (6) in the fourth step, and a solder ball is planted at the third copper bump (7).
3. The fan-out packaging method of an embedded sensor or display chip according to claim 1, characterized in that the processing method of the fan-out package (4) comprises the following steps:
b1, smearing viscose on the upper side of a second glass carrier (46) to form a second viscose layer (47);
B2, manufacturing a first tin-copper contact and a plurality of first RDL layers (41) on the upper side of the second adhesive layer (47), arranging a plurality of copper columns (43) on the upper side of the uppermost first RDL layer (41), and adhering a wafer body (42) on the upper side of the uppermost first RDL layer (41);
B3, pouring a first compression molding resin layer (48) which is wrapped outside the copper column (43) and the wafer body (42) on the upper side of the first RDL layer (41) by a compression molding;
b4, manufacturing a plurality of second RDL layers (44) on the upper side of the first die resin layer (48), wherein the uppermost second RDL layer (44) is a second surface contact, and a second copper bump (49) positioned on the upper side of the second surface contact is arranged at the contact of the uppermost second RDL layer (44);
b5, dissociating the second adhesive layer (47), separating the first RDL layer (41) from the second glass carrier (46), removing the glass carrier, and cutting into single pieces.
4. A fan-out package structure of a fan-out package method of an embedded sensor or a display chip according to any of claims 1-3, comprising a number of said chip scale packages (3) and a number of fan-out packages (4), characterized in that the upper side of said chip scale packages (3) is provided with upwardly distributed tin-copper bumps;
the upper side and the lower side of the fan-out type package (4) are respectively provided with a second surface contact and a first surface tin-copper contact, and the first surface tin-copper contact is electrically connected with a tin-copper bump of the chip scale package (3) in a welding way;
The outer sides of the plurality of chip scale packages (3) and the plurality of outer fan-out type packages (4) are provided with second compression molding resin layers (5), and the upper sides of the second surface joints are provided with a plurality of second copper bumps (49) extending to the upper sides of the second compression molding resin layers (5);
the upper side of the second die-pressing resin layer (5) is provided with a third RDL layer (6) connected with the second copper bumps (49), the uppermost side of the third RDL layer (6) is provided with a plurality of third copper bumps (7), and tin balls are planted on the outer sides of the plurality of third copper bumps (7).
5. The fan-out package structure of an embedded sensor or a display chip according to claim 4, wherein the fan-out package (4) comprises a plurality of first RDL layers (41) arranged on the upper sides of the first tin-copper contacts, a plurality of copper pillars (43) are arranged on the upper sides of the uppermost first RDL layers (41), tin-copper bumps are arranged on the lowermost first RDL layers (41), and a wafer body (42) adhered to the uppermost first RDL layers (41) is arranged between the plurality of copper pillars (43).
6. The fan-out package structure of an embedded sensor or a display chip according to claim 5, wherein the side of the die body (42) is provided with a plurality of first copper bumps (45) distributed upwards.
7. The fan-out package structure of an embedded sensor or a display chip according to claim 6, wherein the upper side of the first RDL layer (41) is provided with a first molding resin layer (48) covering the outer sides of the die body (42) and the plurality of copper pillars (43), and the plurality of copper pillars (43) and the plurality of first copper bumps (45) each extend to the outer side of the first molding resin layer (48).
8. The fan-out package structure of an embedded sensor or a display chip according to claim 7, wherein the upper side of the first die resin layer (48) is provided with a plurality of second RDL layers (44) covering the outer sides of the plurality of copper pillars (43) and the plurality of first copper bumps (45), and the plurality of second copper bumps (49) are provided with the upper side of the uppermost second RDL layer (44).
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CN112151524A (en) * 2019-06-28 2020-12-29 中芯长电半导体（江阴）有限公司 Packaging structure and packaging method of fan-out type fingerprint identification chip

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