CN114765109A - Method for forming semiconductor structure - Google Patents

Abstract

A method for forming a semiconductor structure comprises the following steps: providing a substrate; forming a gate structure on a substrate; forming grooves in the substrates on two sides of the grid structure, wherein the substrate on the bottom surface of each groove is provided with a first crystal orientation; and forming a source-drain doped layer in the groove by adopting an epitaxial process, wherein the silicon source adopted by the epitaxial process comprises a first silicon source and a second silicon source, the first silicon source is suitable for realizing the selective epitaxial growth of the source-drain doped layer, and the second silicon source is suitable for improving the epitaxial growth rate of the source-drain doped layer along the first crystal direction. In the embodiment of the invention, the second silicon source is suitable for improving the epitaxial growth rate of the source-drain doping layer along the first crystal direction, so that the thickness of the source-drain doping layer positioned at the bottom of the groove is increased, particularly the thickness of the bottom of the source-drain doping layer of the long-channel device is increased, the source-drain contact plug is difficult to penetrate through the source-drain doping layer, the source-drain contact plug is prevented from being contacted with a high-resistance area below the source-drain doping layer, and the electrical property of the semiconductor structure is further improved.

Description

Method of forming a semiconductor structure

technical field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor structure.

Background technique

With the rapid development of semiconductor manufacturing technology, in order to achieve higher computing speed, larger data storage capacity, and more functions, semiconductor devices are developing towards higher component density and higher integration. , Complementary Metal Oxide Semiconductor (Complementary Metal Oxide Semiconductor, CMOS) transistors have become thinner and thinner and shorter than ever. In order to obtain better electrical properties, it is usually necessary to improve the performance of semiconductor devices by controlling the mobility of carriers. A key element in controlling carrier mobility is controlling the stress in the transistor channel to increase the drive current.

As the critical dimension of the device is further reduced, in order to ensure the performance of the device, it is often necessary to use an embedded epitaxial layer in the source and drain regions to change the stress of the channel region, thereby improving the mobility of carriers and improving the performance of the device. For example, for NMOS devices, the N-type source and drain doped regions are etched by grooves and then epitaxially grown with a phosphorus-silicon layer with high phosphorus concentration instead of pure N-type ion implantation. The phosphorus-silicon epitaxial layer can be the channel of the NMOS transistor. The region provides tensile stress, which is beneficial to improve the carrier mobility of the NMOS transistor.

However, the electrical properties of current semiconductor structures still need to be improved.

SUMMARY OF THE INVENTION

The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is beneficial to increase the bottom thickness of the source-drain doped layer, so that the source-drain contact plug is not easy to penetrate the source-drain doped layer and contact the lower high-resistance region, Thereby, the electrical performance of the semiconductor structure is improved.

To solve the above problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a gate structure on the substrate; forming grooves in the substrate on both sides of the gate structure, the The substrate on the bottom surface of the groove has a first crystal orientation; an epitaxy process is used to form a source-drain doped layer in the groove, wherein the silicon source used in the epitaxy process includes a first silicon source and a second silicon source, so The first silicon source is suitable for realizing selective epitaxial growth of the source-drain doped layer, and the second silicon source is suitable for increasing the epitaxial growth rate of the source-drain doped layer along the first crystal direction.

Optionally, the second silicon source is one or more of silane, disilane and trisilane.

Optionally, the first silicon source is dichlorosilane.

Optionally, the epitaxy process is a vapor phase epitaxy process; in the step of forming the source-drain doped layer using the epitaxy process, the ratio of the gas flow rate of the first silicon source and the second silicon source is 10:1 to 20:1.

Optionally, the epitaxy process is a vapor phase epitaxy process; the parameters of the epitaxy process include: the total gas flow rate of the silicon source gas is 100 sccm to 400 sccm.

Optionally, the epitaxy process further includes an impurity source; when forming an NMOS, the impurity source is an N-type impurity source.

Optionally, the N-type impurities include P ions, As ions or Sb ions.

Optionally, the N-type impurities are phosphorus ions, and the impurity source is a phosphorus source; in the step of forming the source-drain doping layer, the material of the source-drain doping layer is a phosphorus silicon layer.

Optionally, the epitaxy process is a vapor phase epitaxy process, and the reactive gas of the epitaxy process includes the first silicon source and the second silicon source, a phosphorus source gas, a carrier gas and an etching gas; the parameters of the epitaxy process include: : The gas flow rate of the phosphorus source gas is 500sccm to 1500sccm, the process temperature is 600℃ to 700℃, the pressure is 100Torr to 300Torr, the gas flow rate of the carrier gas is 2.5slm to 10slm, and the gas flow rate of the corrosion gas is 100sccm to 300sccm.

Optionally, in the step of forming the source-drain doped layer, the doping concentration of phosphorus ions in the source-drain doped layer is 1E21 cm ^-3 to 5E21 cm ^-3 .

Optionally, in the step of forming the source-drain doped layer, the part of the source-drain doped layer at the bottom of the groove is used as a bottom doped layer, and the thickness of the bottom doped layer is equal to the thickness of the groove. 1/6 to 1/2 the width.

Optionally, in the step of forming the source-drain doped layer, a portion of the source-drain doped layer at the bottom of the groove is used as a bottom doped layer, and the thickness of the bottom doped layer is 15 nm to 40 nm.

Optionally, the method for forming the semiconductor structure further includes: forming a source-drain contact plug on the source-drain doped layer in contact with the top surface of the source-drain doped layer.

Optionally, the source-drain contact plug also penetrates a part of the thickness of the source-drain doped layer; the thickness of the source-drain doped layer at the bottom of the source-drain contact plug is 5 nm to 20 nm.

Optionally, after forming the source-drain doped layer and before forming the source-drain contact plug, the method for forming the semiconductor structure further includes: forming an interlayer dielectric layer on the substrate on the side of the gate structure , the interlayer dielectric layer covers the source-drain doped layer; the step of forming the source-drain contact plug includes: forming a contact hole penetrating the interlayer dielectric layer on top of the source-drain doped layer; The source-drain contact plugs in contact with the source-drain doped layers are formed in the contact holes.

Optionally, the first crystal orientation is a <100> crystal orientation.

Optionally, the base of the sidewall of the groove has a second crystal orientation, and the second crystal orientation is a <110> crystal orientation.

Optionally, in the step of forming the groove, the cross section of the groove is a rectangular structure.

Optionally, the step of forming the groove includes: using a dry etching process to etch the substrate with a partial thickness on both sides of the gate structure to form the groove.

Optionally, in the step of providing a base, the base includes a substrate and a fin protruding from the substrate; the gate structure is formed on the substrate and spans the fin, the The gate structure covers part of the top part and part of the sidewall of the fin; the groove is formed in the fin on both sides of the gate structure.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following advantages:

In the method for forming a semiconductor structure provided by the embodiment of the present invention, an epitaxial process is used to form a source-drain doped layer in the groove, wherein the silicon source used in the epitaxial process includes a first silicon source and a second silicon source , the second silicon source is suitable for increasing the epitaxial growth rate of the source-drain doped layer along the first crystal direction, thereby helping to improve the epitaxial growth rate of the source-drain doped layer at the bottom of the groove, Correspondingly, it is beneficial to increase the thickness of the source-drain doped layer at the bottom of the groove, especially to increase the bottom thickness of the source-drain doped layer of the long-channel device. When the source-drain contact plug is in contact with the drain-doped layer, the source-drain contact plug is not easy to penetrate the source-drain doped layer, which is beneficial to ensure that the bottom of the source-drain contact plug still retains at least a partial thickness of the source-drain contact plug. The doped layer prevents the source-drain contact plug from contacting the high-resistance region under the source-drain doped layer, thereby improving the contact performance between the source-drain contact plug and the source-drain doped layer, reducing the contact resistance, and correspondingly helping to improve the Electrical properties of semiconductor structures, such as increased saturation current.

In addition, the first silicon source is suitable for realizing selective epitaxial growth of the source and drain doped layers, which is beneficial to ensure that the epitaxial process can meet the requirements of the selective epitaxial growth of the source and drain doped layers, so as to ensure the source and drain doped layers. While the epitaxial growth selectivity of the drain doped layer is increased, the epitaxial growth rate of the source and drain doped layers at the bottom of the groove is increased, thereby increasing the bottom thickness of the source and drain doped layers.

In addition, in the embodiment of the present invention, the silicon source of the epitaxial process is adjusted to increase the bottom thickness of the source-drain doping layer, so as to avoid improving the source-drain doping layer by adjusting the gate pitch (Pitch) and gate width (CD). The thickness of the bottom is correspondingly beneficial to meet the requirements of the established design rules and to improve compatibility.

Description of drawings

1 to 4 are schematic cross-sectional views corresponding to each step in a method for forming a semiconductor structure;

5 to 11 are cross-sectional schematic diagrams corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

Detailed ways

It can be known from the background art that the performance of the current semiconductor structure still needs to be improved.

In the following, in conjunction with a method for forming a semiconductor structure, the reasons why the performance of the current semiconductor structure still needs to be improved will be analyzed. 1 to 4 are schematic cross-sectional views corresponding to each step in a method for forming a semiconductor structure.

Taking an NMOS transistor as an example, in order to improve the carrier mobility of the NMOS transistor channel, the N-type source and drain doped layers are currently etched with grooves, and then a phosphorous silicon layer with high phosphorus concentration is epitaxially grown in the grooves.

Specifically, as shown in FIG. 1 , a substrate is provided, including a substrate (not shown) and a fin 10 on the substrate, and a polysilicon gate 11 across the fin 10 is formed on the substrate. The polysilicon gate 11 is used as a dummy gate structure to occupy a space for forming a metal gate structure.

As shown in FIG. 2 , grooves 12 are formed in the fins 10 on both sides of the polysilicon gate 11 .

As shown in FIG. 3 , an epitaxial process is used to form a phosphorus-silicon layer 13 in the groove 12 , and the phosphorus-silicon layer 13 is used as a source-drain doped layer.

In order to obtain a high phosphorus concentration, the epitaxial growth of the phosphorus-silicon layer 13 needs to be performed under relatively high pressure, low carrier gas flow rate, and high gas flow rate of silicon source and phosphorus source. Among them, under the condition of higher pressure and lower carrier gas flow rate, usually only dichlorosilane can achieve selective epitaxy (Selective Epitaxial Growth), and other types of silicon sources will lead to the loss of epitaxy selectivity, so Dichlorosilane is currently used as the silicon source for epitaxially growing the phosphorous silicon layer 13 .

With reference to FIG. 3 , under the conditions of relatively high pressure, low carrier gas flow rate, and high gas flow rate of the silicon source and phosphorus source, the epitaxial growth at the bottom of the groove 12 is limited, and the sidewall of the groove 12 is limited. The epitaxial growth plays a leading role. For long-channel devices, the width of the groove 12 is relatively large, and the epitaxial layers formed by epitaxial growth on the sidewalls of the groove 12 are difficult to fuse together, while the epitaxial growth at the bottom of the groove 12 is limited, resulting in phosphorus at the bottom of the groove 12. The thickness t of the silicon layer 13 is insufficient.

Referring to FIG. 4 , when the source-drain contact plug 14 in contact with the source-drain doped layer is formed, since the thickness t of the phosphor-silicon layer 13 at the bottom of the groove 12 is too small, the process of forming the source-drain contact plug 14 The phosphor-silicon layer 13 is easily penetrated, and the source-drain doped layer is below the high-resistance region. The source-drain contact plug 14 penetrates the phosphor-silicon layer 13 and contacts the lower high-resistance region, which will seriously affect the performance of the device.

A current solution to the above problems is to adjust the poly pitch and width (poly CD) of the polysilicon gates of the device, which can shorten the width of the etched grooves to improve the bottom thickness of the phosphorous silicon layer. However, under the established design rules (Design Rule), the polysilicon gate spacing is determined, and the width of the polysilicon gate corresponds to the channel length. Changing the width of the polysilicon gate will have a significant impact on device performance. In the actual process flow , and it is not easy to adjust the value of the polysilicon gate spacing and width.

Therefore, without adjusting the gate spacing and width, how to improve the bottom thickness of the source and drain doped layers has become an urgent problem to be solved.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a gate structure on the substrate; forming grooves in the substrate on both sides of the gate structure, The substrate on the bottom surface of the groove has a first crystal orientation; an epitaxy process is used to form a source-drain doped layer in the groove, wherein the silicon source used in the epitaxy process includes a first silicon source and a second silicon source , the first silicon source is suitable for realizing selective epitaxial growth of the source-drain doped layer, and the second silicon source is suitable for increasing the epitaxial growth rate of the source-drain doped layer along the first crystal direction.

In the method for forming a semiconductor structure provided by the embodiment of the present invention, an epitaxial process is used to form a source-drain doped layer in the groove, wherein the silicon source used in the epitaxial process includes a first silicon source and a second silicon source , the second silicon source is suitable for increasing the epitaxial growth rate of the source-drain doped layer along the first crystal direction, thereby helping to improve the epitaxial growth rate of the source-drain doped layer at the bottom of the groove, Correspondingly, it is beneficial to increase the thickness of the source-drain doped layer at the bottom of the groove, especially to increase the bottom thickness of the source-drain doped layer of the long-channel device. When the source-drain contact plug is in contact with the drain-doped layer, the source-drain contact plug is not easy to penetrate the source-drain doped layer, which is beneficial to ensure that the bottom of the source-drain contact plug still retains at least a partial thickness of the source-drain contact plug. The doped layer prevents the source-drain contact plug from contacting the high-resistance region under the source-drain doped layer, thereby improving the contact performance between the source-drain contact plug and the source-drain doped layer, reducing the contact resistance, and correspondingly helping to improve the Electrical properties of semiconductor structures, such as increased saturation current.

In addition, the first silicon source is suitable for realizing selective epitaxial growth of the source and drain doped layers, which is beneficial to ensure that the epitaxial process can meet the requirements of the selective epitaxial growth of the source and drain doped layers, so as to ensure the source and drain doped layers. While the epitaxial growth selectivity of the drain doped layer is increased, the epitaxial growth rate of the source and drain doped layers at the bottom of the groove is increased, thereby increasing the bottom thickness of the source and drain doped layers.

In addition, in the embodiment of the present invention, the silicon source of the epitaxial process is adjusted to increase the bottom thickness of the source-drain doping layer, so as to avoid improving the source-drain doping layer by adjusting the gate pitch (Pitch) and gate width (CD). The thickness of the bottom is correspondingly beneficial to meet the requirements of the established design rules and to improve compatibility.

In order to make the above objects, features and advantages of the embodiments of the present invention more clearly understood, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

5 to 11 are schematic structural diagrams corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

Referring to Figure 5, a substrate is provided.

The substrate is used to provide a process platform for subsequent processes.

In this embodiment, the substrate is used to form a fin field effect transistor (FinFET) as an example, in the step of providing the substrate, the substrate includes a substrate (not shown) and fins protruding from the substrate Section 100.

In this embodiment, the substrate is a silicon substrate. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate can also be a silicon-on-insulator substrate or an insulator other types of substrates such as germanium substrates. The material of the substrate may be a material suitable for process requirements or easy integration.

The fins 100 are used to provide conductive channels of field effect transistors.

In this embodiment, the material of the fin portion 100 is the same as that of the substrate, and the material of the fin portion 100 is silicon. In other embodiments, the material of the fins may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium and other semiconductor materials suitable for forming fins, and the materials of the fins may also be the same as The materials of the substrates are different.

Continuing to refer to FIG. 5, a gate structure 110 is formed on the substrate.

In this embodiment, the gate structure 110 is used as a dummy gate structure for occupying a space for forming a metal gate structure.

In this embodiment, the gate structure 110 is formed on the substrate and spans the fin 100 , and the gate structure 110 covers part of the top and part of the sidewall of the fin 100 .

In this embodiment, the gate structure 110 includes a dummy gate oxide layer (not shown) and a dummy gate layer (not shown) on the dummy gate oxide layer.

In this embodiment, the gate structure 110 is a polysilicon gate (Poly gate) structure. Correspondingly, the material of the dummy gate oxide layer is silicon oxide or silicon oxynitride. In this embodiment, the material of the dummy gate layer is polysilicon.

In this embodiment, the substrate is used for forming long-channel devices, so the interval between adjacent gate structures 110 is also relatively large.

In this embodiment, in the step of forming the gate structure 110 , a gate mask layer (not shown) is further formed on the top of the gate structure 110 . The gate mask layer is used as an etching mask when the gate structure 110 is formed, and the gate mask layer can also protect the top of the gate structure 110 during the formation of the semiconductor structure.

In this embodiment, the material of the gate mask layer is silicon nitride.

In this embodiment, after the gate structure 110 is formed, the method for forming the semiconductor structure further includes: forming spacers 120 on the sidewalls of the gate structure 110 .

The sidewall spacers 120 are used to protect the sidewalls of the gate structure 110 , and the sidewall spacers 120 are also used to define the formation regions of the source and drain doped layers.

The material of the spacer 120 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonitride, silicon oxycarbide, boron nitride and boron carbonitride. The sidewall 120 may be a single-layer structure or a laminated structure.

In this embodiment, the sidewall spacer 120 is an ONO (Oxide-Nitride-Oxide, oxide-nitride-oxide) structure, and the sidewall spacer 120 includes a first silicon oxide layer and is located in the first silicon oxide layer. A silicon nitride layer on the sidewalls and a second silicon dioxide layer on the sidewalls of the silicon nitride layer.

Referring to FIG. 6 , grooves 130 are formed in the substrate on both sides of the gate structure 110 , and the substrate on the bottom surface of the groove 130 has a first crystal orientation.

The grooves 130 are used to provide a space for forming the source and drain doped layers.

In this embodiment, the grooves 130 are formed in the fins 100 on both sides of the gate structure 110 and the spacers 120 .

In this embodiment, the substrate is used to form a long-channel device, and the interval between adjacent gate structures 110 is relatively large, so the width of the groove 130 is relatively large.

In this embodiment, in the step of forming the groove 130, the cross-section of the groove 130 is a rectangular structure, that is, the bottom surface of the groove 130 is parallel or approximately parallel to the surface of the substrate, and the groove 130 The sidewalls are perpendicular or approximately perpendicular to the substrate surface.

In this embodiment, the first crystal orientation is the <100> crystal orientation. Specifically, in this embodiment, the substrate used is usually a substrate with a <100> crystal orientation, and the bottom surface of the groove 130 is parallel or approximately parallel to the substrate surface. Therefore, the substrate on the bottom surface of the groove 130 also has first crystal orientation.

Correspondingly, in this embodiment, since the sidewall of the groove 130 is perpendicular or approximately perpendicular to the surface of the substrate, the substrate of the sidewall of the groove 130 has a second crystal orientation, and the second crystal orientation is <110> crystal orientation.

In this embodiment, the step of forming the groove 130 includes: using a dry etching process (eg, an anisotropic dry etching process) to etch the thickness of the two sides of the gate structure 110 base, forming the groove 130 . Specifically, a dry etching process is used to etch the fins 100 with a partial thickness on both sides of the gate structure 110 .

The dry etching process has the characteristics of anisotropic etching, that is, the longitudinal etching rate is greater than the lateral etching rate, which is beneficial to improve the controllability of the profile of the groove 130, which is further beneficial to make the profile of the groove 130. meet process requirements. Specifically, the dry etching process is beneficial to make the groove 130 have a cross-sectional shape of a rectangular structure.

Referring to FIG. 7 , a source-drain doped layer 200 is formed in the groove 130 by an epitaxial process, wherein the silicon source used in the epitaxial process includes a first silicon source and a second silicon source, and the first silicon source Suitable for realizing selective epitaxial growth of the source-drain doped layer 200 , the second silicon source is suitable for increasing the epitaxial growth rate of the source-drain doped layer 200 along the first crystal direction.

When the device is in operation, the source-drain doping layer 200 is used to provide a carrier source. In this embodiment, the source-drain doping layer 200 is also used to provide stress to the channel, thereby improving the mobility of carriers.

In this embodiment, the silicon source used in the epitaxy process includes a first silicon source and a second silicon source, and the second silicon source is suitable for improving the epitaxial growth of the source-drain doping layer 200 along the first crystal direction Therefore, it is beneficial to increase the epitaxial growth rate of the source-drain doped layer 200 at the bottom of the groove 130 , which is beneficial to increase the thickness of the source-drain doped layer 200 at the bottom of the groove 130 , especially It is to increase the bottom thickness of the source-drain doped layer 200 of the long-channel device. When the source-drain contact plug is subsequently formed on the source-drain doped layer 200 in contact with the source-drain doped layer 200, the source-drain contact plug The plug is not easy to penetrate the source-drain doped layer 200 , which is beneficial to ensure that the bottom of the source-drain contact plug still retains at least a partial thickness of the source-drain doped layer 200 , and prevents the source-drain contact plug from being below the source-drain doped layer 200 . The high-resistance regions are contacted, thereby improving the contact performance between the source-drain contact plug and the source-drain doped layer 200, reducing the contact resistance, and correspondingly improving the electrical performance of the semiconductor structure, such as increasing the saturation current.

In particular, in this embodiment, for a long-channel device, the width of the groove 130 is relatively large, the bottom area of the groove 130 is relatively large, and the growth of the source-drain doped layer 200 in the groove 130 is limited. The problem is more obvious. In this embodiment, by using the first silicon source and the second silicon source together as the silicon source, it is beneficial to significantly increase the bottom thickness of the source-drain doped layer 200 of the long-channel device, thereby significantly improving the long-channel device. performance of the device.

In addition, the first silicon source is suitable for realizing selective epitaxial growth of the source-drain doped layer 200 , which is beneficial to ensure that the epitaxial process can meet the requirements of the selective epitaxial growth of the source-drain doped layer 200 , so that the While ensuring the epitaxial growth selectivity of the source-drain doped layer 200 , the epitaxial growth rate of the source-drain doped layer 200 at the bottom of the groove 130 is increased, thereby increasing the bottom thickness of the source-drain doped layer 200 .

In this embodiment, the epitaxy process is a selective epitaxy process. The selective epitaxy process utilizes the basic principle of epitaxial growth and the characteristics that silicon is difficult to nucleate into a film on an insulator, so that epitaxial growth can be performed only in a specific region of the semiconductor structure. Specifically, in this embodiment, the exposed silicon of the semiconductor structure is only the bottom surface and sidewall of the groove 130 , so that the epitaxy process can selectively grow in the groove 130 .

In addition, in this embodiment, the silicon source of the epitaxial process is adjusted to increase the bottom thickness of the source-drain doping layer 200, so as to avoid improving the source-drain doping layer by adjusting the gate pitch (Pitch) and gate width (CD). The bottom thickness of 200 is correspondingly beneficial to make the gate spacing and gate width meet the requirements of the established design rules, and is beneficial to improve compatibility.

Compared with the solution in which the source and drain doped regions are formed by ion implantation into the substrate, in this embodiment, the source and drain doped layers 200 are formed in the grooves 130 by an epitaxial process, which is favorable for in-situ doping during the epitaxial process. Therefore, the source-drain doped layer 200 with higher doping concentration is obtained, and at the same time, it is also beneficial to avoid the damage to the device caused by ion implantation. In addition, after the source-drain doped layer 200 is formed in this embodiment, heat treatment is usually performed. In order to activate the doping ions in the source-drain doped layer 200, compared with the solution of forming the source-drain doped regions by ion implantation, the heat treatment in this embodiment does not require additional heat energy to repair the crystal lattice damaged by the ion implantation. , which is beneficial to reduce the energy consumption (eg temperature, time) of the heat treatment.

In this embodiment, the first silicon source is dichlorosilane (SiH ₂ Cl ₂ ). In the semiconductor field, under relatively high pressure and low carrier gas content, dichlorosilane can usually achieve selective epitaxial growth (Selective Epitaxial Growth). Therefore, by making the first silicon source dichlorosilane, it is beneficial to ensure the epitaxial process. The requirements for selective epitaxy of the source-drain doped region layer 200 can be met.

Specifically, during the epitaxial process, an etching gas (eg, HCl) is also introduced at the same time, so as to remove the epitaxial material formed on the undesired area (eg, the insulating material). Compared with other types of silicon sources, when using dichlorosilane as the silicon source, the epitaxial growth rate of silicon is relatively slow, which is beneficial to improve the controllability of epitaxial growth and ensure that the etching gas can remove the silicon formed on the undesired area. The epitaxial material is removed, which is beneficial to improve the selectivity of the epitaxial process.

In addition, compared with other types of silicon sources, under relatively high pressure and low carrier gas flow, when using dichlorosilane as the silicon source, the epitaxial growth rate of silicon on the second crystal orientation <110> is greater than The growth rate on the first crystal direction <100>, therefore, when the epitaxial process uses dichlorosilane as a single silicon source, the growth rate of the source-drain doped layer 200 on the sidewall of the groove 130 is greater than that on the bottom of the groove 130 growth rate.

Therefore, in this embodiment, a second silicon source is added together with the first silicon source as a silicon source, and the second silicon source is used to increase the growth rate of the source-drain doped layer 200 at the bottom of the groove 130 . When only the first silicon source is used in the epitaxial process, the bottom thickness T of the source-drain doped layer 200 is likely to be insufficient; when only the second silicon source is used in the epitaxial process, the selectivity of the epitaxial growth cannot satisfy the source-drain doped layer. 200 needs. In this embodiment, the first silicon source and the second silicon source are jointly used as the silicon source for epitaxial growth when forming the source-drain doped layer 200 , so that the source-drain doped layer 200 can be changed at the same time as the selective epitaxy requirement is met. The growth morphology in the groove 130 increases the bottom thickness T of the source-drain doped layer 200 .

In this embodiment, the second silicon source is one or more of silane (SiH ₄ ), disilane (Si ₂ H ₆ ) and trisilane (Si ₃ H ₈ ).

As an example, the second silicon source is silane. Under certain temperature and pressure conditions, compared with dichlorosilane, silane is more favorable for the growth of silicon along the <100> crystal direction, so that the use of the silane epitaxy process is favorable for the growth of the source-drain doped layer 200 at the bottom of the groove 130 Thicker.

In this embodiment, the epitaxy process is a vapor phase epitaxy process, and the silicon source used is correspondingly a silicon source gas source.

In this embodiment, in the step of forming the source-drain doped layer 200 by an epitaxy process, the ratio of the gas flow rates of the first silicon source and the second silicon source should not be too small or too large. If the ratio of the gas flow rates of the first silicon source and the second silicon source is too small, the second silicon source will be too much, which will easily reduce the selectivity of epitaxial growth; If the ratio of the gas flow rate is too large, the second silicon source is relatively too small, and the effect of improving the bottom thickness of the source-drain doping layer 200 is easily reduced. Therefore, in this embodiment, in the step of forming the source-drain doped layer 200 by an epitaxy process, the ratio of the gas flow rates of the first silicon source and the second silicon source is 10:1 to 20:1.

In this embodiment, since the first silicon source and the second silicon source are used together as the silicon source, the total flow rate of the silicon source gas can be appropriately adjusted during the epitaxy process; in this embodiment, the epitaxy process The parameters include: the total gas flow of the silicon source gas is 100 sccm to 400 sccm.

In this embodiment, the epitaxy process further includes an impurity source, and the impurity source is used for doping ions in the source-drain doped layer 200 during the epitaxy process.

In this embodiment, when an NMOS is formed, the impurity source is an N-type impurity source. In this embodiment, the substrate is used to form the NMOS transistor. Compared with the PMOS device, in order to make the source and drain doped layer 200 of the NMOS transistor have a higher doping concentration, the epitaxial process for forming the source and drain doped layer 200 needs to be relatively Under higher pressure, lower carrier gas volume, and higher flow rate of silicon source and phosphorus source gas, under such conditions, the epitaxial growth rate at the bottom of the groove 130 is obviously limited. Using the first silicon source and the second silicon source together as the silicon source is beneficial to significantly improve the performance of the NMOS device. In particular, the performance of N-type long-channel devices is significantly improved.

In this embodiment, the N-type impurities include P ions, As ions or Sb ions.

As an example, the N-type impurities are phosphorus ions, and the impurity source is correspondingly a phosphorus source.

Correspondingly, in the step of forming the source-drain doped layer, the material of the source-drain doped layer 200 is a phosphor-silicon layer. In order to obtain a phosphorus-silicon layer with a higher phosphorus ion doping concentration, the epitaxy process of the source-drain doping layer 200 needs to be performed under relatively high pressure, low carrier gas flow rate, and high silicon source and phosphorus source gas flow rates , so that the present embodiment can significantly increase the growth rate of the phosphorus-silicon layer at the bottom of the groove 130 , which is beneficial to significantly increase the thickness of the phosphorus-silicon layer at the bottom of the groove 130 .

As an example, the phosphorus source is phosphine.

In other embodiments, when the N-type impurities are other types of ions, the impurity source is correspondingly other types of gas sources. For example: when the N-type impurity is As ion, the impurity source is correspondingly arsenic source, and the arsenic source includes arsine (AsH ₃ ); when the N-type impurity is Sb ion, the impurity source is correspondingly antimony source, antimony source Sources may include trimethyl antimony (Sb(CH ₃ ) ₃ ) and triethyl antimony (Sb(C ₂ H ₅ ) ₃ ).

In this embodiment, the epitaxy process is a vapor phase epitaxy process; the reactive gas of the epitaxy process includes the first silicon source and the second silicon source, a phosphorus source gas, a carrier gas and an etching gas.

Among them, although the epitaxial process utilizes the characteristics that silicon is difficult to nucleate and form a film on the insulator to achieve selective epitaxy, in the actual epitaxial process, it is still possible to epitaxially grow on the insulating material to form a thinner epitaxial material. The etching gas is used to etch the epitaxial material during the epitaxial process, so as to remove the epitaxial material formed on the undesired area, while the epitaxial material located in the groove 130 is thicker and is only etched under the action of the etching gas A small thickness is etched so that it can be reserved as the source-drain doped layer 200 .

In this embodiment, the parameters of the epitaxy process include: the gas flow rate of the phosphorus source gas is 500 sccm to 1500 sccm, the process temperature is 600 ℃ to 700 ℃, the pressure is 100 Torr to 300 Torr, and the gas flow rate of the carrier gas is 2.5 slm (standard litre per minute, standard liters per minute) to 10slm, the gas flow rate of the corrosive gas is 100sccm to 300sccm.

During the epitaxy process, the gas flow of the phosphorus source gas affects the doping concentration of phosphorus ions in the source-drain doping layer 200. Therefore, in order to ensure that the doping concentration of phosphorus ions in the source-drain doping layer 200 can meet the requirements of the process Requirements, in this embodiment, the gas flow rate of the phosphorus source gas is 500 sccm to 1500 sccm.

During the epitaxy process, the process temperature should not be too low, otherwise the growth rate of the source-drain doped layer 200 will be easily reduced; however, the process temperature should not be too high, otherwise it will easily cause damage to the device and produce side effects, and excessively high temperature will also It is easy to cause the concentration in the source-drain doping layer 200 to decrease, and also to deteriorate the selectivity of the epitaxial process. Therefore, in this embodiment, the process temperature of the epitaxy process is 600°C to 700°C.

During the epitaxy process, the pressure should not be too low, otherwise the growth rate of the source-drain doped layer 200 may be too slow, and the doping concentration of the source-drain doped layer 200 may also be easily affected; however, the pressure of the epitaxy process is also It should not be too high, otherwise it will easily lead to problems such as poor selectivity of epitaxial growth and shortened life of epitaxial process equipment. Therefore, in this embodiment, the pressure of the epitaxy process is 100 Torr to 300 Torr.

During the epitaxy process, the gas flow rate of the carrier gas should not be too low, otherwise the selectivity of the epitaxial growth will be deteriorated, and the uniformity of the epitaxial growth will easily be reduced; the gas flow rate of the carrier gas should not be too high, otherwise it will easily reduce the silicon The ratio of the source gas or the impurity source to the total flow of the reaction gas may further affect the epitaxial growth rate, or easily reduce the doping concentration of the source-drain doping layer 200 . Therefore, in this embodiment, the gas flow rate of the carrier gas is 2.5slm to 10slm.

In this embodiment, during the epitaxy process, the carrier gas is nitrogen. In other embodiments, the carrier gas can also be hydrogen.

During the epitaxy process, the gas flow rate of the etching gas should not be too low, otherwise it will easily increase the risk of epitaxial material residues in undesired areas; however, the gas flow rate of the etching gas should not be too high, otherwise the rate of epitaxial growth will easily be reduced . Therefore, in this embodiment, the gas flow rate of the etching gas is 100 sccm to 300 sccm. In this embodiment, the corrosive gas is HCl.

In this embodiment, in the step of forming the source-drain doped layer 200 by setting the parameters of the epitaxial process within the above range, the doping concentration of phosphorus ions in the source-drain doped layer 200 is 1E21cm ⁻³ to 5E21cm ^-3 .

In this embodiment, in the step of forming the source-drain doped layer 200 , the portion of the source-drain doped layer 200 located at the bottom of the groove 130 is used as the bottom doped layer 210 .

In this embodiment, the thickness of the bottom doped layer 210 is one-sixth to one-half of the width of the groove 130 under the condition that the parameters of the epitaxial process are set within the aforementioned ranges.

As an example, the thickness of the bottom doped layer 210 is 15 nm to 40 nm.

In this embodiment, compared with the prior art, the thickness of the bottom doped layer 210 is twice that of the prior art, thereby significantly increasing the thickness of the bottom doped layer 210 .

In this embodiment, the portion of the source-drain doped layer 200 at the bottom of the groove 130 is used as the side doped layer 220 .

Referring to FIG. 8 , after the source-drain doped layer 200 is formed, the method for forming the semiconductor structure further includes: forming an interlayer dielectric layer 140 on the substrate at the side of the gate structure 110 , the interlayer dielectric The layer 140 covers the source-drain doped layer 200 .

The interlayer dielectric layer 140 is used to achieve electrical isolation between adjacent devices. Subsequent steps further include: forming source-drain contact plugs on the source-drain doped layer 200 in contact with the top surface of the source-drain doped layer 200 , and the interlayer dielectric layer 140 is also used to realize the source-drain contact plugs Electrical isolation from other electrical connection structures.

The material of the interlayer dielectric layer 140 is an insulating material.

In this embodiment, the material of the interlayer dielectric layer 140 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be other dielectric materials such as silicon nitride or silicon oxynitride.

Referring to FIG. 9 , in this embodiment, the gate structure 110 is a dummy gate structure. Therefore, after forming the interlayer dielectric layer 140 , the method for forming the semiconductor structure further includes: removing the gate structure 110 , and forming the interlayer dielectric layer 140 . A gate opening (not shown) is formed in the dielectric layer 140 ; a metal gate structure 170 is formed in the gate opening.

The metal gate structure 170 is used as a device gate structure, and when the device is working, the metal gate structure 170 is used to control the opening and closing of the field effect conduction channel.

In this embodiment, the metal gate structure 170 includes a gate dielectric layer (not shown), a work function layer (not shown) on the gate dielectric layer, and a gate electrode layer (not shown) on the work function layer. not shown).

In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer. The material of the high-k gate dielectric layer is a high-k dielectric material; wherein, the high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer is HfO ₂ . In other embodiments, the material of the high-k gate dielectric layer may also be selected from ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al ₂ O ₃ and the like.

The work function layer is used to adjust the work function of the metal gate structure 170, thereby adjusting the threshold voltage of the device. When forming a PMOS device, the work function layer is a P-type work function layer, and the material of the P-type work function metal includes one or more of TiN, Ta, TaN, TaSiN and TiSiN; when forming an NMOS device , the work function layer is an N-type work function layer, and the material of the N-type work function metal includes one or more of TiAl, TaAlN, TiAlN, MoN, TaCN and AlN.

The material of the gate electrode layer is Al, Cu, Ag, Au, Pt, Ni, Ti or W. In this embodiment, the material of the gate electrode layer is W.

Referring to FIGS. 10 to 11 , the method for forming the semiconductor structure further includes: forming a source-drain contact plug 160 on the source-drain doped layer 200 in contact with the top surface of the source-drain doped layer 200 .

The source-drain contact plugs 160 are used to realize electrical connection between the source-drain doped layer 200 and external circuits or other interconnect structures.

It can be seen from the foregoing description that the method for forming a semiconductor structure provided in this embodiment is beneficial to increase the thickness of the source-drain doping layer 200 located at the bottom of the groove 130 , especially to increase the source-drain doping of long-channel devices The thickness of the bottom of the impurity layer 200 is low. Therefore, when the source-drain contact plug 160 is formed on the source-drain impurity layer 200 in contact with the source-drain impurity layer 200 , the source-drain contact plug 160 cannot easily penetrate the source and drain. The doped layer 200 is beneficial to ensure that at least a partial thickness of the source-drain doped layer 200 remains at the bottom of the source-drain contact plug 160 and prevent the source-drain contact plug 160 from contacting the high-resistance region under the source-drain doped layer 200 , which is beneficial to improve the contact performance between the source-drain contact plug 160 and the source-drain doped layer 200 , reduce the contact resistance, and correspondingly help to improve the electrical performance of the semiconductor structure, such as increasing the saturation current.

Specifically, the source-drain doped layer 200 is a highly doped region, and accordingly, the source-drain doped layer 200 has higher ion concentration and lower resistance. This embodiment is beneficial to ensure the source-drain contact insertion. The bottom of the plug 160 still retains at least a partial thickness of the source-drain doped layer 200, so as to ensure that the source-drain contact plug 160 is in contact with the highly doped region, which is correspondingly beneficial to reduce the source-drain contact plug 160 and the source-drain doped layer. The contact resistance of 200 improves the performance of the semiconductor structure, especially the electrical performance of the long-channel device.

In this embodiment, the material of the source-drain contact plug 160 is a conductive material. As an example, the material of the source-drain contact plug 160 is W. In other embodiments, the material of the source-drain contact plug may also be a conductive material such as Al, Cu, Ag, or Au.

In this embodiment, in order to ensure that the source-drain contact plug 160 can be in contact with the source-drain doped layer 200 , the process of forming the source-drain contact plug 160 may also perform over-etching (Over Etch, OE). The source-drain contact plug 160 also penetrates part of the thickness of the source-drain doped layer 200 .

In this embodiment, based on the thickness of the bottom doped layer 210 and the amount of over-etching when forming the source-drain contact plug 160, the thickness of the source-drain doped layer 200 at the bottom of the source-drain contact plug 160 is 5 nm to 20 nm, so that a sufficient thickness of the source-drain doped layer 200 remains at the bottom of the source-drain contact plug 160 .

In this embodiment, the step of forming the source-drain contact plug 160 includes: as shown in FIG. 10 , forming a contact hole 150 penetrating the interlayer dielectric layer 140 on top of the source-drain doped layer 200 ; as shown in FIG. 11 , As shown, source-drain contact plugs 160 are formed in the contact holes 150 in contact with the source-drain doped layer 200 .

Wherein, in the step of forming the contact hole 150, in order to ensure that the source-drain doped layer 200 can be exposed, a certain amount of over-etching (Over Etch) is also performed. The same amount of over-etching in the contact hole etching process Basically the same, in this embodiment, the thickness of the bottom of the source-drain doped layer 200 is increased, thereby reducing the probability that the bottom of the source-drain doped layer 200 is etched through the over-etching, thereby helping to ensure that the bottom of the contact hole 150 still retains The source-drain doped layer 200 is partially thick, so that the source-drain contact plug 160 stays in the source-drain doped layer 200 and contacts the source-drain doped layer 200 .

In this embodiment, the process of forming the contact hole 150 includes a dry etching process.

In this embodiment, the process of forming the source-drain contact plug 160 in the contact hole 150 includes one or more of a chemical vapor deposition process, a physical vapor deposition process, and an electrochemical plating process.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:

providing a substrate;

forming a gate structure on the substrate;

forming grooves in the substrates on two sides of the grid structure, wherein the substrate on the bottom surface of each groove is provided with a first crystal direction;

and forming a source-drain doped layer in the groove by adopting an epitaxial process, wherein the silicon source adopted by the epitaxial process comprises a first silicon source and a second silicon source, the first silicon source is suitable for realizing the selective epitaxial growth of the source-drain doped layer, and the second silicon source is suitable for improving the epitaxial growth rate of the source-drain doped layer along the first crystal direction.

2. The method of forming a semiconductor structure of claim 1, wherein the second silicon source is one or more of silane, disilane, and trisilane.

3. The method of forming a semiconductor structure of claim 1, wherein the first silicon source is dichlorosilane.

4. The method of forming a semiconductor structure of claim 1, wherein the epitaxial process is a vapor phase epitaxial process; in the step of forming the source-drain doping layer by using an epitaxial process, the gas flow ratio of the first silicon source to the second silicon source is 10:1 to 20: 1.

5. The method of forming a semiconductor structure of claim 1, wherein the epitaxial process is a vapor phase epitaxial process; the parameters of the epitaxial process comprise: the total gas flow of the silicon source gas is 100sccm to 400 sccm.

6. The method of forming a semiconductor structure of claim 1, wherein the epitaxial process further comprises an impurity source; when forming the NMOS, the impurity source is an N-type impurity source.

7. The method of forming a semiconductor structure according to claim 6, wherein the N-type impurity includes P ions, As ions, or Sb ions.

8. The method of forming a semiconductor structure according to claim 6, wherein the N-type impurity is a phosphorus ion, and the impurity source is a phosphorus source; in the step of forming the source-drain doped layer, the source-drain doped layer is made of a phosphorus silicon layer.

9. The method of forming a semiconductor structure of claim 8, wherein the epitaxial process is a vapor phase epitaxy process, and wherein the reaction gases of the epitaxial process include the first and second silicon sources, a phosphorous source gas, a carrier gas, and an etch gas;

The parameters of the epitaxial process comprise: the gas flow rate of the phosphorus source gas is 500sccm to 1500sccm, the process temperature is 600 ℃ to 700 ℃, the pressure is 100Torr to 300Torr, the gas flow rate of the carrier gas is 2.5slm to 10slm, and the gas flow rate of the etching gas is 100sccm to 300 sccm.

10. The method for forming the semiconductor structure according to claim 8, wherein in the step of forming the source-drain doping layer, the doping concentration of phosphorus ions in the source-drain doping layer is 1E21cm^-3To 5E21cm^-3。

11. The method for forming a semiconductor structure according to claim 1, wherein in the step of forming the source and drain doping layers, a portion of the source and drain doping layers located at the bottom of the groove is used as a bottom doping layer, and a thickness of the bottom doping layer is one sixth to one half of a width of the groove.

12. The method for forming the semiconductor structure according to claim 1, wherein in the step of forming the source and drain doping layers, a portion of the source and drain doping layers located at the bottom of the groove is used as a bottom doping layer, and the thickness of the bottom doping layer is 15nm to 40 nm.

13. The method of forming a semiconductor structure of claim 1, further comprising: and forming a source-drain contact plug which is contacted with the top surface of the source-drain doping layer on the source-drain doping layer.

14. The method for forming a semiconductor structure according to claim 13, wherein the source drain contact plug further penetrates through a portion of the thickness of the source drain doping layer; the thickness of the source drain doping layer at the bottom of the source drain contact plug is 5nm to 20 nm.

15. The method for forming a semiconductor structure according to claim 13, wherein after the forming of the source-drain doping layer and before the forming of the source-drain contact plug, the method for forming a semiconductor structure further comprises: forming an interlayer dielectric layer on the substrate at the side part of the grid structure, wherein the interlayer dielectric layer covers the source-drain doping layer;

the step of forming the source-drain contact plug comprises the following steps: forming a contact hole penetrating through the interlayer dielectric layer at the top of the source drain doping layer; and forming the source-drain contact plug in contact with the source-drain doping layer in the contact hole.

16. The method of forming a semiconductor structure of claim 1, wherein the first crystal orientation is a <100> crystal orientation.

17. The method of claim 1, wherein a base of the recess sidewalls has a second crystal orientation, the second crystal orientation being a <110> crystal orientation.

18. The method of forming a semiconductor structure according to claim 1, wherein in the step of forming the recess, a cross section of the recess has a rectangular shape.

19. The method of forming a semiconductor structure of claim 1, wherein the step of forming the recess comprises: and etching the substrate with the thickness of the two side parts of the grid structure by adopting a dry etching process to form the groove.

20. The method of claim 1, wherein in the step of providing a base, the base comprises a substrate and a fin protruding from the substrate;

the grid electrode structure is formed on the substrate and stretches across the fin part, and the grid electrode structure covers part of the top and part of the side wall of the fin part;

the grooves are formed in the fin portions on two sides of the gate structure.

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