CN114827497A - Image sensor, method of operating image sensor - Google Patents

Abstract

The present invention provides an image sensor and an operating method of the image sensor, the image sensor including: the pixel unit comprises at least one row of pixel units, a row driving circuit and a row decoding and holding circuit, wherein the row driving circuit corresponds to the row pixel units and is suitable for driving the photodiodes in the pixel units in the corresponding row to reset according to a reset row address; the row decode hold circuit is adapted to decode and hold the row address of the pixel cells to control the row drive circuit so that the photodiodes in a plurality of rows of pixel cells are simultaneously reset. According to the invention, the photodiodes in the multi-line image sensor can be simultaneously reset, so that compared with the traditional reset operation method, the time is greatly saved, and the frame rate of the image sensor can be obviously improved.

Description

Image sensor, operation method of image sensor

technical field

The present invention relates to the technical field of image sensors, and in particular, to an image sensor and an operation method of the image sensor.

Background technique

The general pixel unit structure is shown in Figure 1. A pixel unit includes a photodiode D1, a transfer transistor MTX, a floating diffusion FD, a reset transistor MRST, an amplifier (source follower) MSF and a strobe transistor. MSEL. The signal TX drives the gate of the transmission transistor MTX, the signal RST drives the gate of the reset transistor MRST, and the signal SEL drives the gate of the strobe transistor MSEL.

The reset operation process of the photodiode D1 in the pixel unit is: first, the signal RST changes from low to high, the reset transistor MRST is turned on, and the floating diffusion FD is reset to VDD; then the signal RST becomes low, and the reset transistor MRST is turned off; then When the signal TX changes from low to high, the transmission tube MTX is turned on, and all the electrons accumulated in the photodiode D1 are transferred to the floating diffusion area FD; finally, the signal TX becomes low, and the transmission tube MTX is turned off. In this way, the reset operation of the photodiode D1 in the pixel unit is completed.

Due to the performance requirements of image sensors, photodiodes in multi-row pixel units need to be reset.

In a conventional image sensor, the photodiodes in the multi-row pixel units are reset in time division (serial), that is, the photodiodes in the multi-row pixel units are reset row by row in sequence. Figure 2 is a timing diagram of a conventional image sensor row operation, in which ADDR<10:0> is a row address signal (take an 11-bit row address code as an example), and RSEL, RG, and TG are row input signals. RSEL is used to generate the signal SEL, RG is used to generate the signal RST, TG is used to generate the signal TX; T1 is the time for the photodiode in the pixel unit of the reset row to complete a single reset operation, and T2 is the photodiode in the pixel unit of the read row j When the readout operation is completed, the photodiode reset operation in the pixel units of the reset rows 1, m, and n is performed time-divisionally (serially). Take the number of reset rows as 3 as an example, because the time for the photodiode to complete a reset operation is T1, and the photodiode reset operation in the 3-row pixel unit is performed in time division, and the photodiode in the 3-row pixel unit completes the reset operation. , the time required is 3T1.

Therefore, the time-division (serial) reset operation of the photodiodes in the multi-row pixel units of the traditional image sensor will limit the improvement of the frame rate of the image sensor.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide an image sensor and an operation method thereof to solve the technical problem that the time-division (serial) reset operation of the photodiodes in the multi-row pixel units of the traditional image sensor will limit the frame rate of the image sensor.

In order to solve the above technical problems, the technical solution of the present invention provides an image sensor, comprising: at least one row of pixel units, a row driving circuit and a row decoding and holding circuit; the row driving circuit corresponds to the row pixel unit and is suitable for The photodiode in the pixel unit of the corresponding row is driven to reset according to the reset row address; the row decoding and holding circuit is adapted to decode the row address of the pixel unit and keep its state, so as to control the row driving circuit so that The photodiodes in multiple rows of pixel cells are reset simultaneously.

Preferably, the row decoding and holding circuit includes a decoding unit and at least one state holding unit; the decoding unit is suitable for decoding the reset row address; the state holding unit is suitable for decoding according to the decoding unit The decoding result is set to control the row driving circuit, so as to reset the photodiodes in the pixel units of multiple rows at the same time, save the reset time of multiple rows, and improve the frame rate.

Preferably, the decoding unit includes a series-connected reset circuit, a decoding enabling unit and a decoding logic unit;

The reset circuit is adapted to reset the state of the state holding unit before decoding the target row address;

The decoding enable unit is adapted to provide an enable signal to the decoding logic unit;

The decoding logic unit is adapted to decode the row address code signal ADDR<n-1:0>, and output the decoding result to the state holding unit;

The state holding unit is adapted to hold the decoding result of the decoding unit until the next reset circuit resets it.

One end of the decoding logic unit is grounded, and the other end is connected to the decoding enabling unit, and the decoding logic unit is n series-connected NMOS transistors, n is a natural number, and the gates of the n series-connected NMOS transistors The row address code signals ADDR<n-1:0> are respectively connected in one-to-one correspondence.

Preferably, the decoding enabling unit is an NMOS transistor N _n connected in series with the decoding logic unit.

Preferably, the decoding enabling unit is connected to the first end of the reset circuit, the second end of the reset circuit is connected to VDD, the third end of the reset circuit is a control end, and the third end of the reset circuit Accepts row address reset signal.

Preferably, the reset circuit is a PMOS, the gate of the PMOS is connected to the output terminal of the first inverter inv1, and the input terminal of the first inverter inv1 is connected to the row address reset signal clear.

Preferably, the state maintaining unit includes a capacitor, a second inverter inv2 and a level recovery circuit, the capacitor is suitable for maintaining the state output by the decoding circuit of the decoding line, and the level recovery circuit is suitable for recovering the untranslated line The state of the decoding unit output.

Preferably, the level recovery circuit is a PMOS transistor, the gate of the level recovery circuit is connected to the output end of the second inverter inv2, and is connected to the output signal REN of the row decoding and holding circuit, and the The drain of the level restoration circuit is connected to the input terminal of the second inverter inv2, and the source of the level restoration circuit is connected to the power supply voltage VDD.

Preferably, the capacitor is a MOM capacitor, a MIM capacitor, a PIP capacitor or a MOS capacitor; one end of the capacitor is grounded, and the other end is connected to the input end of the second inverter inv2.

Preferably, the row decoding and holding circuit is an integral module.

Preferably, the pixel unit includes:

Photodiode D1, floating diffusion area FD, transmission transistor MTX, reset transistor MRST, source follower MSF and strobe transistor MSEL;

The TX signal drives the gate of the transmission tube MTX;

The RST signal drives the gate of the reset transistor MRST;

The SEL signal drives the gate of the strobe MSEL.

Preferably, the method includes: the reset circuit cooperates with the decoding enabling unit and the decoding logic unit to accurately decode the target row and avoid decoding the non-target row.

Preferably, the rising edge/falling edge of the row address reset signal clear and the row address enable signal gating are staggered from each other.

The technical solution of the present invention also provides an operation method of the image sensor as described above, including:

Decode the reset row address signal in turn, and save the decoding result;

The row driving signal is output to make the pixel unit of the target row perform the reset operation at the same time.

Compared with the prior art, the image sensor and the operation method thereof of the present invention have the following beneficial effects:

In the present invention, the photodiodes in the multi-row image sensors can be reset simultaneously. Compared with the traditional reset operation method, the new reset operation method greatly saves time and can significantly improve the frame rate of the image sensor.

Description of drawings

1 is a schematic diagram of a general pixel unit structure;

FIG. 2 is a timing diagram of a conventional image sensor row operation;

3 to 4 are schematic structural diagrams of an image sensor in an embodiment provided by the technical solution of the present invention;

FIG. 5 is an operation timing diagram of the image sensor row in the embodiment provided by the technical solution of the present invention.

Detailed ways

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar promotions without departing from the connotation of the present invention. Therefore, the present invention is not limited by the specific implementation disclosed below.

Next, the present invention is described in detail by using schematic diagrams. When describing the embodiments of the present invention in detail, for the convenience of description, the schematic diagrams are only examples, which should not limit the protection scope of the present invention.

In order to make the above objects, features and advantages of the present invention more clearly understood, the image sensor and its operation method of the present invention will be described in detail below with reference to the accompanying drawings.

1 , with reference to FIGS. 3 to 4 , the present invention provides an image sensor, comprising: at least one row of pixel units, a row driving circuit and a row decoding and holding circuit, wherein the row driving circuit corresponds to the row pixel units , suitable for driving the photodiode in the pixel unit of the corresponding row to reset according to the reset row address; the row decoding and holding circuit is suitable for decoding the row address of the pixel unit and maintaining its state to control the row driving circuit, Simultaneous resetting of photodiodes in multiple rows of pixel cells.

Continuing to refer to FIG. 1, specifically, in this embodiment, the pixel unit of the image sensor includes: a photodiode D1, a transfer transistor MTX, a floating diffusion FD, a reset transistor MRST, and a source follower The TX signal drives the gate of the transmission transistor MTX, the RST signal drives the gate of the reset transistor MRST, and the SEL signal drives the gate of the gate transistor MSEL.

In this embodiment, the reset operation process of the photodiode D1 in the pixel unit is:

First, the RST signal changes from low to high, the reset transistor MRST is turned on, and the floating diffusion FD is reset to VDD;

Then, the RST signal becomes low, and the reset tube MRST is turned off;

Then, the TX signal changes from low to high, and the transmission tube MTX is turned on, transferring all the electrons accumulated in the photodiode D1 to the floating diffusion region FD;

Finally, the TX signal becomes low, and the transmission tube MTX is turned off.

In this way, the reset operation of the photodiode D1 in the pixel unit is completed. In general applications, photodiodes in multiple rows of pixel units need to be reset due to the performance requirements of the image sensor.

Referring to FIG. 3 , FIG. 3 is a schematic structural diagram of a row circuit provided by the technical solution of the present invention. Wherein, the row circuit includes a row decoding and holding circuit and a row driving circuit. In this embodiment, the row decoding circuit and the row decoding holding circuit are an integral module.

Referring to FIG. 4 , in this embodiment, the row decoding and holding circuit includes a decoding unit and at least one state holding unit. Wherein, the decoding unit is suitable for decoding the reset row address; the state maintaining unit is suitable for setting according to the decoding result of the decoding unit, so as to control the row driving circuit, so as to simultaneously perform the decoding on multiple rows The photodiode in the pixel unit is reset, which saves the reset time of multiple rows and improves the frame rate.

Specifically, in this embodiment, an 11-bit row address code is taken as an example, ADDR<10:0> at the input end of the row decoding and holding circuit shown in FIG. 3 is the row address signal, clear is the row address reset signal, and gating is the row address enable signal.

RSEL, RG, TG of the input terminal of the row driving circuit in FIG. 3 are row input signals. Among them, RSEL is used to generate the row signal SEL, RG is used to generate the signal RST, and TG is used to generate the signal TX. SEL<1>, RST<1>, TX<1> are the row driving signals of the pixel unit of row 1; SEL<n>, RST<n>, TX<n> are the row driving signals of the pixel unit of row n. That is, in this embodiment, n is 10 as an example.

The row address signal ADDR<10:0>, the row address reset signal clear, and the row address enable signal gating are simultaneously input to the input terminal of the row decoding and holding circuit. The row decoding and holding circuit decodes the row address and maintains its state. The decoding and holding circuit outputs the REN signal, and REN and the row input signals RSEL, RG, TG are input to the input terminal of the row driving circuit, and jointly control the output signals SEL, RST and TX of the row driving circuit. The SEL signal drives the gate of the strobe transistor MSEL, the RST signal drives the gate of the reset transistor MRST, and the TX signal drives the gate of the transmission transistor MTX.

Referring to FIG. 4 , FIG. 4 is a structural diagram of the row decoding and holding circuit provided in this embodiment. The row decoding and holding circuit includes a decoding unit and at least one state holding unit; the decoding unit is suitable for decoding the reset row address; the state holding unit is suitable for decoding according to the decoding unit As a result, the arrangement is performed to control the row driving circuit so as to reset the photodiodes in the pixel units of the multiple rows at the same time, thereby saving the reset time of the multiple rows and improving the frame rate.

Wherein, the decoding unit includes a series-connected reset circuit, a decoding enabling unit and a decoding logic unit.

The reset circuit is adapted to reset the state of the state holding unit before decoding the target row address;

The decoding enable unit is adapted to provide an enable signal to the decoding logic unit;

The decoding logic unit is adapted to decode the row address code signal ADDR<10:0>, and output the decoding result to the state holding unit;

The state holding unit is adapted to hold the decoding result of the decoding unit until the next reset circuit resets it.

The decoding logic unit is a total of 11 NMOS transistors connected in series with N0~N10, and one end of the decoding logic unit is grounded, and the other end is connected to the decoding enabling unit, wherein the series N10~N0 The gate of the NMOS transistor is correspondingly connected to the row address code signal ADDR<10:0>, the decoding enabling unit is an NMOS transistor N11 connected in series with the decoding logic unit, and n is a natural number.

In FIG. 4, NMOS transistors N0~N10 are connected in series to form a decoding logic unit to decode the row address code. The decoding enabling unit is an NMOS transistor N11.

In this embodiment, in the decoding logic unit, one end is connected to the ground terminal GND by the source of the NMOSN10, and the other end is connected to the source of the NMOS transistor N11 by the drain of the NMOSN0. The drain of the NMOS transistor N11 is connected to the first terminal of the reset circuit P1, the second terminal of the reset circuit P1 is connected to VDD, the third terminal of the reset circuit P1 is the control terminal, and the third terminal accepts the row address The reset signal clear is output after passing through the first inverter inv1.

In this embodiment, the reset circuit P1 is a PMOS transistor. Specifically, in other embodiments, the reset circuit P1 may be another three-terminal device, and the conduction or closing between the other two ends is controlled by controlling the third terminal.

Specifically, in this embodiment, the row address reset signal clear is inverted by the first inverter inv1 and then connected to the gate of the reset circuit P1.

In this embodiment, the state maintaining unit maintains the output state of the decoding circuit, and the state maintaining unit includes: a capacitor C ₀ , a second inverter inv2 and a level recovery circuit P2; wherein the capacitor C ₀ is suitable for maintaining the state of the output of the decoding line decoding circuit, and the level restoration circuit P2 is suitable for restoring the state of the output of the decoding unit of the un-interpreting line.

Specifically, in this embodiment, the level recovery circuit P2 is a PMOS transistor, and the gate of the level recovery circuit P2 is connected to the output end of the second inverter inv2 and connected to the row decoding hold The circuit outputs a signal REN, the drain of the level restoration circuit is connected to the input terminal of the second inverter inv2, and the source of the level restoration circuit is connected to the power supply voltage VDD.

Specifically, in this embodiment, the capacitor C ₀ is a MOM capacitor, a MIM capacitor, a PIP capacitor or a MOS capacitor, one end of the capacitor C ₀ is grounded, and the other end is connected to the input end of the second inverter inv2.

Specifically, in this embodiment, the row address reset signal clear is input to the gate terminal of the reset circuit P1 through the first inverter inv1. When the row address reset signal clear is high, the reset circuit P1 pulls the node A to the power supply VDD. The code holding circuit output signal REN is low and invalid, that is, the row address state held by the state holding unit is reset.

When the row address reset signal clear is low, the reset circuit P1 is turned off, when the row address enable signal gating is high, N11 is turned on, and the row address code ADDR<10:0> makes a row N0~N10 all turned on, then N0 ~N10 forms a path from node A to ground, pulls node A to ground, capacitor C0 keeps the node A voltage at a low level, and the output signal REN is high and valid, that is, the row address is decoded.

When the middle row address is not translated, after the node A is pulled to VDD and the reset circuit P1 is turned off, if gating and ADDR<10:0> operate frequently, the conduction of some tubes of N0~N10 will cause node A and signal The charge on the parasitic capacitance on the path is redistributed, so that the voltage of node A will drop, and if it drops to a certain extent, the output REN will be mistakenly translated to a high level, that is, the output REN of the uninterpreted line will be incorrectly output. P2 and inv2 form positive feedback, which can prevent node A from becoming low due to charge redistribution. At the same time, P2 is an inverse ratio tube, and its driving capability is much smaller than the series path of N0~N11, avoiding pull-down errors during decoding.

An embodiment of the present invention also provides a method for simultaneously resetting photodiodes in multiple rows by an image sensor, including: before decoding the address of the target row, resetting the state of the state holding unit through the reset circuit P1, and then decoding The enable logic is enabled, the decoding circuit decodes the reset row address, the decoding result is output to the state holding unit, and the state holding unit holds the decoding result of the decoding unit until the next reset circuit resets it.

Specifically, with reference to FIG. 5, FIG. 5 is a new image sensor row operation timing diagram, and an embodiment of the present invention further provides an image sensor operation method, including:

Decode the reset row address signal in turn, and save the decoding result;

The row driving signal is output to make the pixel unit of the target row perform the reset operation at the same time.

The decoding unit decodes the row address of the reset row in turn, and the decoding result is output to the state holding unit, which controls the row driving circuit, so as to realize the operation of resetting the row photodiodes at the same time, so as to save more time. sub-photodiode reset time, improving efficiency.

The reset circuit cooperates with the decoding enabling unit and the decoding logic unit, so that the target row can be accurately decoded and the non-target row can be avoided.

In Fig. 5, at time A, the row address reset signal clear is a narrow pulse signal, the output REN of the row decoding and holding circuit is reset, and then the row address enable signal gating is a narrow pulse, the exposure row 1 is decoded, and the capacitor C0 The translated row address code remains valid until the next narrow pulse of the row address reset signal clear occurs to reset the row address. T3 (time A to time B) is the time when the address of exposure line l is translated.

Further, in this embodiment, it can be seen that the rising edge/falling edge of the row address reset signal clear and the row address enable signal gating are staggered. This is because the rising/falling edges of the row address code signals of different bits are not completely aligned when input to the input terminal of the decoding logic unit, and the rising/falling edges of the row address reset signal clear and the row address enable signal gating are staggered. , which can avoid non-target lines in translation.

Further, in this embodiment, from time B to time C is the time when the address of exposure row m is being translated, and the process from time A to time B is repeated. At time C, a narrow pulse signal appears in gating, and exposure line n is being translated, because the previous exposure lines l and m remain valid after being translated. During T1 time, the line input signals RSEL, RG, TG make reset lines l, The row driving circuits of m and n simultaneously output the same row driving signals SEL, RST, and TX to the pixel array, so that the reset rows 1, m, and n perform the reset operation at the same time. T2 (time D to time E) is the readout operation time of the readout row j.

In general, the address translation time T3 is about 20~30ns, the reset operation time T1 is about 200ns~500ns, and the time T3 is much shorter than the time T1. The above embodiments illustrate the operation method and principle of the present invention by taking the example of simultaneously resetting three rows. Those skilled in the art can learn from the above information that the above structure and method are applied to the case where multiple rows are reset simultaneously.

When three lines are reset at the same time, compared with the traditional reset operation method, the new reset operation method saves 360ns to 940ns. If the number of simultaneous reset lines increases, the time saved is more significant.

Because the row address reset signal clear first resets the state holding unit when the row address changes, the row address enable signal is valid only after the row address is stable, and the decoder performs decoding, which avoids different bits when the row address changes. Address codes arrive at the decoder at different times, resulting in incorrect row address codes in translation.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can use the methods and technical contents disclosed above to improve the present invention without departing from the spirit and scope of the present invention. The technical solutions are subject to possible changes and modifications. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solutions of the present invention belong to the technical solutions of the present invention. protected range.

Claims (15)

1. An image sensor, comprising:

at least one row of pixel units, a row driving circuit and a row decoding holding circuit;

the row driving circuit corresponds to the row pixel units and is suitable for driving the photodiodes in the corresponding row pixel units to reset according to a reset row address;

the row decode hold circuit is adapted to decode and hold the state of the row address of the pixel cells to control the row drive circuit so that the photodiodes in a plurality of rows of pixel cells are simultaneously reset.

2. The image sensor of claim 1, wherein the row decode holding circuit comprises a decode unit and at least one state holding unit; the decoding unit is suitable for decoding a reset row address; the state holding unit is suitable for being arranged according to the decoding result of the decoding unit so as to control the row driving circuit, so that the photodiodes in a plurality of rows of pixel units are reset at the same time, the multi-row reset time is saved, and the frame rate is improved.

3. The image sensor of claim 2, wherein the decode unit includes a reset circuit, a decode enable unit, and a decode logic unit in series;

the reset circuit is suitable for resetting the state of the state holding unit before decoding the target row address;

the decoding enabling unit is suitable for providing an enabling signal to the decoding logic unit;

the decoding logic unit is suitable for decoding row address code signals ADDR < n-1:0> and outputting a decoding result to the state holding unit;

the state holding unit is suitable for holding the decoding result of the decoding unit until the reset circuit resets the decoding unit next time.

4. The image sensor as claimed in claim 3, wherein one end of the decoding logic unit is grounded, the other end of the decoding logic unit is connected to the decoding enable unit, the decoding logic unit includes n serially connected NMOS transistors, n is a natural number, and gates of the n serially connected NMOS transistors are respectively connected to the row address code signals ADDR < n-1:0> in a one-to-one correspondence manner.

5. The image sensor of claim 4, wherein the decode enable unit is an NMOS transistor Nn in series with the decode logic unit.

6. The image sensor as claimed in claim 4, wherein the decode enable unit is connected to a first terminal of the reset circuit, a second terminal of the reset circuit is connected to VDD, a third terminal of the reset circuit is a control terminal, and the third terminal is connected to a row address reset signal.

7. The image sensor as claimed in claim 6, wherein the reset circuit is a PMOS, a gate of the PMOS is connected to an output terminal of a first inverter inv1, and an input terminal of the first inverter inv1 is connected to a row address reset signal clear.

8. The image sensor as claimed in claim 2, wherein the state holding unit includes a capacitor adapted to hold the state of the output of the decoded row decoding circuit, a second inverter inv2, and a level restoration circuit adapted to restore the state of the output of the un-decoded row decoding unit.

9. The image sensor as claimed in claim 8, wherein the level recovery circuit is a PMOS transistor, a gate of the level recovery circuit is connected to an output terminal of the second inverter inv2 and to the row decoding hold circuit output signal REN, a drain of the level recovery circuit is connected to an input terminal of the second inverter inv2, and a source of the level recovery circuit is connected to the power supply voltage VDD.

10. The image sensor of claim 8, wherein the capacitance is a MOM capacitance, a MIM capacitance, a PIP capacitance, or a MOS capacitance; one end of the capacitor is grounded, and the other end of the capacitor is connected to the input end of the second inverter inv 2.

11. The image sensor of claim 2, wherein the row decode hold circuit is an integral module.

12. The image sensor of claim 1, wherein the pixel cell comprises:

a photodiode D1, a transmission tube MTX, a floating diffusion region FD, a reset tube MRST, a source follower MSF and a gate tube MSEL;

the TX signal drives the grid electrode of the transmission tube MTX;

the RST signal drives the grid electrode of the reset tube MRST;

the SEL signal drives the gate of the gate tube MSEL.

13. The image sensor of claim 3, comprising: the reset circuit is matched with the decoding enabling unit and the decoding logic unit to accurately decode the target line and avoid decoding non-target lines.

14. A method of operating an image sensor as claimed in claim 1, comprising:

sequentially decoding the reset row address signals and storing decoding results;

and outputting a row driving signal to enable the target row of pixel units to simultaneously carry out reset operation.

15. The method of operating an image sensor of claim 14, comprising:

the rising/falling edges of the row address reset signal clear and the row address enable signal gating are staggered.

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