CN114823718A - A new type of LTPO backplane structure and fabrication method - Google Patents

Abstract

The invention discloses a novel LTPO backplane structure and a manufacturing method, comprising a Poly semiconductor layer, a GI layer and a metal layer M1 gate are arranged on the Poly semiconductor layer, and the GI layer and the metal layer M1 gate are provided with external An insulating layer PV1, a metal layer M2 is arranged on the insulating layer PV1, an insulating layer PV2 is arranged on the outside of the metal layer M2, a metal layer M3 is arranged on the insulating layer PV2, and an insulating layer is arranged on the metal layer M3 PV3 layer, an IGZO semiconductor layer is formed by coating on the insulating layer PV3 layer, a GI layer and a metal layer M4 gate are arranged on the IGZO semiconductor layer, and an insulating layer PV4 is arranged on the metal layer M4 gate and the IGZO semiconductor layer , the insulating layer PV4 is provided with a metal layer M5. The invention belongs to the technical field of backplanes, and specifically refers to a novel LTPO backplane structure and manufacturing method, with low power consumption and good stability.

Description

A new type of LTPO backplane structure and fabrication method

technical field

The invention belongs to the technical field of backplanes, and specifically refers to a novel LTPO backplane structure and a manufacturing method.

Background technique

At present, the small and medium-sized OLED panels on the market mainly use two technologies: LTPS (low temperature polysilicon) and IGZO (gallium zinc indium oxide) for the backplane.

The OLED panel using the LTPS backplane structure has larger electron mobility and aperture ratio, and can achieve higher resolution. Although the on-state current of the LTPS structure is large, the leakage current is also large, which requires continuous charging to maintain the capacitor potential, resulting in high power consumption and inability to drive at low frequencies.

The OLED panel using the IGZO backplane structure is similar to the amorphous silicon substrate process, and the production cost is lower than that of the LTPS backplane structure, but the mobility of IGZO is lower than that of LTPS, and the size of the TFT is larger, which makes the resolution lower; and the properties of IGZO are different. Stable, easily oxidized in the air, and the panel has a low service life.

SUMMARY OF THE INVENTION

In order to solve the above problems, the present invention provides a novel LTPO backplane structure, which divides the backplane into a double-layer structure, the bottom layer is a top-gate structure driving TFT, and LTPS is used as a semiconductor; the top layer is a top-gate structure switching TFT , Using IGZO as a semiconductor, this structure combines the advantages of high electron mobility of LTPS and small leakage current of IGZO, which makes the panel lower power consumption, better stability, and can realize low frequency refresh display of the panel.

In order to realize the above-mentioned functional mode, the technical solution adopted in the present invention is as follows: a novel LTPO backplane structure includes a Poly semiconductor layer, and the Poly semiconductor layer is formed on the substrate through an ELA (excimer laser annealing) process, and the Poly semiconductor layer is provided with There is a GI layer and a metal layer M1 gate, the GI layer separates the metal layer M1 gate and the Poly semiconductor layer, the GI layer and the metal layer M1 gate are provided with an insulating layer PV1, and the insulating layer PV1 is on the outside. A metal layer M2 is provided, the metal layer M2 is connected to the gate of the metal layer M1, an insulating layer PV2 is provided outside the metal layer M2, a metal layer M3 is provided on the insulating layer PV2, and the metal layer M3 (OVDD signal) and the metal layer M2 through the insulating layer PV2 to form the storage capacitor Cst of the pixel drive circuit, the metal layer M3 is provided with an insulating layer PV3 layer, the insulating layer PV3 layer is coated to form an IGZO semiconductor layer, the IGZO semiconductor layer There is a GI layer and a metal layer M4 gate, the GI layer separates the metal layer M4 gate from the IGZO semiconductor layer, the Scan signal is sent through the metal layer M4, the metal layer M4 gate and IGZO An insulating layer PV4 is arranged on the semiconductor layer, a metal layer M5 is arranged on the insulating layer PV4, the metal layer M5 is connected with the metal layer M2, and the metal layer M5 is used as the Source and Drain pole of the switching TFT and connected with the metal layer M2, and the metal layer M5 is connected to the metal layer M2. The DATA signal is sent to the gate of the metal layer M1 of the driving TFT and stored in the capacitor Cst. The metal layer M5 is provided with an organic leveling layer OC, and an anode metal layer Anode is provided on the organic leveling layer OC. The layer Anode is connected to the metal layer M3 and receives the OVDD current signal. The organic planarization layer OC is provided with a pixel definition layer PDL, and the anode metal layer Anode is provided with an opening.

The insulating layer PV1 is provided with a VIA1 hole, and the metal layer M2 is connected to the gate of the metal layer M1 through the VIA1 hole.

Further, a VIA2 hole is provided on the insulating layer PV2, and the metal layer M3 is connected to the Drain and Source electrodes of the driving TFT through the VIA2 hole.

Preferably, the insulating layer PV4 is provided with a VIA4 hole, and the metal layer M5 is connected to the metal layer M2 through the VIA4 hole.

Wherein, an OC hole is provided on the organic leveling layer OC, and the anode metal layer Anode is connected to the metal layer M3 through the OC hole.

The present invention also includes a method for making a novel LTPO backplane structure, comprising the following steps:

(1) Coating an amorphous silicon (a-si) film layer on the glass substrate, forming a POLY (LTPS) semiconductor layer in the middle part by the ELA (excimer laser annealing) process, and then injecting P+ ions into POLY by an ion implantation process The left and right ends form the source electrode and the drain electrode respectively;

(2) The GI layer and the metal layer M1 (gate) are respectively plated on the semiconductor layer Poly, and the GI layer separates the gate of the metal layer M1 from the semiconductor layer;

(3) The insulating layer PV1 covers the metal layer M1, the GI film layer, the SOURCE electrode and the DRAIN electrode;

(4) Punch VIA1 hole in PV1 of insulating layer;

(5) The metal layer M2 is plated on the insulating layer PV1 and connected to the gate of the metal layer M1 through the VIA1 hole;

(6) Plating the insulating layer PV2 to cover the metal layer M2;

(7) Punch VIA2 holes in the insulating layer PV2;

(8) A metal layer M3 is plated on the insulating layer PV2. The metal layer M3 (OVDD signal) is connected to the Drain and Source poles of the driving TFT through the VIA2 hole, and the metal layer M2 forms the storage capacitor Cst of the pixel driving circuit through the insulating layer PV2. ;

(9) The insulating layer PV3 covers the metal layer M3, the PV3 layer is coated to form an IGZO semiconductor layer, the GI layer and the metal layer M4 gate are respectively plated on the IGZO semiconductor layer, and the GI layer separates the metal layer M4 gate from the IGZO semiconductor layer. On, the Scan signal is sent through the metal layer M4;

(10) The insulating layer PV4 covers the gate of the metal layer M4 and the IGZO semiconductor layer;

(11) Punch VIA4 holes in PV4 of insulating layer;

(12) A metal layer M5 is plated on the insulating layer PV4. The metal layer M5 is used as the Source and Drain pole of the switching TFT to be connected to the metal layer M2, and the DATA signal is sent to the gate of the metal layer M1 of the driving TFT and stored in the capacitor Cst. ;

(13) The organic leveling layer OC covers the metal layer M5;

(14) Punch OC holes on the organic leveling layer OC;

(15) An anode metal layer Anode is plated on the organic leveling layer OC and connected to the metal layer M3 to receive the OVDD current signal;

(16) A pixel definition layer PDL is plated on the organic leveling layer OC, and an opening is formed at the anode metal layer Anode.

The present invention adopts the above structure to obtain the following beneficial effects: the novel LTPO backplane structure and manufacturing method provided by the present invention are simple in operation, compact in structure and reasonable in design, and compared with the traditional LTPS backplane, the leakage current of the switching TFT is reduced, and The opening size of the driving TFT is constant during the display time, which reduces the power consumption of the panel; compared with the traditional IGZO backplane, the size of the driving TFT is reduced and the TFT layered distribution reduces the driving circuit area of a single pixel and increases the power consumption of the panel. PPI improves the resolution and makes the screen display clearer; combines the advantages of LTPS and IGZO backplane structures to improve panel stability, increase panel aperture ratio, and realize panel low-frequency refresh display.

Description of drawings

1 is a schematic structural diagram of a novel LTPO backplane structure provided by the present invention;

FIG. 2 is a schematic diagram of the PEP sequence of the backplane mask of the novel LTPO backplane structure provided by the present invention.

Detailed ways

The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation or a specific orientation. construction and operation, and therefore should not be construed as limiting the invention. Furthermore, the terms "first", "second", and "third" are used for descriptive purposes only and should not be construed to indicate or imply relative importance. The present invention will be described in further detail below with reference to the accompanying drawings.

As shown in Fig. 1-2, the novel LTPO backplane structure provided by the present invention includes a Poly semiconductor layer. The Poly semiconductor layer is formed on the substrate through an ELA (excimer laser annealing) process. The Poly semiconductor layer is provided with a GI layer and a metal layer. M1 gate, the GI layer separates the metal layer M1 gate and the Poly semiconductor layer, the GI layer and the metal layer M1 gate are provided with an insulating layer PV1, and the insulating layer PV1 is provided with a metal layer M2, the metal layer M2 and the metal layer The gate of M1 is connected to the gate, the metal layer M2 is provided with an insulating layer PV2, and the insulating layer PV2 is provided with a metal layer M3. The metal layer M3 (OVDD signal) is connected to the Drain and Source electrodes of the driving TFT, and the metal layer M3 (OVDD signal) is connected to The metal layer M2 forms the storage capacitor Cst of the pixel drive circuit through the insulating layer PV2, the insulating layer PV3 layer is provided on the metal layer M3, the insulating layer PV3 layer is plated to form an IGZO semiconductor layer, and the IGZO semiconductor layer is provided with a GI layer and a metal layer M4 The gate, the GI layer separates the gate of the metal layer M4 from the IGZO semiconductor layer, the Scan (scan) signal is sent through the metal layer M4, the gate of the metal layer M4 and the IGZO semiconductor layer are provided with an insulating layer PV4, on the insulating layer PV4 There is a metal layer M5, the metal layer M5 is connected with the metal layer M2, and the metal layer M5 is used as the Source and Drain pole of the switching TFT to be connected with the metal layer M2, and the DATA signal is sent to the gate of the metal layer M1 of the driving TFT and stored in the capacitor Cst In the middle, an organic leveling layer OC is provided on the metal layer M5, an anode metal layer Anode is provided on the organic leveling layer OC, the anode metal layer Anode is connected to the metal layer M3, and receives an OVDD current signal, and a pixel definition layer is provided on the organic leveling layer OC. PDL, the anode metal layer Anode is provided with an opening.

There is a VIA1 hole on the insulating layer PV1, and the metal layer M2 is connected to the gate of the metal layer M1 through the VIA1 hole; there is a VIA2 hole on the insulating layer PV2, and the metal layer M3 is connected to the Drain and Source poles of the driving TFT through the VIA2 hole; the insulating layer A VIA4 hole is provided on the PV4, and the metal layer M5 is connected to the metal layer M2 through the VIA4 hole; an OC hole is provided on the organic leveling layer OC, and the anode metal layer Anode is connected to the metal layer M3 through the OC hole.

The present invention also includes a method for making a novel LTPO backplane structure, comprising the following steps:

(1) Coating an amorphous silicon (a-si) film layer on the glass substrate, forming a POLY (LTPS) semiconductor layer in the middle part by the ELA (excimer laser annealing) process, and then injecting P+ ions into POLY by an ion implantation process The left and right ends form the source electrode and the drain electrode respectively;

(2) The GI layer and the metal layer M1 (gate) are respectively plated on the semiconductor layer Poly, and the GI layer separates the gate of the metal layer M1 from the semiconductor layer;

(3) The insulating layer PV1 covers the metal layer M1, the GI film layer, the SOURCE electrode and the DRAIN electrode;

(4) Punch VIA1 hole in PV1 of insulating layer;

(5) The metal layer M2 is plated on the insulating layer PV1 and connected to the gate of the metal layer M1 through the VIA1 hole;

(6) Plating the insulating layer PV2 to cover the metal layer M2;

(7) Punch VIA2 holes in the insulating layer PV2;

(8) A metal layer M3 is plated on the insulating layer PV2. The metal layer M3 (OVDD signal) is connected to the Drain and Source poles of the driving TFT through the VIA2 hole, and the metal layer M2 forms the storage capacitor Cst of the pixel driving circuit through the insulating layer PV2. ;

(9) The insulating layer PV3 covers the metal layer M3, the PV3 layer is coated to form an IGZO semiconductor layer, the GI layer and the metal layer M4 gate are respectively plated on the IGZO semiconductor layer, and the GI layer separates the metal layer M4 gate from the IGZO semiconductor layer. On, the Scan signal is sent through the metal layer M4;

(10) The insulating layer PV4 covers the gate of the metal layer M4 and the IGZO semiconductor layer;

(11) Punch VIA4 holes in PV4 of insulating layer;

(12) A metal layer M5 is plated on the insulating layer PV4. The metal layer M5 is used as the Source and Drain pole of the switching TFT to be connected to the metal layer M2, and the DATA signal is sent to the gate of the metal layer M1 of the driving TFT and stored in the capacitor Cst. ;

(13) The organic leveling layer OC covers the metal layer M5;

(14) Punch OC holes on the organic leveling layer OC;

(15) An anode metal layer Anode is plated on the organic leveling layer OC and connected to the metal layer M3 to receive the OVDD current signal;

(16) A pixel definition layer PDL is plated on the organic leveling layer OC, and an opening is formed at the anode metal layer Anode.

The specific use is as follows:

(1) Coating an amorphous silicon (a-si) film layer on the glass substrate, forming a POLY (LTPS) semiconductor layer in the middle part by the ELA (excimer laser annealing) process, and then injecting P+ ions into POLY by an ion implantation process The left and right ends form the source electrode and the drain electrode respectively;

(2) The GI layer and the metal layer M1 (gate) are respectively plated on the semiconductor layer Poly, and the GI layer separates the gate of the metal layer M1 from the semiconductor layer;

(3) The insulating layer PV1 covers the metal layer M1, the GI film layer, the SOURCE electrode and the DRAIN electrode;

(4) Punch VIA1 hole in PV1 of insulating layer;

(5) The metal layer M2 is plated on the insulating layer PV1 and connected to the gate of the metal layer M1 through the VIA1 hole;

(6) Plating the insulating layer PV2 to cover the metal layer M2;

(7) Punch VIA2 holes in the insulating layer PV2;

(8) A metal layer M3 is plated on the insulating layer PV2. The metal layer M3 (OVDD signal) is connected to the Drain and Source poles of the driving TFT through the VIA2 hole, and the metal layer M2 forms the storage capacitor Cst of the pixel driving circuit through the insulating layer PV2. ;

(9) The insulating layer PV3 covers the metal layer M3, the PV3 layer is coated to form an IGZO semiconductor layer, the GI layer and the metal layer M4 gate are respectively plated on the IGZO semiconductor layer, and the GI layer separates the metal layer M4 gate from the IGZO semiconductor layer. On, the Scan signal is sent through the metal layer M4;

(10) The insulating layer PV4 covers the gate of the metal layer M4 and the IGZO semiconductor layer;

(11) Punch VIA4 holes in PV4 of insulating layer;

(12) A metal layer M5 is plated on the insulating layer PV4. The metal layer M5 is used as the Source and Drain pole of the switching TFT to be connected to the metal layer M2, and the DATA signal is sent to the gate of the metal layer M1 of the driving TFT and stored in the capacitor Cst. ;

(13) The organic leveling layer OC covers the metal layer M5;

(14) Punch OC holes on the organic leveling layer OC;

(15) An anode metal layer Anode is plated on the organic leveling layer OC and connected to the metal layer M3 to receive the OVDD current signal;

(16) A pixel definition layer PDL is plated on the organic leveling layer OC, and an opening is formed at the anode metal layer Anode.

The present invention and its embodiments have been described above, and the description is not restrictive, and what is shown in the accompanying drawings is only one of the embodiments of the present invention, and the actual structure is not limited thereto. All in all, if those of ordinary skill in the art are inspired by it, and without departing from the purpose of the present invention, any structural modes and embodiments similar to this technical solution are designed without creativity, all should belong to the protection scope of the present invention.

Claims (6)

1. A novel LTPO backplate structure which characterized in that: the organic light-emitting diode comprises a Poly semiconductor layer, wherein a GI layer and a metal layer M1 grid electrode are arranged on the Poly semiconductor layer, the GI layer separates a metal layer M1 grid electrode from the Poly semiconductor layer, an insulating layer PV1 is arranged outside the GI layer and the metal layer M1 grid electrode, a metal layer M2 is arranged on the insulating layer PV1, a metal layer M2 is connected with a metal layer M1 grid electrode, an insulating layer PV2 is arranged outside the metal layer M2, a metal layer M3 is arranged on the insulating layer PV2, the metal layer M3 and the metal layer M2 form a storage capacitor Cst of a pixel driving circuit through an insulating layer PV2, an insulating layer PV3 layer is arranged on the metal layer M3, an IGZO semiconductor layer is formed on the insulating layer PV3 by coating, a GI layer and a metal layer M4 grid electrode are arranged on the IGZO semiconductor layer, the metal layer M4 grid electrode is separated from the IGZO semiconductor layer by the GI layer, a PV insulating layer is arranged on the metal layer M4 grid electrode and the IGZO semiconductor layer, a PV insulating layer is arranged on the metal layer and the IGZO semiconductor layer, a PV insulating layer 6 is arranged on the PV4 insulating layer, the metal layer M5 and the metal layer M2 link to each other, be equipped with organic planarization layer OC on the metal layer M5, be equipped with Anode metal layer Anode on the organic planarization layer OC, Anode metal layer Anode links to each other with metal layer M3, be equipped with pixel definition layer PDL on the organic planarization layer OC, be equipped with the opening on Anode metal layer Anode.

2. The novel LTPO backplane structure of claim 1 wherein: the insulating layer PV1 is provided with VIA1 holes, and the metal layer M2 is connected with the grid electrode of the metal layer M1 through the VIA1 holes.

3. The novel LTPO backplane structure of claim 2 wherein: the insulating layer PV2 is provided with a VIA2 hole, and the metal layer M3 is connected with a Drain electrode and a Source electrode of the driving TFT through the VIA2 hole.

4. A novel LTPO back plate structure as claimed in claim 3, wherein: the insulating layer PV4 is provided with VIA4 holes, and the metal layer M5 is connected with the metal layer M2 through the VIA4 holes.

5. The novel LTPO backplane structure of claim 4, wherein: the organic planarization layer OC is provided with OC holes, and the Anode metal layer Anode is connected with the metal layer M3 through the OC holes.

6. A method of making a novel LTPO back sheet structure according to any one of claims 1-5, wherein: the method comprises the following steps:

(1) plating an amorphous silicon a-si film layer on a glass substrate, forming a POLY semiconductor layer in the middle part through an ELA process, and injecting P + ions into the left end and the right end of the POLY through an ion injection process to respectively form a source electrode and a drain electrode;

(2) respectively plating a GI layer and a metal layer M1 on the semiconductor layer Poly, wherein the GI layer separates the gate of the metal layer M1 from the semiconductor layer;

(3) the insulating layer PV1 covers the metal layer M1, the GI film layer, the SOURCE electrode and the DRAIN electrode;

(4) the insulation layer PV1 is provided with VIA1 holes;

(5) plating a metal layer M2 on the insulating layer PV1 and connecting the metal layer M1 gate through a VIA1 hole;

(6) plating an insulating layer PV2 to cover the metal layer M2;

(7) punching VIA2 holes in the insulating layer PV 2;

(8) plating a metal layer M3 on the insulating layer PV2, wherein the metal layer M3 is connected with Drain and Source electrodes of the driving TFT through a VIA2 hole, and forms a storage capacitor Cst of the pixel driving circuit with the metal layer M2 through an insulating layer PV 2;

(9) the insulating layer PV3 covers the metal layer M3, an IGZO semiconductor layer is formed on the PV3 layer coating film, a GI layer and a metal layer M4 grid electrode are respectively coated on the IGZO semiconductor layer, the GI layer separates the metal layer M4 grid electrode from the IGZO semiconductor layer, and Scan, namely scanning signals are sent through the metal layer M4;

(10) the insulating layer PV4 covers the metal layer M4 grid and the IGZO semiconductor layer;

(11) the insulation layer PV4 is provided with VIA4 holes;

(12) plating a metal layer M5 on the insulating layer PV4, connecting the metal layer M5 as the Source and Drain poles of the switching TFT with the metal layer M2, sending the DATA signal to the metal layer M1 gate of the driving TFT and storing the DATA signal in the capacitor Cst;

the organic planarization layer OC covers the metal layer M5;

punching OC holes on the organic planarization layer OC;

(15) plating an Anode metal layer Andode on the organic planarization layer OC, connecting the Anode metal layer Antode with the metal layer M3, and receiving an OVDD current signal;

(16) a pixel definition layer PDL is plated on the organic planarization layer OC, and is opened at the Anode metal layer Anode.

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