CN114864661A - Stepped JTE-Rings super junction power device terminal structure and preparation method thereof - Google Patents

Abstract

The invention discloses a stepped JTE-Rings super junction power device terminal structure, which comprises a substrate layer and a first conductive type epitaxial layer positioned on the substrate layer, wherein an active region and a terminal region positioned at the periphery of the active region are formed in the epitaxial region, the terminal region of the epitaxial layer comprises a multi-layer epitaxial structure, a plurality of JTE-Rings regions are arranged in each epitaxial structure, and the number of the JTE-Rings regions in each epitaxial structure is sequentially increased from bottom to top so as to form a stepped JTE-Rings terminal from the left lower part to the right upper part; and a surface terminal region is also arranged above the JTE-Rings region at the topmost layer of the stepped JTE-Rings terminal. According to the invention, the super junction structure and the stepped JTE-Rings terminal structure are respectively formed in the active region and the terminal region of the device simultaneously in a multilayer epitaxial growth mode, the terminal structure is simple and easy to realize, the injection damage is reduced, the process complexity is reduced, and the device performance is promoted.

Description

A ladder type JTE-Rings super junction power device terminal structure and preparation method thereof

technical field

The invention belongs to the technical field of microelectronics, and in particular relates to a terminal structure of a stepped JTE-Rings super junction power device and a preparation method thereof.

Background technique

With the development of microelectronics technology, modern power semiconductor technology has been widely used in all aspects of the national economy, from traditional industrial electronics, to information communication, computer, consumer and automotive fields, new energy, rail transit, electric vehicles and smart The power grid is becoming a powerful engine for the growth of the power semiconductor market. To further enhance the performance of power devices, superjunction junctions are widely used in diodes with related Schottky structures. The so-called super junction structure is to add one or more layers of discontinuous or continuous P+ structures to the epitaxial layer of traditional power devices, which is similar to forming a PN junction structure inside the epitaxial layer. When the device works in the reverse state, the addition of the superjunction structure can change the original triangular or trapezoidal electric field distribution inside the epitaxial layer, thereby increasing the reverse breakdown voltage of the device under the condition that the thickness and concentration of the epitaxial layer remain unchanged.

However, due to the addition of a super junction structure to the traditional device structure, the influence of various factors such as epitaxial layer structure, source region super junction structure, terminal region super junction structure and terminal structure on device performance should be comprehensively considered in the device structure design. The design is relatively complex. Therefore, it is necessary to design and optimize the terminal structure of the super junction device to ensure the performance of the super junction structure.

At present, the conventional practice is to add one or more layers of continuous or discontinuous P+ structures to the epitaxial layers of traditional power devices, so as to realize the super junction structure of the active region and the terminal region of the device at the same time. However, the implantation damage in the termination region formed by this method is relatively large, which affects the device performance to a certain extent.

SUMMARY OF THE INVENTION

In order to solve the above problems existing in the prior art, the present invention provides a terminal structure of a stepped JTE-Rings super junction power device and a preparation method thereof. The technical problem to be solved by the present invention is realized by the following technical solutions:

A stepped JTE-Rings super junction power device terminal structure, comprising a substrate layer and a first conductivity type epitaxial layer on the substrate layer, an active region is formed in the epitaxial layer and a periphery of the active region is formed the terminal area, where,

The terminal region of the epitaxial layer includes a multi-layer epitaxial structure, each layer of the epitaxial structure is provided with a number of JTE-Rings regions, and the number of JTE-Rings regions in each layer of the epitaxial structure increases sequentially from bottom to top, so as to form from the bottom left. Square to the upper right ladder type JTE-Rings terminal;

Wherein, a surface termination region is also formed above the JTE-Rings region on the topmost layer of the stepped JTE-Rings termination.

In an embodiment of the present invention, the included angle between the right boundary of the bottommost JTE-Rings area of the stepped JTE-Rings terminal and the right boundary of the topmost JTE-Rings area and the horizontal direction ranges from 10° to 80° °.

In one embodiment of the present invention, the JTE-Rings region is formed by Al ion implantation, and the implantation concentration is 5×10 ¹⁶ to 5×10 ¹⁷ cm ⁻³ .

In one embodiment of the present invention, the first conductivity type is N-type.

In one embodiment of the present invention, a super junction structure is formed in the active region.

In an embodiment of the present invention, the super junction structure is a floating junction or a P-pillar super junction.

Another embodiment of the present invention provides a method for preparing a terminal structure of a stepped JTE-Rings super junction power device, comprising the following steps:

Step 1: provide an N++ substrate;

Step 2: growing a layer of N-epitaxial structure on the N++ substrate;

Step 3: performing ion implantation on the surface of the active region of the N-epitaxial structure to form a super junction active region;

Step 4: performing ion implantation on the surface of the terminal region of the N-epitaxial structure to form a JTE-Rings region;

Step 5: Repeat steps 2-4 to form an epitaxial layer with a multi-layer epitaxial structure; wherein the number of JTE-Rings regions in each epitaxial structure increases sequentially from bottom to top to form a stepped JTE from bottom left to top right -Rings terminal;

Step 6: A layer of N-epitaxial structure is grown again on the surface of the sample obtained in Step 5, and ion implantation is performed to form a surface termination region.

Yet another embodiment of the present invention also provides a semiconductor power device, including the stepped JTE-Rings super junction power device termination structure described in the above embodiment.

Beneficial effects of the present invention:

In the present invention, a super junction structure and a stepped JTE-Rings terminal structure are respectively formed in the active region and the terminal region of the device by means of multi-layer epitaxial growth. The process complexity is reduced and the device performance is improved.

The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

Description of drawings

1 is a schematic diagram of a terminal structure of a stepped JTE-Rings super junction power device provided by an embodiment of the present invention;

2 is a flowchart of a method for preparing a terminal structure of a stepped JTE-Rings super junction power device provided by an embodiment of the present invention;

3a-3g are process flow diagrams of preparing a terminal structure of a stepped JTE-Rings super junction power device according to an embodiment of the present invention.

Detailed ways

The present invention will be described in further detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

Example 1

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a terminal structure of a stepped JTE-Rings super junction power device provided by an embodiment of the present invention, which includes: a substrate layer (not shown in FIG. 1) and a first terminal located on the substrate layer. A conductive type epitaxial layer, an active region 1 and a terminal region 2 located at the periphery of the active region 1 are formed in the epitaxial layer, wherein,

The terminal region 2 of the epitaxial layer includes a multi-layer epitaxial structure, and each layer of the epitaxial structure is provided with a number of JTE-Rings regions 3, and the number of JTE-Rings regions 3 in each layer of the epitaxial structure is sequentially increased from bottom to top. Stepped JTE-Rings terminal from bottom left to top right;

A surface termination region 4 is also formed above the JTE-Rings region 3 on the topmost layer of the stepped JTE-Rings termination.

In this embodiment, the angle between the right boundary of the bottommost JTE-Rings area of the stepped JTE-Rings terminal and the right boundary of the topmost JTE-Rings area and the horizontal direction ranges from 10° to 80°.

It can be understood that the number of JTE-Rings regions 3 in each epitaxial structure can increase linearly or non-linearly from bottom to top, and the size and spacing of each JTE-Rings region do not have to be exactly the same. , which can be flexibly set according to actual needs, and the comparison in this embodiment does not make specific limitations.

In this embodiment, the step angle of the stepped JTE-Rins terminal ranges from 10° to 80°, which ensures the withstand voltage requirement of the device terminal and minimizes the impact of injection damage on device performance. influences.

Further, the JTE-Rings region 3 is formed by Al ion implantation, and the implantation concentration is 5×10 ¹⁶ to 5×10 ¹⁷ cm ⁻³ .

In this embodiment, the first conductivity type is N-type.

It should be noted that the active region in this embodiment is a super junction active region, in which a super junction structure is formed. The super junction structure may be a floating junction or a P-pillar super junction, or may be other super junction structures. This embodiment does not limit this.

In this embodiment, a super junction structure and a stepped JTE-Rings terminal structure are formed in the active region and the terminal region of the device by the multi-layer epitaxial growth method. The device has a simple structure and is easy to implement, which not only reduces the injection damage, but also The process complexity is reduced and the device performance is improved.

Embodiment 2

On the basis of the above-mentioned first embodiment, this embodiment further provides a preparation method for preparing the semiconductor terminal structure provided in the above-mentioned first embodiment. Please refer to FIG. 2. FIG. 2 is a flowchart of a method for preparing a terminal structure of a stepped JTE-Rings super junction power device provided by an embodiment of the present invention, which specifically includes the following steps:

Step 1: provide an N++ substrate;

Step 2: growing a layer of N-epitaxial structure on the N++ substrate;

Step 3: performing ion implantation on the surface of the active region of the N-epitaxial structure to form a super junction active region;

Step 4: performing ion implantation on the surface of the terminal region of the N-epitaxial structure to form a JTE-Rings region;

Step 5: Repeat steps 2-4 to form an epitaxial layer with a multi-layer epitaxial structure; wherein the number of JTE-Rings regions in each epitaxial structure increases sequentially from bottom to top to form a step from the lower left to the upper right Type JTE-Rings terminal;

Step 6: A layer of N-epitaxial structure is grown again on the surface of the sample obtained in Step 5, and ion implantation is performed to form a surface termination region.

The angle between the right boundary of the bottommost JTE-Rings area of the stepped JTE-Rings terminal and the right boundary of the topmost JTE-Rings area and the horizontal direction ranges from 10° to 80°.

The process for preparing the semiconductor terminal structure provided in this embodiment will be described in detail below with reference to FIGS. 3a-3g. Please refer to FIGS. 3a-3g. FIGS. 3a-3g are process diagrams of preparing a terminal structure of a stepped JTE-Rings super junction power device according to an embodiment of the present invention.

S1: Provide an N++ substrate, as shown in Figure 3a.

S2: growing the first N- epitaxial structure 21 on the surface of the N++ substrate, as shown in FIG. 3b.

Specifically, in this embodiment, a CVD (chemical vapor deposition) method is used to form the first N-epitaxial structure 21 on the surface of the substrate, and the growth temperature is 1600°C to 1900°C.

S3: Perform ion implantation on the surface of the active region 1 of the first N- epitaxial layer 21 to form a super junction active region (not shown in the figure).

S4: ion implantation is performed on the surface of the terminal region 2 of the first N- epitaxial layer 21 to form the JTE-Rings region 3, as shown in FIG. 3c;

Specifically, in this embodiment, the JTE-Rings region 3 is formed by Al ion implantation, and the implantation concentration is 5×10 ¹⁶ to 5×10 ¹⁷ cm ⁻³ .

S5 : growing the second N- epitaxial structure 22 on the surface of the first N- epitaxial structure 21 , as shown in FIG. 3d .

Specifically, the growth process of the second N- epitaxial structure 22 is the same as that of the first N- epitaxial layer 21 .

S6: Perform ion implantation on the surface of the active region 1 of the second N- epitaxial layer 22 to form a super junction active region (not shown in the figure).

S7: performing ion implantation on the surface of the terminal region 2 of the second N- epitaxial layer 22 to form a plurality of JTE-Rings regions 3, as shown in FIG. 3e;

S8: Repeat the operations of steps S5-S7 to form an N-epitaxial layer including a multi-layer epitaxial structure on the substrate, wherein each epitaxial structure includes at least one JTE-Rings region 3, and each layer of the epitaxial structure includes a JTE-Rings region 3. The number of Ring regions 3 increases sequentially from bottom to top, thereby forming a stepped JTE-Rings terminal from the lower left to the upper right, as shown in Figure 3f.

S9: Above the JTE-Rings region 3 of the topmost epitaxial structure, grow an N-epitaxial layer again and perform ion implantation to form a surface termination region 4, as shown in FIG. 3g.

In this embodiment, before the ion implantation is performed in the terminal region of each epitaxial structure to form the JTE-Rings region, ion implantation needs to be performed in the active region of each epitaxial structure to form the super junction active region. For the specific process, reference may be made to the existing preparation process, which is not described in detail in this embodiment.

In addition, it can be understood that, after completing the above process steps, it also includes:

An oxide layer is grown on the surface of the uppermost N-epitaxial layer, and metal layers are deposited on the back and front of the sample, and the back and front electrodes of the device are formed by an annealing process, thereby completing the preparation of the device.

Among them, the metal can be selected from Ti, Ni, etc., and the annealing temperature is 400°C to 1000°C.

In the preparation method provided in this embodiment, a super junction structure and a stepped JTE-Rings terminal structure are formed in the active region and the terminal region of the device simultaneously by means of multi-layer epitaxial growth. The device has a simple structure, is easy to implement, and reduces the Implant damage while reducing process complexity and help improve device performance.

Embodiment 3

On the basis of the first embodiment above, the example further provides a semiconductor power device, which includes the stepped JTE-Rings super junction power device termination structure provided in the first embodiment.

Specifically, the semiconductor power device provided in this embodiment may be a silicon carbide super junction power device, such as a super junction JBS, a MOSFET, an SBD, and the like.

Therefore, the semiconductor power device provided in this embodiment also has the advantages of simple structure, easy implementation, small injection damage and excellent performance.

In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", " rear, left, right, vertical, horizontal, top, bottom, inside, outside, clockwise, counterclockwise, etc., or The positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, Therefore, it should not be construed as a limitation of the present invention.

In addition, the terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature defined as "first" or "second" may expressly or implicitly include one or more of that feature. In the description of the present invention, "plurality" means two or more, unless otherwise expressly and specifically defined.

In the present invention, unless otherwise expressly specified and limited, a first feature "on" or "under" a second feature may include the first and second features in direct contact, or may include the first and second features Not directly but through additional features between them. Also, the first feature being "above", "over" and "above" the second feature includes the first feature being directly above and obliquely above the second feature, or simply means that the first feature is level higher than the second feature. The first feature is "below", "below" and "below" the second feature includes the first feature being directly below and diagonally below the second feature, or simply means that the first feature has a lower level than the second feature.

In the description of this specification, description with reference to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples", etc., mean specific features described in connection with the embodiment or example , structure, material or feature is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

Although the application is described herein in conjunction with the various embodiments, those skilled in the art will understand and understand from a review of the drawings, the disclosure, and the appended claims in practicing the claimed application. Other variations of the disclosed embodiments are implemented. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that these measures cannot be combined to advantage.

The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be considered that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deductions or substitutions can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (8)

1. A ladder type JTE-Rings super junction power device terminal structure, characterized in that, comprising a substrate layer and a first conductivity type epitaxial layer positioned on the substrate layer, and an active region (1) is formed in the epitaxial layer. ) and a termination region (2) at the periphery of the active region (1), wherein, The terminal region (2) of the epitaxial layer includes a multi-layer epitaxial structure, each layer of the epitaxial structure is provided with several JTE-Rings regions (3), and the number of JTE-Rings regions (3) in each layer of the epitaxial structure is from the bottom The top increases in turn to form a stepped JTE-Rings terminal from the lower left to the upper right; Wherein, a surface termination region (4) is further formed above the JTE-Rings region (3) on the topmost layer of the stepped JTE-Rings termination. 2 . The stepped JTE-Rings super junction power device terminal structure according to claim 1 , wherein the right boundary of the bottommost JTE-Rings area of the stepped JTE-Rings terminal and the right boundary of the topmost JTE-Rings area are 2 . The angle between the right boundary line and the horizontal direction ranges from 10° to 80°. 3 . The stepped JTE-Rings super junction power device termination structure according to claim 1 , wherein the JTE-Ring region ( 3 ) is formed by Al ion implantation, and the implantation concentration is 5×10 ¹⁶ ~ 3 . 5×10 ¹⁷ cm ^-3 . 4 . The stepped JTE-Rings super junction power device termination structure according to claim 1 , wherein the first conductivity type is N-type. 5 . 5 . The stepped JTE-Rings super junction power device termination structure according to claim 1 , wherein a super junction structure is formed in the active region. 6 . 6 . The stepped JTE-Rings super junction power device termination structure according to claim 5 , wherein the super junction structure is a floating junction or a P-pillar super junction. 7 . 7. A preparation method of a ladder type JTE-Rings super junction power device terminal structure, characterized in that, comprising the following steps: Step 1: provide an N++ substrate; Step 2: growing a layer of N-epitaxial structure on the N++ substrate; Step 3: performing ion implantation on the surface of the active region of the N-epitaxial structure to form a super junction active region; Step 4: performing ion implantation on the surface of the terminal region of the N-epitaxial structure to form a JTE-Rings region; Step 5: Repeat steps 2-4 to form an epitaxial layer with a multi-layer epitaxial structure; wherein the number of JTE-Rings regions in each epitaxial structure increases sequentially from bottom to top to form a step from the lower left to the upper right Type JTE-Rings terminal; Step 6: A layer of N-epitaxial structure is grown again on the surface of the sample obtained in Step 5, and ion implantation is performed to form a surface termination region. 8 . A semiconductor power device, characterized by comprising the stepped JTE-Rings super junction power device termination structure according to any one of claims 1 to 6 .

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