CN114883401A - Current carrier storage trench gate IGBT - Google Patents

Abstract

The embodiment of the present invention discloses a carrier storage trench gate IGBT, which includes a collector electrode; a first conductivity type collector region, a second conductivity type buffer zone, a second conductivity type drift region, and a first conductive type body region; at least two gate trenches; the surface of the first conductive type body region surrounded by the first gate trench is provided with a second conductive type source region, a carrier storage layer; a first conductive type drift region A shielding doping region is provided, the shielding doping region is located between the second gate trench and the first gate trench, and the depth of the shielding doping region is greater than that of the first gate trench and the drift of the second gate trench in the first conductivity type The depth of the region, and surrounds the second gate trench and the bottom of the first gate trench; insulating layer; emitter. The invention can greatly improve the concentration of the carrier storage layer, enhance the conductance modulation effect, reduce the on-voltage drop of the device, ensure the withstand voltage of the device, and improve the reliability of the device.

Description

A carrier storage trench gate IGBT

technical field

Embodiments of the present invention relate to the technical field of semiconductor power devices, and in particular, to a carrier storage trench gate IGBT.

Background technique

As a core power electronic device, the insulated gate bipolar thyristor (IGBT) is widely used in rail transit, smart grid, new energy vehicles due to its advantages of fast switching speed, low loss and simple driving circuit. and home appliances.

In the prior art, a carrier storage trench gate bipolar transistor (Carrier Stored Trench Gate Bipolar Transistor, CSTBT) with a P-body region is formed by adding a layer of current carrier between the P-body region and the N-drift region. The sub-storage layer can enhance the conductance modulation effect, thereby reducing the turn-on voltage drop of the device. The higher the doping concentration of the carrier storage layer, the better the conductance modulation effect and the lower the on-voltage drop. However, with the increase of the doping concentration of the carrier storage layer, the withstand voltage of the device will become lower and lower. Therefore, the structure of the CSTBT needs to be optimized and improved.

SUMMARY OF THE INVENTION

The invention provides a carrier storage trench gate IGBT, which can greatly increase the concentration of the carrier storage layer, greatly enhance the conductance modulation effect, greatly reduce the on-voltage drop of the device, and ensure the withstand voltage of the device, thereby Improve device reliability.

The present invention provides a carrier storage trench gate IGBT, the IGBT includes:

collector;

a first-conductivity-type collector region, a second-conductivity-type buffer zone, a second-conductivity-type drift region, and a first-conductivity-type body region disposed on one side of the collector;

At least two gate trenches, the gate trenches extending from the surface of the first conductivity type body region to the second conductivity type drift region, the gate trenches including a first gate trench and at least one first gate trench Two gate trenches, the second gate trenches are arranged around the first gate trench;

A surface of the first conductive type body region surrounded by the first gate trench is provided with a second conductive type source region, and a groove is provided in the middle of the second conductive type source region, and the groove extends to the second conductive type source region. a conductive type body region;

a carrier storage layer, the carrier storage layer is located on the surface of the second conductivity type drift region surrounded by the first gate trench and adjacent to the first conductivity type body region;

The first conductive type drift region is provided with a shielding doping region, the shielding doping region is located between the second gate trench and the first gate trench, and the depth of the shielding doping region is greater than that of the shielding doping region. the depths of the first gate trench and the second gate trench in the drift region of the first conductivity type, and surround the bottom of the second gate trench and the first gate trench;

an insulating layer covering the gate trench and the source region of the second conductivity type;

an emitter electrode, which covers the insulating layer and the bottom and sidewalls of the groove.

Optionally, the number of the second gate trenches includes at least two, the shielding doping region is located between two adjacent second gate trenches, and the depth of the shielding doping region is greater than that of the first gate trenches. The two gate trenches are at the depth of the drift region of the first conductivity type and surround the bottoms of two adjacent second gate trenches.

Optionally, shielding doped regions between the first gate trench and the second gate trench are connected;

The shielding doped regions are connected between two adjacent second gate trenches.

Optionally, the carrier storage layer includes a second conductivity type carrier storage layer.

Optionally, the shielding doped regions include shielding doped regions of the first conductivity type.

Optionally, the first conductivity type ion implantation energy of the shielding doped region is greater than the first conductivity type ion implantation energy of the first conductivity type body region.

Optionally, the ion implantation energy of the first conductivity type of the shielding doped region is 120Kev˜240Kev.

Optionally, a gate oxide layer and a polysilicon gate are arranged in the gate trench, and the gate oxide layer surrounds the polysilicon gate.

Optionally, the depth of the shielding doped region is larger than the depth of the gate trench by 0.5um˜1.5um.

Optionally, the first conductivity type includes N-type, and the second conductivity type includes P-type;

Alternatively, the first conductivity type includes a P-type, and the second conductivity type includes an N-type.

In the technical solution of this embodiment, the carrier storage layer can be effectively shielded by increasing the shielding doping region, so that the withstand voltage of the device is hardly affected by the doping concentration of the carrier storage layer, which solves the problem of the current carrier storage layer in the prior art. The increase in the doping concentration of the sub-storage layer leads to the problem of lowering the withstand voltage of the device. By shielding the carrier storage layer by shielding the doping region and increasing the doping concentration of the carrier storage layer, the on-voltage drop of the device can be reduced without affecting the The withstand voltage of the device and the increased shielding doping area can also reduce the electric field peak value at the bottom of the gate trench, play a certain protective role, and enhance the reliability of the device.

It should be understood that the content described in this section is not intended to identify key or critical features of the embodiments of the invention, nor is it intended to limit the scope of the invention. Other features of the present invention will become readily understood from the following description.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort.

1 is a schematic structural diagram of a carrier storage trench gate IGBT according to an embodiment of the present invention;

2 is a schematic structural diagram of another carrier storage trench gate IGBT provided according to an embodiment of the present invention;

3 is a schematic structural diagram of another carrier storage trench gate IGBT provided according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of yet another carrier storage trench gate IGBT according to an embodiment of the present invention.

Detailed ways

In order to make those skilled in the art better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only Embodiments are part of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

It should be noted that the terms "first", "second" and the like in the description and claims of the present invention and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific sequence or sequence. It is to be understood that the data so used may be interchanged under appropriate circumstances such that the embodiments of the invention described herein can be practiced in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "having" and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those expressly listed Rather, those steps or units may include other steps or units not expressly listed or inherent to these processes, methods, products or devices.

At present, the mainstream technology of IGBT is based on trench gate structure, combined with carrier storage and field termination technology to form CSTBT. 1 is a schematic structural diagram of a carrier storage trench gate IGBT according to an embodiment of the present invention. Referring to FIG. 1 , the structure includes: a collector 10 , a first conductivity type collector region 20 , and a second conductivity type buffer region 30, second conductivity type drift region 40 and first conductivity type body region 50; gate trench 60 includes gate oxide layer 61 and polysilicon gate 62, second conductivity type source region 70 and groove 701, carrier storage layer 80 , insulating layer 90 and emitter 100 .

Optionally, the first conductivity type includes N type, and the second conductivity type includes P type; or, the first conductivity type includes P type, and the second conductivity type includes N type. In the embodiment of the present invention, the first conductivity type includes P-type and the second conductivity type includes N-type as an example for description.

It can be seen from FIG. 1 that in this structure, a carrier storage layer 80 is added between the first conductivity type body region 50 and the first conductivity type drift region 40 to block holes, thereby improving the first conductivity type. The carrier concentration under the conductive type body region 50 enhances the conductance modulation effect and greatly reduces the turn-on voltage drop of the device. However, the density of the gate trenches 60 in this structure is high, and the problem of degradation of the short circuit capability of the device is likely to occur.

In order to solve the problem that the short-circuit capability of the device is degraded due to the high channel density in the above-mentioned embodiment, the embodiment of the present invention adopts the method of reducing the channel, and does not make a hole contact between part of the gate trenches 60 . FIG. 2 is a schematic structural diagram of another carrier storage trench gate IGBT provided according to an embodiment of the present invention. Referring to FIG. 2, the structure can not only enhance the short-circuit resistance of the device, but also optimize the carrier distribution and enhance the conductance. modulation effect, thereby further reducing the device turn-on voltage drop. In this structure, a carrier storage layer 80 is added between the first conductivity type body region 50 and the first conductivity type drift region 40, but the doping concentration of the carrier storage layer 80 cannot be very high, otherwise it will decrease withstand voltage of the device.

In view of the above-mentioned defect that the high doping concentration of the carrier storage layer 80 causes the device withstand voltage to decrease, an embodiment of the present invention provides a carrier storage trench gate IGBT, and FIG. 3 is another embodiment of the present invention. A schematic structural diagram of a carrier storage trench gate IGBT, referring to FIG. 3 , the IGBT includes: a collector 10 ; The second conductive type drift region 40 and the first conductive type body region 50; at least two gate trenches 60, the gate trenches 60 extend from the surface of the first conductive type body region 50 into the second conductive type drift region 40, the gate The trench 60 includes a first gate trench 601 and at least one second gate trench 602 , the second gate trench 602 is arranged around the first gate trench 601 ; the first conductive type body region 50 surrounded by the first gate trench 601 A second conductivity type source region 70 is arranged on the surface of the second conductivity type source region 70, a groove 701 is arranged in the middle of the second conductivity type source region 70, and the groove 701 extends into the first conductivity type body region 50; the carrier storage layer 80, the current carrier The sub-storage layer 80 is located on the surface of the second conductive type drift region 40 surrounded by the first gate trench 601 and adjacent to the first conductive type body region 50; 401 is located between the second gate trench 602 and the first gate trench 601, and the depth of the shielding doped region 401 is greater than the depths of the first gate trench 601 and the second gate trench 602 in the first conductivity type drift region 40, And surround the bottom of the second gate trench 602 and the first gate trench 601; the insulating layer 90, the insulating layer 90 covers the gate trench 60 and the second conductive type source region 70; the emitter 100, the emitter 100 covers the insulating layer 90 and the bottom and side walls of groove 701.

Continuing to refer to FIG. 3 , optionally, the first conductivity type includes N-type, and the second conductivity type includes P-type; or, the first conductivity type includes P-type, and the second conductivity type includes N-type.

Specifically, the first conductive type body region 50 and the second conductive type source region 70 may be formed in the second conductive type drift region 40 through an ion implantation process. The ions implanted in the first conductivity type body region 50 are opposite to those doped in the second conductivity type drift region 40 , and the ions implanted in the second conductivity type source region 70 are doped with the second conductivity type drift region 40 . The ion types are the same.

For example, the ions doped in the drift region 40 of the second conductivity type are pentavalent elements (phosphorus or arsenic) to form an N-type drift region, and the ions implanted in the body region 50 of the first conductivity type are trivalent elements (boron or fluoride) Boron), the ions implanted in the source region 70 of the second conductivity type are of the same type as the ions doped in the drift region 40 of the second conductivity type, and can also be pentavalent phosphorus or arsenic.

It should be noted that FIG. 3 only exemplarily shows that the first conductivity type collector region 20 is a heavily doped P+ region, the second conductivity type buffer region 30 is a heavily doped N+ region, and the second conductivity type drifts The region 40 is a lightly doped N- region, the first conductive type body region 50 is a lightly doped P- region, and the second conductive type source region 70 is a heavily doped N+ region.

Specifically, in the embodiment of the present invention, in the drift region 40 of the second conductivity type, the shielding doped region 401 is formed by impurity implantation and diffusion push junction. The depth of the shielding doped region 401 is greater than the depth of the first gate trench 601 and the second gate trench 602 in the first conductivity type drift region 40, and surrounds the bottom of the second gate trench 602 and the first gate trench 601; When the device is subjected to a reverse voltage, the shielding doped regions 401 under the first conductive type body region 50 expand, and as the reverse voltage increases, the adjacent shielding doped regions 401 get closer and closer, and finally connect together, In this way, the carrier storage layer 80 is shielded, so that the withstand voltage of the device is hardly affected by the doping concentration of the carrier storage layer 80 . Therefore, the doping concentration of the carrier storage layer 80 can be made higher. When the device is in forward conduction, the higher doping concentration of the carrier storage layer 80 can better block holes, greatly enhance the conductance modulation effect, and greatly reduce the turn-on voltage drop of the device. At the same time, since the increased shielding doping region 401 encloses the bottoms of the second gate trench 602 and the first gate trench 601, the electric field peaks at the bottoms of the second gate trench 602 and the first gate trench 601 are reduced, and the To a certain degree of protection, the reliability of the device is improved.

In the technical solution of this embodiment, the carrier storage layer can be effectively shielded by increasing the shielding doping region, so that the withstand voltage of the device is hardly affected by the doping concentration of the carrier storage layer, which solves the problem of the current carrier storage layer in the prior art. The increase in the doping concentration of the sub-storage layer leads to the problem of lowering the withstand voltage of the device. By shielding the carrier storage layer by shielding the doping region and increasing the doping concentration of the carrier storage layer, the on-voltage drop of the device can be reduced without affecting the The withstand voltage of the device and the increased shielding doping area can also reduce the electric field peak value at the bottom of the gate trench, play a certain protective role, and enhance the reliability of the device.

4 is a schematic structural diagram of another carrier storage trench gate IGBT provided according to an embodiment of the present invention. Referring to FIG. 4 , optionally, the number of the second gate trenches 602 includes at least two, shielding the doped regions 401 is located between two adjacent second gate trenches 602, the depth of the shielding doped region 401 is greater than the depth of the second gate trench 602 in the first conductivity type drift region 40, and surrounds the adjacent two second gate trenches 602 bottom of.

Specifically, the depth of the shielding doped region 401 is greater than the depth of the second gate trench 602 in the first conductivity type drift region 40 and surrounds the bottoms of two adjacent second gate trenches 602. The shielding of the doped region 401 can improve the adjacent The electric field concentration effect at the bottom of the two second gate trenches 602 will not cause an excessive electric field peak value to affect the breakdown voltage, so that the maximum electric field peak value is effectively reduced, thereby greatly increasing the device breakdown voltage.

The setting of the shielding doping region 401 effectively ensures the function of the carrier storage layer 80, so that the doping concentration of the carrier storage layer 80 is further increased, which can better block holes and greatly enhance the The conductance modulation effect is improved, the on-voltage drop of the device is greatly reduced, the withstand voltage of the device is ensured, and the reliability of the device is improved.

Continuing to refer to FIG. 4 , optionally, the shielding doped regions 401 between the first gate trench 601 and the second gate trench 602 are connected;

The shielding doped regions 401 are connected between two adjacent second gate trenches 602 .

Specifically, when the device is subjected to the reverse voltage, the depletion layer of the shielding doping region 401 gradually expands, and as the reverse voltage increases, the depletion layers of the adjacent shielding doping regions 401 get closer and closer. The shielding doped regions 401 between the gate trenches 601 and the second gate trenches 602 are connected, the shielding doped regions 401 between two adjacent second gate trenches 602 are connected, and finally the shielding doped regions 401 are connected together. The carrier storage layer 80 is shielded, so that the withstand voltage of the device is hardly affected by the doping concentration of the carrier storage layer 80 . Therefore, the doping concentration of the carrier storage layer 80 can be made higher. In this way, when the device is in forward conduction, the carrier storage layer 80 with higher doping concentration can better block holes, greatly enhance the conductance modulation effect, and greatly reduce the on-voltage drop of the device .

With continued reference to FIG. 4 , the carrier storage layer 80 optionally includes a second conductivity type carrier storage layer.

The carrier storage layer 80 may be a P-type carrier storage layer or an N-type carrier storage layer. The carrier storage layer 80 can optimize the distribution of carriers in the drift region 40 of the second conductivity type, and greatly reduce the forward voltage drop of the device.

With continued reference to FIG. 4 , optionally, the shield doped region 401 includes a shield doped region of the first conductivity type.

The shielding doping region 401 may be a P-type shielding doping region or an N-type shielding doping region. The introduction of the shielding doped region 401 improves the electric field concentration effect at the bottom of the gate trench 60, so that the breakdown voltage of the device is improved. The existence of the shielding doped region 401 effectively ensures the function of the carrier storage layer 80, so that the thickness and concentration of the carrier storage layer 80 can be further increased, and the forward voltage drop can be further reduced.

It should be noted that FIG. 4 only exemplarily shows the case where the carrier storage layer 80 is an N-type carrier storage layer, and the shielding doped region 401 is a P-type shielding doped region.

Continuing to refer to FIG. 4 , optionally, the first conductivity type ion implantation energy of the shield doped region 401 is greater than the first conductivity type ion implantation energy of the first conductivity type body region 50 .

Specifically, the first conductive type ion material of the shielding doping region 401 can be boron, and the doping concentration can be 10 ¹⁵ -10 ¹⁷ cm ^-3 ; the first conductive type ion material of the first conductive type body region 50 can be boron , the doping concentration can be less than 10 ¹⁵ -10 ¹⁷ cm ^-3 ; the implanted impurity in the drift region 40 of the second conductivity type is phosphorus, and its doping concentration is 10 ¹³ -10 ¹⁴ cm ^-3 ; the implantation of the carrier storage layer 80 The impurity is phosphorus, and its doping concentration is 10 ¹⁵ -10 ¹⁶ cm ^-3 .

The implantation energy of the shielding doped region 401 is greater than the implantation energy of the first conductive type body region 50 , and diffusion push junction is performed, so that there is an additional layer of shielding doping region 401 under the first conductive type body region 50 , and the shielding doping region 401 The setting of the carrier storage layer 80 can further increase the doping concentration of the carrier storage layer 80, which can better block holes, greatly enhance the conductance modulation effect, greatly reduce the on-voltage drop of the device, and ensure the device’s performance. withstand voltage, which improves the reliability of the device.

Continuing to refer to FIG. 4 , optionally, the ion implantation energy of the first conductivity type of the shield doped region 401 is 120Kev˜240Kev.

Specifically, the implantation energy of the shielding doped region 401 is greater than the implantation energy of the first conductivity type body region 50 . Exemplarily, the implantation energy of the shielding doped region 401 may be 120Kev˜240Kev, and the implantation energy of the first conductivity type body region 50 The energy can be from 60Kev to 100Kev.

Continuing to refer to FIG. 4 , optionally, a gate oxide layer 61 and a polysilicon gate electrode 62 are provided in the gate trench 60 , and the gate oxide layer 61 surrounds the polysilicon gate electrode 62 .

The gate oxide layer 61 and the polysilicon gate 62 form the gate trench 60 structure. The gate oxide layer 61 can be grown by a high-density plasma chemical vapor deposition method and a thermal oxidation method or alternately used. The polysilicon gate 62 may be formed by chemical vapor deposition.

Continuing to refer to FIG. 4 , optionally, the depth of the shielding doped region 401 is greater than the depth of the gate trench 60 by 0.5um˜1.5um.

The depth of the shielding doped region 401 is 0.5-1.5um larger than that of the gate trench 60, which can reduce the electric field peak value at the bottom of the gate trench 60, play a certain protective role, and enhance the reliability of the device.

The above-mentioned specific embodiments do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may occur depending on design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (10)

1. a carrier storage trench gate IGBT, is characterized in that, comprises: collector; a first-conductivity-type collector region, a second-conductivity-type buffer zone, a second-conductivity-type drift region, and a first-conductivity-type body region disposed on one side of the collector; At least two gate trenches, the gate trenches extending from the surface of the first conductivity type body region to the second conductivity type drift region, the gate trenches including a first gate trench and at least one first gate trench Two gate trenches, the second gate trenches are arranged around the first gate trench; A surface of the first conductive type body region surrounded by the first gate trench is provided with a second conductive type source region, and a groove is provided in the middle of the second conductive type source region, and the groove extends to the second conductive type source region. a conductive type body region; a carrier storage layer, the carrier storage layer is located on the surface of the second conductivity type drift region surrounded by the first gate trench and adjacent to the first conductivity type body region; The first conductive type drift region is provided with a shielding doping region, the shielding doping region is located between the second gate trench and the first gate trench, and the depth of the shielding doping region is greater than that of the shielding doping region. the depths of the first gate trench and the second gate trench in the drift region of the first conductivity type, and surround the bottom of the second gate trench and the first gate trench; an insulating layer covering the gate trench and the source region of the second conductivity type; an emitter electrode, which covers the insulating layer and the bottom and sidewalls of the groove. 2 . The IGBT according to claim 1 , wherein the number of the second gate trenches includes at least two, and the shielding doping region is located between two adjacent second gate trenches, so the The depth of the shielding doping region is greater than the depth of the second gate trench in the drift region of the first conductivity type, and surrounds the bottoms of two adjacent second gate trenches. 3. The IGBT according to claim 2, wherein the shielding doped regions between the first gate trench and the second gate trench are connected; The shielding doped regions are connected between two adjacent second gate trenches. 4. The IGBT of claim 1, wherein the carrier storage layer comprises a second conductivity type carrier storage layer. 5 . The IGBT of claim 1 , wherein the shielding doped region comprises a first conductive type shielding doped region. 6 . 6 . The IGBT of claim 5 , wherein the first conductivity type ion implantation energy of the shielding doped region is greater than the first conductivity type ion implantation energy of the first conductivity type body region. 7 . 7 . The IGBT according to claim 5 , wherein the ion implantation energy of the first conductivity type of the shielding doped region is 120Kev˜240Kev. 8 . 8 . The IGBT according to claim 1 , wherein a gate oxide layer and a polysilicon gate are provided in the gate trench, and the gate oxide layer surrounds the polysilicon gate. 9 . 9 . The IGBT according to claim 1 , wherein the depth of the shielding doped region is greater than the depth of the gate trench by 0.5um˜1.5um. 10 . 10. The IGBT of claim 1, wherein the first conductivity type comprises N-type, and the second conductivity type comprises P-type; Alternatively, the first conductivity type includes a P-type, and the second conductivity type includes an N-type.

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