CN114911738A

CN114911738A - FPGA pin multiplexing method based on signal phase, electronic device and medium

Info

Publication number: CN114911738A
Application number: CN202210510990.8A
Authority: CN
Inventors: 李春峰; 黄建锋
Original assignee: Beijing Yunshu Innovation Software Technology Co ltd; Shanghai Hejian Industrial Software Group Co Ltd
Current assignee: Beijing Yunshu Innovation Software Technology Co ltd; Shanghai Hejian Industrial Software Group Co Ltd
Priority date: 2022-05-11
Filing date: 2022-05-11
Publication date: 2022-08-16
Anticipated expiration: 2042-05-11
Also published as: CN114911738B

Abstract

The invention relates to a signal phase-based FPGA pin multiplexing method, electronic equipment and a medium, comprising a step S1 of acquiring a TDM high-speed clock period T of an FPGA and N pieces of signal set information { S) designed by a chip ₁ ，S ₂ ,…S _N },S _n ＝{A _n ,R _n ,T _n ,P _n ,a _n ,b _n }; step S2, if the phase difference P between the nth signal set and the n-1 st signal set is satisfied at the same time _n ‑P _n‑1 >(R _n‑1 *b _n‑1 +a _n‑1 ) T, phase difference P of Nth signal set and first signal set _N ‑P ₁ <T ₁ ‑[(R _N *b _N +a _N )*T]，T ₁ ≤T _N ，

Then executeStep S3; step S3, a _n Individual clock domain identification and/or check identification is added to b _n A is _n In (1), produce A _n’ According to A _1’ ，A _2’ ,…A _N’ The sequence of which sends the signals from the first FPGA pin to the second FPGA pin in sequence. The invention improves the multiplexing rate of the FPGA pin under the condition of not increasing signal delay based on the constraint condition corresponding to the signal set phase.

Description

FPGA pin multiplexing method based on signal phase, electronic device and medium

Technical Field

The invention relates to the technical field of chips, in particular to a signal phase-based FPGA pin multiplexing method, electronic equipment and a medium.

Background

In a chip emulation (emulation) system and a chip prototype (prototype) system, they are generally implemented based on a plurality of FPGAs. In a chip simulation (emulation) system and a chip prototype (prototype) system, signal transmission between chips is realized through connection between pins of an FPGA. Since the number of signals is much larger than the number of pins of the FPGA, it is usually necessary to multiplex a plurality of user signals with one FPGA pin to transfer the signals. However, in the prior art, the more signals are multiplexed, the greater the delay of the signals from one FPGA pin to another FPGA pin is, and the lower the operating frequency of the chip design is, which is usually a decisive factor affecting the performance of the chip simulation system and the chip prototype system. Therefore, it is known how to improve the multiplexing rate of the FPGA pins without increasing the signal delay, and further improve the operating frequency of the chip design, so as to improve the performance of the chip simulation system and the chip prototype system.

Disclosure of Invention

The invention aims to provide an FPGA pin multiplexing method based on signal phase, electronic equipment and a medium, which improve the multiplexing rate of FPGA pins under the condition of not increasing signal delay.

According to a first aspect of the present invention, there is provided a signal phase-based FPGA pin multiplexing method, including:

step S1, obtaining TDM high-speed clock period T of FPGA, N pieces of signal set information { S ] of chip design ₁ ，S ₂ ,…S _N The FPGA is used for realizing the function of chip design, wherein S _n Is the nth signal set information, and the value range of N is 1 to N, S _n ＝{A _n ,R _n ,T _n ,P _n ,a _n ,b _n },A _n Is S _n The nth signal set of (a), different signal sets belonging to different clock domains; r _n Is S _n TDM multiplex proportion of (T) _n Is S _n Clock period of (D), P ₁ Is S ₁ At the moment of one of the clock rising edges, P _n+1 Is at P _n Then S _n+1 At the time of the first clock rising edge of (2), P ₁ <P ₂ <…P _N ，a _n Is A _n The reserved signal is used for storing clock domain identification and/or check identification, a _n ≥1；b _n Is A _n Number of transmissions of b _n ≥1；

Step S2, if the phase difference P between the nth signal set and the n-1 st signal set is satisfied at the same time _n -P _n-1 >(R _n-1 *b _n-1 +a _n-1 ) T, phase difference P of Nth signal set and first signal set _N -P ₁ <T ₁ -[(R _N *b _N +a _N )*T]，T ₁ ≤T _N ，

Step S3 is executed;

step S3, a _n Individual clock domain identification and/or check identification is added to b _n A is _n In (1), produce A _n ', according to A ₁ ’，A ₂ ’,…A _N The sequence of' sends signals from the first FPGA pin to the second FPGA pin in turn.

According to a second aspect of the present invention, there is provided an electronic apparatus comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of the first aspect of the invention.

According to a third aspect of the invention, there is provided a computer readable storage medium, the computer instructions being for performing the method of the first aspect of the invention.

Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the FPGA pin multiplexing method based on the signal phase, the electronic equipment and the medium can achieve considerable technical progress and practicability, have wide industrial utilization value and at least have the following advantages:

according to the method, under the condition that signal delay is not increased, based on the constraint condition corresponding to the signal phase relation, the invalid data transmission time slot of the first signal set is used for transmitting signals of other signal sets, the multiplexing rate of the FPGA pin is improved, the running frequency of chip design is further improved, and the performance of a chip simulation system and a chip prototype system is improved.

The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.

Drawings

Fig. 1 is a flowchart of an FPGA pin multiplexing method based on signal phases according to an embodiment of the present invention;

fig. 2 is a schematic diagram of data transmission of a clock domain signal set multiplexing FPGA pin in the prior art.

Detailed Description

To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description will be given to specific embodiments and effects of an FPGA pin multiplexing method, an electronic device and a medium based on signal phases according to the present invention with reference to the accompanying drawings and preferred embodiments.

An embodiment of the present invention provides a signal phase-based FPGA (Field-Programmable Gate Array) pin multiplexing method, as shown in fig. 1, including:

step S1, obtaining TDM (Testing Data Management/Technical Data Management) high-speed clock period T of FPGA, N pieces of signal set information of chip design { S1, S2, … S _N The FPGA is used for realThe function of the chip design is now described.

Wherein S is _n Is the nth signal set information, and the value range of N is 1 to N, S _n ＝{A _n ,R _n ,T _n ,P _n ,a _n ,b _n },A _n Is S _n Different signal sets belong to different clock domains. R _n Is S _n The TDM multiplexing ratio of (A) is understood to be _n Including R _n Signals belonging to the same clock domain, R _n The value of (c) may satisfy the frequency requirement of the nth signal set. T is _n Is S _n Is, it can be understood that T _n And is more than or equal to T so as to realize TDM. P ₁ Is S ₁ At the moment of one of the clock rising edges, P _n+1 Is at P _n Then S _n+1 At the moment of the first clock rising edge of (1), P ₁ <P ₂ <…P _N 。a _n Is A _n The reserved signal bits are used for storing clock domain identification and/or check identification, a _n ≥1；b _n Is A _n Number of transmissions of (b) _n Not less than 1. Note that, in order to prevent signal transmission failure due to system jitter or the like, a signal is generally transmitted multiple times to increase the transmission success rate, and therefore, b _n Can be set according to specific redundancy requirements, preferably, b _n 2. It will be appreciated that if redundancy is not required, b _n May be set to 1. The value of N is too large, which may increase signal delay, and is preferably less than or equal to 3.

Step S3 is executed.

As an embodiment, if N is 2, the first signal set and the second signal set multiplex one FPGA pin, and the first signal set and the second signal set must satisfy:

phase difference P of the second signal set and the first signal set ₂ -P ₁ >(R ₁ *b ₁ +a ₁ ) T to ensure that in a round of multiplexing, the signals of the second signal set are transmitted after the transmission of the first signal set is completed.

Phase difference P of the second signal set and the first signal set ₂ -P ₁ <T ₁ -(R ₂ *b ₂ +a ₂ ) T to ensure that the signals of the second signal set are transmitted before and after the signals of the first signal set are transmitted in the next round of multiplexing, so that the transmission of the signals of the first signal set is not affected.

In addition, T is also required to be satisfied ₁ ≤T ₂ ，

Therefore, the second signal set and the third signal set … are ensured to transmit signals by using the invalid data transmission time slot of the first signal set, and the utilization rate of the FPGA pins is improved.

As an embodiment, if N is 3, the first signal set, the second signal set, and the third signal set multiplex one FPGA pin, and the first signal set, the second signal set, and the third signal set must satisfy:

phase difference P of the second signal set and the first signal set ₂ -P ₁ >(R ₁ *b ₁ +a ₁ )*T。

Phase difference P of third signal set and second signal set ₃ -P ₂ >(R ₂ *b ₂ +a ₂ )*T。

Third signal set phase difference P of first signal set ₃ -P ₁ <T ₁ -(R ₃ *b ₃ +a ₃ ) T to ensure that the signals of the second signal set are transmitted before and after the signals of the first signal set are transmitted in the next round of multiplexing, so that the transmission of the signals of the first signal set is not affected.

It should be noted that, in the prior art, pin multiplexing is, as shown in fig. 2 as an example, independently multiplexed for each signal set, that is, multiplexing is separately set for each clock domain. In fig. 2, TDM clock is denoted by TDM _ clk, TDM _ tx denotes data transmission of a transmitting-end FPGA pin, and TDM _ rx denotes data transmission of a receiving-end FPGA pin, and if T is 0.714ns and the multiplexing ratio is 8:1, the minimum period of a user is T3-T1-50 ns in the case of 1m cable, but as can be seen from fig. 2, the transmission time of valid data is only T3-T2-0.714-8-5.712 ns, which means that the time of T2-T1-50-5.712-44.288 ns is wasted, and the utilization rate is only 8/(50/0.714) ═ 11%. In the embodiment of the invention, by judging the signal phase, the signal sets of other clock domains are added in the t2-t1 for FPGA pin multiplexing under the condition of not influencing the signal set signal transmission in the figure 2, so that the utilization rate of the FPGA pin is improved.

According to the method, under the condition that signal delay is not increased, signals of other signal sets are transmitted by using the invalid data transmission time slot of the first signal set based on the constraint condition corresponding to the signal phase relation, the multiplexing rate of the FPGA pins is improved, the running frequency of chip design is further improved, and the performance of a chip simulation system and a chip prototype system is improved. The invalid data transmission time slot of the first signal set refers to the time taken for the first signal pin to transmit the first signal set in one period from the first FPGA pin to the second FPGA pin in the one period, and is subtracted by the time taken for the second FPGA pin to receive the first signal set, and it can be understood that the time taken for the first signal set to transmit the first signal set in the one period from the first FPGA pin is equal to the time taken for the first signal set to transmit the first signal set in the one period from the first FPGA pin.

As a kind ofExample A ₁ ' begin sending signals from the first FPGA pin to the second FPGA pin to receive all { A ₁ ’，A ₂ ’,…A _N ' } time period, as one multiplexing period TW, for the ith multiplexing period TW _i In step S3, the method includes:

step S31, at TW _i At the start position, n is set to 1.

Step S32, A _n ' continuously transmits the first FPGA pin to the second FPGA pin, and executes the step S33 after the transmission is finished.

In step S33, if N < N, N is set to N +1, the process returns to step S32, and if N is set to N, i is set to i +1, and the process returns to step S31.

It should be noted that the clock domain identifier is used to distinguish which clock domain the signal in the signal set belongs to, the check identifier is used to check the signal, the adding manner of the clock domain identifier and the check identifier is flexible, and the clock domain identifier and the check identifier can be added to corresponding positions according to specific application requirements as long as the function of distinguishing the signal clock domain or checking can be realized. As an example of the way in which the liquid is introduced,

as an example, a _n In step S3, when the number of the first frames is 1, b is _n A is _n First of (A) _n Adding A to the head of _n Clock domain identification of, generate A _n ’。

As an example, a _n ≧ 2, in the step S3, at least b _n A is _n First of (A) _n The first addition of A _n Clock domain identification of (1), in b _n A is _n At least one A of _n And adding a check mark at the tail part of the terminal. For example at each A _n Adding A to the first position of _n Clock domain identification of (A), each _n In (5) adding A to the tail _n The check mark of (2). Or, in b _n A is _n First of (A) _n Adding A to the first position of _n Clock domain identification of (1), in b _n A is _n Last one of A _n And adding a check mark at the tail part of the terminal. It should be noted that the number of the clock domain identifiers and the number of the check identifiers may be one or more, and are flexibly set according to application requirements.

As an example, a _j ≧ 2, in the step S3, in b _n A is _n At least one A is added to the head of each p bits _j The clock domain of (1) and the spare bits of the last p bits are added with A _j The check mark of (2). And the corresponding clock domain identifier is set for each P bit, so that the signal sequencing is more orderly and the processing is convenient. As exemplified in table 1.

Bit0

Bit1

Bit2

Bit3

Bit4

Bit5

Bit6

Bit7

0:dataset0

data0

data1

data2

data3

data4

data5

data6

0:dataset0

data7

data0

data1

data2

data3

data4

data5

0:dataset0

data6

data7

crc0

crc1

crc2

crc3

crc4

1:dataset1

data8

data9

data10

data11

data12

data13

data14

1:dataset1

data8

data9

data10

data11

data12

data13

data14

1:dataset1

data8

data9

data10

data11

data12

data13

data14

TABLE 1

In Table 1, the 0 th bit of every 8 bits is used for signal indication, 0: dataset0 represents the first signal set, and 1: dataset1 represents the second signal set. The data of the first set of signals are all in the same clock domain. The signals of the second set of signals are all of the other clock domain. The signal phase of the first signal set of the second signal set satisfies the conditions set forth in step S2. crc denotes a check mark. Table 1 is only an example, and the number and the positions of the clock domain identifier and the check identifier may be flexibly set. In addition, compared with the multiplexing ratio of the pins of the FPGA in the prior art shown in fig. 2, in the example of table 1, the multiplexing ratio of the pins of the FPGA is increased from 8:1 to 15:1, and the multiplexing rate of the pins of the FPGA is increased.

As an embodiment, the method further comprises:

step S4, when { A ₁ ’，A ₂ ’,…A _N And the signal in the' reaches the pin of the second FPGA, the currently received signal is analyzed, and the current target clock domain is determined based on the clock domain mark obtained by current analysis.

It is understood that when { A } ₁ ’，A ₂ ’,…A _N The arrival of the signal in the' at the second FPGA pin means that there is a { A } ₁ ’，A ₂ ’,…A _N When the signal in' } reaches the second FPGA pin, { A } ₁ ’，A ₂ ’,…A _N The signal in' } is sent continuously to the second FPGA pin.

Step S5, if the corresponding check bit identification exists, the received signal is checked, if the check passes, the signal is sent to the current target clock domain after synchronous operation, and if the check bit does not exist, the signal is sent to the current target clock domain after synchronous operation;

and step S6, if a new clock domain identifier is obtained through analysis, updating the current target clock domain based on the new clock domain identifier.

The signals transmitted from the first FPGA pin to the second FPGA pin can be demultiplexed through the steps of 5-S6, signal synchronization is performed through calibration logic, if a check mark exists, the signals can be checked through the check logic to determine whether a link has an error, and if the link has the error, prompt information can be sent.

It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently or simultaneously. In addition, the order of the steps may be rearranged. A process may be terminated when its operations are completed, but may have additional steps not included in the figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.

An embodiment of the present invention further provides an electronic device, including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions configured to perform a method according to an embodiment of the invention.

The embodiment of the invention also provides a computer-readable storage medium, and the computer instructions are used for executing the method of the embodiment of the invention.

Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. An FPGA pin multiplexing method based on signal phase is characterized by comprising the following steps:

step S1, obtaining TDM high-speed clock period T of FPGA, N pieces of signal set information { S ] of chip design ₁ ，S ₂ ,…S _N The FPGA is used for realizing the function of chip design, wherein S _n Is the nth signal set information, and the value range of N is 1 to N, S _n ＝{A _n ,R _n ,T _n ,P _n ,a _n ,b _n },A _n Is S _n The nth signal set of (a), different signal sets belonging to different clock domains; r _n Is S _n TDM multiplex proportion of (T) _n Is S _n Clock period of (D), P ₁ Is S ₁ At the moment of one of the clock rising edges, P _n+1 Is at P _n Then S _n+1 At the moment of the first clock rising edge of (1), P ₁ <P ₂ <…P _N ，a _n Is A _n The reserved signal is used for storing clock domain identification and/or check identification, a _n ≥1；b _n Is A _n Number of transmissions of b _n ≥1；

Step S3 is executed;

step S3, a _n Individual clock domain identification and/or check identification is added to b _n A is _n In (1), produce A _n ', according to A ₁ ’，A ₂ ’,…A _N ' the sequence sequentially transfers signals fromAnd the first FPGA pin is sent to the second FPGA pin.

2. The method of claim 1,

a is to be ₁ ' begin sending signals from the first FPGA pin to the second FPGA pin to receive all { A ₁ ’，A ₂ ’,…A _N ' } time period, as one multiplexing period TW, for the ith multiplexing period TW _i In step S3, the method includes:

step S31, at TW _i Setting n to be 1 at the initial position;

step S32, A _n Continuously sending the first FPGA pin to a second FPGA pin, and executing the step S33 after the sending is finished;

3. The method of claim 1,

a _j ≧ 2, in the step S3, in b _n A is _n At least one A is added to the head of each p bits _j Clock domain identification of (1), adding A to the spare bits of the last p bits _j The check mark of (2).

4. The method of claim 1,

further comprising:

step S4, when { A ₁ ’，A ₂ ’,…A _N The signal in the' reaches the second FPGA pin, the currently received signal is analyzed, and the current target clock domain is determined based on the clock domain mark obtained by current analysis;

5. The method of claim 1,

b _n the values of (A) are all 2.

6. The method of claim 1,

n is less than or equal to 3.

7. An electronic device, comprising:

at least one processor;

and a memory communicatively coupled to the at least one processor;

wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of any of the preceding claims 1-6.

8. A computer-readable storage medium having stored thereon computer-executable instructions for performing the method of any one of claims 1-6.