CN114937669B

CN114937669B - Semiconductor device and method for manufacturing the same

Info

Publication number: CN114937669B
Application number: CN202210509148.2A
Authority: CN
Inventors: 王春明; 王绍迪
Original assignee: Beijing Witinmem Technology Co ltd; Hangzhou Zhicun Computing Technology Co ltd
Current assignee: Beijing Witinmem Technology Co ltd; Hangzhou Zhicun Computing Technology Co ltd
Priority date: 2022-05-10
Filing date: 2022-05-10
Publication date: 2025-08-05
Anticipated expiration: 2042-05-10
Also published as: CN114937669A; WO2023216366A1

Abstract

A semiconductor device and a method of manufacturing the same are provided. The method includes sequentially forming a first oxide layer, a memory layer, a second oxide layer, a control gate layer, and a hard mask layer on a substrate, etching the hard mask layer, the control gate layer, the second oxide layer, the memory layer, and the first oxide layer to form a gate stack, forming a first gate spacer and a second gate spacer on both sides of the gate stack, forming a first select gate on a side of the first gate spacer opposite the gate stack, forming a second select gate on a side of the second gate spacer opposite the gate stack, etching the gate stack to form a first opening, forming a source region in a portion of the substrate below the first opening, and forming a first drain region in the substrate on a side of the first select gate opposite the first opening, and forming a second drain region in the substrate on a side of the second select gate opposite the first opening.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method of manufacturing the same.

Background

In electronic devices, it is necessary to read and store data by means of a memory. Thus, as the demand for electronic devices continues to grow, so does the demand for memory technology.

Flash memory is an electrically erasable and reprogrammable, electrically non-volatile computer storage medium that retains on-chip information even after the power supply is turned off. The flash memory has the characteristics of convenient use, reading and writing flexibility, faster access speed and no information loss after power failure, so that the flash memory technology is developed very rapidly.

Flash memory includes an array of addressable memory cells, wherein each memory cell includes a floating gate transistor for storing corresponding information. Accordingly, it is desirable to improve methods of manufacturing flash memories, and in particular memory cells in flash memories.

Disclosure of Invention

According to some embodiments of the present disclosure, a method of manufacturing a semiconductor device is provided, including sequentially forming a first oxide layer, a memory layer, a second oxide layer, a control gate layer, and a hard mask layer on a substrate, etching the hard mask layer, the control gate layer, the second oxide layer, the memory layer, and the first oxide layer to form a gate stack of remaining portions of the hard mask layer, the control gate layer, the second oxide layer, the memory layer, and the first oxide layer, forming a first gate spacer and a second gate spacer on both sides of the gate stack, respectively, and forming a first select gate oxide structure and a second select gate oxide structure on first and second regions of the substrate, respectively, wherein the first and second regions are located on both sides of the gate stack, forming a first select gate on a side of the first gate spacer opposite the gate stack, forming a second select gate on a side of the second gate spacer opposite the gate stack, forming a first select gate in the first region, forming a second gate opening in the first region, and forming a second region in the first region, and forming a second gate opening in the first region.

According to some embodiments of the present disclosure, there is provided a method of manufacturing a semiconductor device, including sequentially forming a first oxide layer, a select gate layer, and a hard mask layer on a substrate, etching the hard mask layer and the select gate layer to form a gate stack composed of the hard mask layer and a remaining portion of the select gate layer, forming a first memory structure on a first side of the gate stack and a first gate region, and forming a second memory structure on a second side of the gate stack and a second gate region, wherein the first gate region is located on one side of the first side of the gate stack, the second gate region is located on one side of the second side of the gate stack, forming a first control gate on the first memory structure, and forming a second control gate on the second memory structure, etching the gate stack to form a first opening through the hard mask layer and the select gate layer, forming a second memory structure on a second side of the gate region located below the first opening, and forming a second control gate region in the substrate opposite the first side of the first gate region, and forming a second control gate in the first side of the substrate opposite the first gate region.

According to some embodiments of the present disclosure, there is provided a semiconductor device manufactured by a method as described in the present disclosure.

These and other aspects of the disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter.

Drawings

Further details, features and advantages of the present disclosure are disclosed in the following description of exemplary embodiments, with reference to the following drawings, wherein:

fig. 1 is a schematic flow chart of a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

Fig. 2A-2G are schematic cross-sectional views of steps of a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

fig. 3A-3M are schematic cross-sectional views of steps of a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

fig. 4A-4B are schematic cross-sectional views of steps of a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

fig. 5 is a schematic cross-sectional view of steps of a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

Fig. 6 is a schematic cross-sectional view of steps of a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

fig. 7 is a schematic cross-sectional structure of a semiconductor device according to some embodiments of the present disclosure;

FIG. 8 is a circuit schematic of a memory cell array according to some embodiments of the present disclosure;

9A-9B are top plan views of memory cell arrays according to some embodiments of the present disclosure;

Fig. 10 is a schematic flow chart of a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

11A-11G are schematic cross-sectional views of steps of a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

fig. 12A-12N are schematic cross-sectional views of steps of a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

Fig. 13A-13B are schematic cross-sectional views of steps of a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

Fig. 14 is a schematic cross-sectional view of steps of a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

fig. 15 is a schematic cross-sectional view of steps of a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

fig. 16 is a schematic cross-sectional structure of a semiconductor device according to some embodiments of the present disclosure;

FIG. 17 is a circuit schematic of a memory cell array according to some embodiments of the present disclosure;

18A-18B are top plan views of memory cell arrays according to some embodiments of the present disclosure.

Detailed Description

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

Spatially relative terms, such as "below," "under," "lower," "under," "above," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "under" or "beneath" other elements or features would then be oriented "over" the other elements or features. Thus, the exemplary terms "below" and "under" may encompass both an orientation of above and below. Terms such as "before" or "before" and "after" or "followed by" may similarly be used, for example, to indicate the order in which light passes through the elements. The device may be oriented in other ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items, and the phrase "at least one of a and B" means a alone, B alone, or both a and B.

It will be understood that when an element or layer is referred to as being "on," "connected to," "coupled to," or "adjacent to" another element or layer, it can be directly on, connected to, coupled to, or adjacent to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to," or "directly adjacent to" another element or layer, there are no intervening elements or layers present. However, in no event "on" or "directly on" should be construed as requiring one layer to completely cover an underlying layer.

Embodiments of the present disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the present disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As used herein, the term "substrate" may refer to a substrate of a diced wafer, or may refer to a substrate of an uncut wafer. Similarly, the terms chip and die may be used interchangeably unless such an interchange would cause a conflict.

Common types of flash memory cells in the prior art include stacked gate memory cells and split gate memory cells. Compared with a stacked gate memory cell, the split gate memory cell has the technical advantages of lower power consumption, higher injection efficiency and the like. For a flash memory having split gate memory cells, the present disclosure provides a method of manufacturing a semiconductor device including sequentially forming a first oxide layer, a memory layer, a second oxide layer, a control gate layer, and a hard mask layer on a substrate, etching the hard mask layer, the control gate layer, the second oxide layer, the memory layer, and the first oxide layer to form a gate stack composed of the hard mask layer, the control gate layer, the second oxide layer, the memory layer, and a remaining portion of the first oxide layer, forming a first gate spacer and a second gate spacer on both sides of the gate stack, respectively, and forming a first select gate oxide structure and a second select gate oxide structure on a first region and a second region of the substrate, respectively, wherein the first region and the second region are located on both sides of the gate stack, forming a first select gate on a side of the first gate spacer opposite the gate stack, and forming a second select gate on a side of the second gate spacer opposite the gate stack, etching the gate stack to form a gate stack through the hard layer, the control gate layer, the first oxide layer, and the second oxide layer, and the first gate spacer, and the first select gate is formed in the first region and the second region is formed in the substrate opposite the first region, and the first region is formed in the first region and the second region is opposite the first region.

Fig. 1 is a schematic flow chart of a method 100 of fabricating a semiconductor device according to some embodiments of the present disclosure.

At step S101, a first oxide layer, a memory layer, a second oxide layer, a control gate layer, and a hard mask layer are sequentially formed on a substrate.

According to some embodiments, the method of manufacturing 100 further comprises forming shallow trench isolation in the substrate in advance of forming the first oxide layer on the substrate. According to some embodiments, the method 100 of manufacturing further comprises pre-implanting a memory cell well (memory cell well) in the substrate prior to forming the first oxide layer on the substrate.

According to some embodiments, the process of forming the shallow trench isolation may include, but is not limited to, forming a liner oxide, depositing silicon nitride, active area exposure, shallow trench etching, shallow trench filling, shallow trench planarization, and removing silicon nitride.

According to some embodiments, step S101 includes forming a first oxide layer over a substrate, forming a memory layer over the first oxide layer, forming a second oxide layer over the memory layer, forming a control gate layer over the second oxide layer, and forming a hard mask layer over the control gate layer.

According to some embodiments, the material of the memory layer may be silicon nitride (SiN), or a high-K material such as HfO ₂、HfSiON、Ta₂O₅、Al₂O₃、TiO₂、ZrO₂ or the like.

According to some embodiments, an ONO (oxygen-nitrogen-oxygen) material is grown on an upper surface of a substrate to form a first oxide layer, a storage layer, and a second oxide, a control gate polysilicon is deposited on the upper surface of the ONO (oxygen-nitrogen-oxygen) material to form a control gate layer, and a hard mask material (e.g., a silicon nitride material) is deposited on the control gate layer to form a hard mask layer.

Fig. 2A shows a cross-sectional view of an exemplary structure formed after step S101. As shown in fig. 2A, semiconductor structure 200 includes, in order from bottom to top, a substrate 210, a first oxide layer 220, a memory layer 230, a second oxide layer 240, a control gate layer 250, and a hard mask layer 260.

At step S102, the hard mask layer, the control gate layer, the second oxide layer, the memory layer, and the first oxide layer are etched to form a gate stack composed of the hard mask layer, the control gate layer, the second oxide layer, the memory layer, and the remaining portion of the first oxide layer.

According to some embodiments, first, a photolithography process is performed on an upper surface of a hard mask layer to form a photoresist pattern, and then, the hard mask layer, the control gate layer, the second oxide layer, the memory layer, and the first oxide layer are etched using the formed photoresist pattern as a mask.

Fig. 2B shows a cross-sectional view of an exemplary structure formed after steps S101-S102. As shown in fig. 2B, the semiconductor structure 200 includes, in order from bottom to top, a substrate 210 and a gate stack 270, wherein the gate stack 270 includes, in order from bottom to top, a first oxide layer 220, a memory layer 230, a second oxide layer 240, a control gate layer 250, and a remaining portion of a hard mask layer 260.

At step S103, a first gate spacer and a second gate spacer are formed on both sides of the gate stack, respectively, and a first select gate oxide structure and a second select gate oxide structure are formed on a first region and a second region of the substrate, respectively, wherein the first region and the second region are located on both sides of the gate stack.

According to some embodiments, forming first and second gate spacers on both sides of a gate stack, respectively, and forming first and second select gate oxide structures on first and second regions of a substrate, respectively, includes forming control gate spacers on both sides of the gate stack, depositing a first gate oxide film on sides and an upper surface of the gate stack, and on the first and second regions of the substrate, removing portions of the first gate oxide film on the upper surface of the gate stack, and on the first and second regions of the substrate, to form first and second gate spacers, and forming first and second select gate oxide structures on the first and second regions of the substrate, respectively.

According to some embodiments, after etching the hard mask layer, the control gate layer, the second oxide layer, the memory layer, and the first oxide layer, a control gate spacer is formed on both sides of the hard mask layer, the control gate layer, the second oxide layer, the memory layer, and the remaining portion of the first oxide layer, for example, a control gate oxide (e.g., silicon oxide) is deposited on both sides of the hard mask layer, the control gate layer, the second oxide layer, the memory layer, and the remaining portion of the first oxide layer, and the deposited control gate oxide is etched to form the control gate spacer.

According to some embodiments, depositing the first gate oxide film on the side and upper surfaces of the gate stack and the first and second regions of the substrate includes depositing the first gate oxide film on the side and upper surfaces of the gate stack and the first, second and high voltage tube regions of the substrate.

According to some embodiments, a portion of the first gate oxide film on the sidewalls of the gate stack is preserved by etching (e.g., dry etching and wet etching) the first gate oxide film. According to some embodiments, after etching the first gate oxide film, a high temperature rapid thermal process is performed to enhance the quality of the oxide on the sidewalls.

In embodiments as described in this disclosure, a high voltage tube oxide structure having a different thickness than the select gate oxide structure is formed over the high voltage tube region by oxide film deposition and removal of excess oxide during deposition to facilitate subsequent formation of a corresponding high voltage logic device (e.g., 11V powered high voltage device) over the high voltage tube region.

According to some embodiments, the method of fabricating a semiconductor device as described in the present disclosure further includes performing a select gate channel ion (e.g., boron or BF 2) implantation in the first and second regions of the substrate prior to depositing the first gate oxide film on the sides and upper surface of the gate stack and the first and second regions of the substrate.

According to some embodiments, performing select gate channel ion implantation in a first region and a second region of a substrate includes performing select gate channel lithography to form a photoresist pattern to protect regions where ion implantation is not required, and performing select gate channel ion implantation with the formed photoresist pattern as a mask.

Fig. 2C shows a cross-sectional view of an exemplary structure formed after steps S101-S103. As shown in fig. 2C, the semiconductor structure 200 includes, in order from bottom to top, a substrate 210 and a gate stack 270, wherein the gate stack 270 includes, in order from bottom to top, a first oxide layer 220, a memory layer 230, a second oxide layer 240, a control gate layer 250, and a remaining portion of a hard mask layer 260. The semiconductor structure 200 further includes first and second gate spacers 271a and 271b formed on both sides of the gate stack 270, and first and second select gate oxide structures 222a and 222b formed on the first and second regions of the substrate 210, respectively.

It should be appreciated that while the first select gate oxide structure 222a and the first gate spacer 271a are shown as two separate portions and the second select gate oxide structure 222b and the second gate spacer 271b are shown as two separate portions, the first select gate oxide structure 222a and the first gate spacer 271a may actually be continuous but have different thickness oxides and the second select gate oxide structure 222b and the second gate spacer 271b may actually be continuous but have different thickness oxides, e.g., formed by the oxide film deposition step described above.

According to the embodiments described above, by leaving or additionally forming the oxide structure on the sides of the gate stack prior to depositing the first gate oxide film on the first and second regions of the substrate and on the sides and upper surface of the gate stack, the select gate oxide structure can be made to be different from the gate spacer structure thickness, e.g., thicker gate spacer structures facilitate data storage, thinner select gate oxide structures facilitate improved memory device performance (e.g., provide greater read current).

At step S104, a first select gate is formed on a side of the first gate spacer opposite the gate stack, and a second select gate is formed on a side of the second gate spacer opposite the gate stack.

According to some embodiments, a first select gate is formed on a side of a first gate spacer opposite a gate stack and a logic well implant is performed in a substrate before a second select gate is formed on a side of a second gate spacer opposite the gate stack, a logic IO gate oxide structure is formed on the substrate, and a logic core gate oxide structure is formed on the substrate.

According to some embodiments, forming the first and second select gate oxide structures on the first and second regions of the substrate, respectively, includes forming the first and second select gate oxide structures on the first and second regions of the substrate, respectively, concurrently with forming the logic IO gate oxide structure or the logic core gate oxide structure.

According to some embodiments, forming a first select gate on a side of the first gate spacer opposite the gate stack and forming a second select gate on a side of the second gate spacer opposite the gate stack includes depositing select gate polysilicon on the first and second select gate oxide structures and on the gate stack and removing portions of the deposited select gate polysilicon to form the first and second select gates.

According to some embodiments, the deposited select gate polysilicon has the same coverage at the surfaces of the first and second select gate oxide structures, and the gate stack, such that the deposited select gate polysilicon exhibits a "convex" shape. For example, as described in detail below with reference to fig. 3G.

According to some embodiments, removing portions of the deposited select gate polysilicon to form a first select gate and a second select gate includes planarizing the deposited select gate polysilicon, etching the planarized select gate polysilicon to form a first polysilicon structure and a second polysilicon structure on a first region and a second region of the substrate, respectively, and etching the first polysilicon structure and the second polysilicon structure to form the first select gate and the second select gate, respectively.

According to some embodiments, the deposited select gate polysilicon is planarized to remove the select gate polysilicon deposited over the gate stack. According to some embodiments, oxide deposited over the gate stack in a previous step may also be removed during the planarization process of the deposited select gate polysilicon.

According to some embodiments, etching the planarized select gate polysilicon to form first and second polysilicon structures on first and second regions of the substrate, respectively, includes etching shoulders of the "L" shaped select gate polysilicon on both sides of the gate stack to form rectangular shaped first and second polysilicon structures on the first and second regions of the substrate, respectively, for subsequent etching using photoresist or hard mask spacers as a mask to form the first and second select gates. For example, as described in detail below with reference to fig. 3H.

According to some embodiments, etching the first polysilicon structure and the second polysilicon structure to form the first select gate and the second select gate, respectively, includes performing a first photolithography process on the first polysilicon structure and the second polysilicon structure, etching the first polysilicon structure and the second polysilicon structure to form the first select gate and the second select gate, respectively, using a photoresist pattern formed by the first photolithography process as a mask, and removing the photoresist pattern formed by the first photolithography process. For example, as described in detail below with reference to fig. 3I-3J.

According to some embodiments, etching the first polysilicon structure and the second polysilicon structure to form the first select gate and the second select gate, respectively, includes forming a first hard mask spacer and a second hard mask spacer on both sides of the gate stack, respectively, the first hard mask spacer being located on the first polysilicon structure and the second hard mask spacer being located on the second polysilicon structure, and etching the first polysilicon structure and the second polysilicon structure with the first hard mask spacer and the second hard mask spacer as masks to form the first select gate and the second select gate, respectively. For example, as described in detail below with reference to fig. 4A-4B.

According to some embodiments, removing portions of the deposited select gate polysilicon to form the first select gate and the second select gate includes self-aligned etching the deposited select gate polysilicon to form the first select gate and the second select gate, respectively. For example, as described in detail below with reference to fig. 5.

According to some embodiments, the method of fabricating a semiconductor device as described in the present disclosure further includes depositing a logic gate polysilicon over a logic gate region of the substrate while depositing the select gate polysilicon over the first select gate oxide structure and the second select gate oxide structure, and over the gate stack, and removing portions of the logic gate polysilicon while removing portions of the deposited select gate polysilicon to form the first select gate and the second select gate to form the logic gate.

According to further embodiments, logic gate polysilicon is deposited over a logic gate region of the substrate while depositing the select gate polysilicon over the first and second select gate oxide structures and over the gate stack, and portions of the logic gate polysilicon are removed in a different processing step than portions of the deposited select gate polysilicon to form the logic gate.

Fig. 2D shows a cross-sectional view of an exemplary structure formed after steps S101-S104. As shown in fig. 2D, semiconductor structure 200 includes, in addition to substrate 210, gate stack 270, first select gate oxide structure 222a, first gate spacer 271a, second select gate oxide structure 222b, and second gate spacer 271b, a first select gate 280a formed on a side of first gate spacer 271a opposite gate stack 270, and a second select gate 280b formed on a side of second gate spacer 271b opposite gate stack 270.

At step S105, the gate stack is etched to form a first opening through the hard mask layer, the control gate layer, the second oxide layer, and the memory layer.

According to some embodiments, etching the gate stack to form a first opening through the hard mask layer, the control gate layer, the second oxide layer, and the remaining portion of the memory layer includes performing source photolithography to form a photoresist pattern, and etching the gate stack to form the first opening with the formed photoresist pattern as a mask.

Fig. 2E shows a cross-sectional view of an exemplary structure formed after steps S101-S105. As shown in fig. 2E, compared to fig. 2D, the first opening 272 passes through the hard mask layer, the control gate layer, the second oxide layer, and the remaining portion of the memory layer, wherein the hard mask layer, the control gate layer, the second oxide layer, and the remaining portion of the memory layer include gate structures of memory cells belonging to both sides, respectively, i.e., a gate structure composed of the first memory layer 230a, the second oxide structure 240a, the first control gate 250a, and the first hard mask 260a on the left side, and a gate structure composed of the second memory layer 230b, the second oxide structure 240b, the second control gate 250b, and the second hard mask 260b on the right side.

At step S106, a source region is formed in a portion of the substrate below the first opening.

According to some embodiments, the source region is formed by source ion implantation (e.g., arsenic and phosphorus) to form a graded junction in the substrate, i.e., the source ion doping concentration is gradually reduced in the direction from the first oxide layer to the substrate in the source region to improve the stressed capability of the semiconductor device. In embodiments described in this disclosure, since the gate structure and the oxide structure of the memory cell on both sides are formed first and then the source region implantation is performed, the performance of the source region is prevented from being affected by the thermal deposition step of forming the gate structure and the oxide structure.

Fig. 2F shows a cross-sectional view of an exemplary structure formed after steps S101-S106. As shown in fig. 2F, in contrast to fig. 2E, the semiconductor device 200 includes a source region 212 in the substrate 210 below the first opening 272.

At step S107, a first drain region is formed in the substrate on the side of the first select gate opposite the first opening, and a second drain region is formed in the substrate on the side of the second select gate opposite the first opening.

According to some embodiments, forming a first drain region in the substrate on a side of the first select gate opposite the first opening and forming a second drain region in the substrate on a side of the second select gate opposite the first opening includes performing a lightly doped drain implant in the substrate on a side of the first select gate opposite the first opening and in the substrate on a side of the second select gate opposite the first opening to form a first lightly doped drain region on a side of the first select gate and a second lightly doped drain region on a side of the second select gate, forming a first drain spacer on a side of the first select gate opposite the first opening and forming a second drain spacer on a side of the second select gate opposite the first opening, forming a first source spacer on a side of the first select gate opposite the first opening and forming a second source spacer on a side of the second select gate opposite the first opening, and forming a second drain spacer on a side of the first drain spacer opposite the first side of the first select gate opposite the first opening and in the first drain region opposite the second drain region.

Fig. 2G shows a cross-sectional view of an exemplary structure formed after steps S101-S107. As shown in fig. 2G, compared to fig. 2F, the semiconductor device 200 includes a first drain region 211a formed in the substrate 210 on the side of the first select gate 280a opposite the first opening 272 and a second drain region 211b formed in the substrate 210 on the side of the second select gate 280b opposite the first opening 272.

According to some embodiments, the method for manufacturing the semiconductor device further comprises forming silicide structures on the first select gate, the first drain region, the source region, the second select gate and the second drain region.

In conventional semiconductor device fabrication methods, a source region is formed between two adjacent memory cells and beneath the opening, and then a select gate is formed on one side of each memory cell, which deposits excess select gate material in the opening between the two adjacent memory cells when depositing the select gate material to form the select gate. In the method for manufacturing the semiconductor device according to the disclosure, since the select gates on both sides of the gate stack are formed first, and then the openings passing through the gate stack and the source regions located under the openings are formed, the unnecessary select gate material is not deposited in the openings as described above with reference to the conventional manufacturing method, so that the steps for removing the unnecessary select gate material are reduced, the manufacturing cost is reduced, and the deposition of conductive polysilicon in more trench regions and the removal of the deposited polysilicon using, for example, dry etching are avoided, the increased process risk during etching and the probability of defects generated on the wafer surface after etching are reduced, and the chip yield is improved.

In addition, in the existing manufacturing method of the semiconductor device, since the source region located under the opening between two adjacent memory cells is formed first and then deposited to form the remaining structure of the memory cell, the deposition process performed after the formation of the source region will affect the performance of the source region (e.g., further enlarge the source region), so that the process requirement for forming the source region is high (i.e., the desired performance can be maintained after the subsequent thermal treatment subjected to the subsequent multiple process steps (e.g., deposition). In the manufacturing method of the semiconductor device, as each deposition treatment is performed before the source region is formed, the formed source region is prevented from being influenced by the subsequent deposition treatment, and therefore the process requirement on the source region is reduced.

Fig. 3A-3M are schematic cross-sectional views of steps of a method of fabricating a semiconductor device 300 according to some embodiments of the present disclosure.

According to some embodiments, as shown in fig. 3A, semiconductor structure 300 includes, in order from bottom to top, a substrate 210, a first oxide layer 220, a memory layer 230, a second oxide layer 240, a control gate layer 250, and a hard mask layer 260, similar to that described with reference to fig. 2A.

According to some embodiments, as shown in fig. 3B, a photoresist is coated on an upper surface of the hard mask layer 260, a photolithography process is performed to form a photoresist pattern 290, and the hard mask layer 260, the control gate layer 250, the second oxide layer 240, the memory layer 230, and the first oxide layer 220 are etched with the photoresist pattern 290 as a mask, forming a gate stack including the first oxide layer 220, the memory layer 230, the second oxide layer 240, the control gate layer 250, and the hard mask layer 260.

According to some embodiments, as shown in fig. 3C, the photoresist pattern shown in fig. 3B is removed, first and second control gate spacers 273a and 273B are formed at both sides of the hard mask layer 260, the control gate layer 250, the second oxide layer 240, the memory layer 230, and the remaining portion of the first oxide layer 220, for example, control gate oxide is deposited, and the deposited control gate oxide is etched to form the control gate spacers.

According to some embodiments, performing the select gate channel ion implantation in the first and second regions of the substrate 210 includes performing select gate channel lithography to form a photoresist pattern, thereby protecting regions where ion implantation is not required, and performing the select gate channel ion implantation with the formed photoresist pattern as a mask, as shown in fig. 3D.

According to some embodiments, as shown in fig. 3E, a first gate oxide film 291 covering the semiconductor device 300 is formed on the first and second regions of the substrate 210, and the sides and upper surface of the gate stack.

According to some embodiments, although not shown in fig. 3E, a first gate oxide film 291 covering the semiconductor device 300 is formed on the first and second regions of the substrate 210, the side and upper surfaces of the gate stack, and the upper surface of the high-voltage tube region.

According to some embodiments, as shown in fig. 3F, portions of the first gate oxide film 291 located on the first and second regions and the upper surface of the gate stack are removed to obtain the first and second gate spacers 271a and 271b. It should be understood that although not shown, a portion of the first gate oxide film 291 on the high voltage tube region of the substrate 210 is reserved for subsequent formation of a corresponding oxide structure of the high voltage tube region.

Although not shown in fig. 3F, a logic well implant may be performed in substrate 210, logic IO gate oxide structures formed on substrate 210, and logic core gate oxide structures formed on substrate 210, according to some embodiments.

According to some embodiments, the entire thickness of the first gate oxide film 291 on the first and second regions of the first gate oxide film 291 is removed, thereby redepositing an oxide on the first and second regions of the substrate to form the first and second select gate oxide structures 222a and 222b of a preset thickness.

According to some embodiments, a first select gate oxide structure 222a and a second select gate oxide structure 222b may be formed on a first region and a second region of a substrate, respectively, at the same time as a logic IO gate oxide structure or a logic core gate oxide structure is formed.

According to some embodiments, as shown in fig. 3G, a select gate silicide 280 is deposited over the first select gate oxide structure 222a and the second select gate oxide structure 222b, and over the gate stack, wherein the select gate silicide 280 has substantially uniform coverage. Logic gate polysilicon for subsequent formation of logic gates may be deposited along with select gate silicide 280 in fig. 3G, according to some embodiments.

In accordance with some embodiments, as shown in fig. 3H, the semiconductor structure 300 is planarized and polysilicon etched to remove portions of the select gate silicide 280 to form a first polysilicon structure 281a located over the first region and a second polysilicon structure 281b located over the second region.

According to some embodiments, as shown in FIG. 3I, the first polysilicon structure 281a and the second polysilicon structure 281b are subjected to a photolithography process, and the first polysilicon structure 281a and the second polysilicon structure 281b are etched to form a first selection gate 280a and a second selection gate 280b, respectively, using a photoresist pattern 293 formed by the photolithography process as a mask. According to some embodiments, a logic gate may be formed along with the steps shown in fig. 3I.

According to some embodiments, as shown in fig. 3J, a photolithographic process (e.g., corresponding to photoresist patterns 294a and 294b as shown in fig. 3J) and a corresponding etch are performed to form first openings 272, and source ion implantation is performed in the portion of substrate 210 under first openings 272 to form source regions 212. According to some embodiments, the source ion implantation may be an N-type ion implantation. According to other embodiments, the source ion implantation may include an appropriately increased P-type ion implantation in addition to the N-type ion implantation to adjust the floating gate channel threshold voltage.

According to some embodiments, as shown in fig. 3K, lightly doped drain (lightly doped drain, LDD) implant lithography (e.g., corresponding to the photoresist pattern 295 shown in fig. 3K) is performed, and lightly doped drain implants (e.g., arsenic) are performed in the substrate 210 on the opposite side of the first select gate 280a from the first opening 272 and in the substrate 210 on the opposite side of the second select gate 280b from the first opening 272 to form a first lightly doped drain region 2111a on one side of the first select gate 280a and a second lightly doped drain region 2111b on one side of the second select gate 280 b. According to some embodiments, the associated process of forming the logic IO/core device may be performed after performing the lightly doped drain implant. According to some embodiments, the photoresist pattern 295 may be removed after performing the lightly doped drain implant.

According to some embodiments, as shown in fig. 3L, first, a first drain spacer 274a is formed on a side of the first select gate 280a opposite the first opening 272, and a second drain spacer 274b is formed on a side of the second select gate 280b opposite the first opening 272, a first source spacer 275a is formed on a side of the first select gate 280a facing the first opening 272, and a second source spacer 275b is formed on a side of the second select gate 280b facing the first opening 272, then, a heavily doped drain implant lithography (e.g., corresponding to the photoresist pattern 296 shown in fig. 3L) is performed, and a heavily doped drain implant is performed in the substrate 210 on a side of the first drain spacer 274a opposite the first opening 272 and in the substrate 210 on a side of the second drain spacer 274b opposite the first opening 272 to form a first heavily doped drain region 2112a on a side of the first drain spacer 274a and a second heavily doped drain region 2112b on a side of the second drain spacer 274 b. According to some embodiments, a baseline logic process (baseline logic process) may be performed after the heavily doped drain implant is performed.

According to some embodiments, a silicide structure is formed on the first select gate, the first drain region, the source region, the second select gate, and the second drain region. As shown in fig. 3M, silicide structures 223a-223e are formed on the first select gate 280a, the first heavily doped drain region 2112a, the source region 212, the second select gate 280b, and the second heavily doped drain region 2112 b. According to some embodiments, as shown in fig. 3M, the oxide layer 222 over the first and second heavily doped drain regions 2112a and 2112b and the portion of the oxide layer 220 over the source region 212 are removed, and silicide structures 223a and 223e are formed on the substrate 210 exposed by the removal of the oxide layer 222 and silicide structure 223c is formed on the substrate 210 exposed by the removal of the oxide layer 220.

Fig. 4A-4B are schematic cross-sectional views of steps of a method of fabricating a semiconductor device 400 according to some embodiments of the present disclosure.

According to some embodiments, after forming a first polysilicon structure 281a located on the first region and a second polysilicon structure 281b located on the second region as shown in fig. 3H, first hard mask spacers 282a and second hard mask spacers 282b are formed on both sides of the semiconductor device 200, respectively, as shown in fig. 4A, wherein the first hard mask spacers 282a are located on the first polysilicon structure 281a and the second hard mask spacers 282b are located on the second polysilicon structure 281b, for example, by depositing a hard mask material and etching the hard mask material to form the first hard mask spacers 282a and the second hard mask spacers 282b.

According to some embodiments, as shown in fig. 4B, first polysilicon structure 281a and second polysilicon structure 281B are etched with first hard mask spacers 282a and second hard mask spacers 282B as masks to form first select gate 280a and second select gate 280B, respectively.

After forming the semiconductor structure 400 as shown in fig. 4B, process steps as described above with reference to fig. 3J-3M may be performed to form a flash memory semiconductor device, according to some embodiments.

Fig. 5 is a schematic cross-sectional view of steps of a method of fabricating a semiconductor device according to some embodiments of the present disclosure.

After forming the first polysilicon structure 281a located on the first region and the second polysilicon structure 281b located on the second region as shown in fig. 3H, the deposited select gate polysilicon is self-aligned etched to form the first select gate 280a and the second select gate 280b, respectively, as shown in fig. 5, according to some embodiments.

According to some embodiments, after forming the semiconductor structure 500 as shown in fig. 5, process steps as described above with reference to fig. 3J-3M may be performed to form a flash memory semiconductor device.

Fig. 6 is a schematic cross-sectional view of steps of a method of fabricating a semiconductor device according to some embodiments of the present disclosure.

According to some embodiments, after forming a first gate oxide film 291 covering the semiconductor device 300 as shown in fig. 3E, as shown in fig. 6, performing a select gate channel ion implantation in the first and second regions of the substrate 210, including performing select gate channel lithography to form a photoresist pattern to protect regions where ion implantation is not required, performing the select gate channel ion implantation with the formed photoresist pattern as a mask, and then removing portions of the first gate oxide film 291 on the first and second regions and the upper surface of the gate stack to form gate oxide structures 271a and 271b on both sides of the gate stack. According to some embodiments, the portions of the first gate oxide film 291 on the sidewalls of the gate stack are preserved by etching (e.g., dry etching and wet etching) the first gate oxide film 291. According to other embodiments, instead of partially removing the first gate oxide film 291 on the sides of the gate stack, the first gate oxide film 291 on the sides of the gate stack is completely removed and then an oxide of a certain thickness is formed on the floating gate sidewalls by, for example, polysilicon oxidation.

According to some embodiments, after forming the semiconductor structure 600 as shown in fig. 6, the process steps as described above with reference to fig. 3F-3M may be performed to form a flash memory semiconductor device.

As an embodiment of the present disclosure, there is also provided a semiconductor device manufactured by the method of manufacturing a semiconductor device as described in the present disclosure.

Fig. 7 is a schematic cross-sectional structure of a semiconductor device 700 according to some embodiments of the present disclosure.

According to some embodiments, the semiconductor device 700 includes a substrate 210, gate stacks 270a and 270b formed over the substrate 210, a first select gate 280a, a second select gate 280b, a first drain region 211a, a second drain region 211b, and a source region 212 located within the substrate 210, wherein the first gate stack 270a includes a portion of the first oxide layer 220, the first storage layer 230a, the second oxide layer 240a, the first control gate 250a, and the first hard mask 260a, and the second gate stack 270b includes a portion of the first oxide layer 220, the second storage layer 230b, the second oxide layer 240b, the second control gate 250b, and the second hard mask 260b.

According to some embodiments, the semiconductor device 700 further includes a first gate spacer 271a between the first select gate 280a and the first gate stack 270a, a second gate spacer 271b between the second select gate 280b and the second gate stack 270b, a first select gate oxide structure 222a under the first select gate 280a, and a second select gate oxide structure 222b under the second select gate 280 b.

According to some embodiments, the semiconductor device 700 includes two memory cells sharing the source region 212. According to some embodiments, the semiconductor device 700 includes a first program channel 213a, a second program channel 213b, a first erase channel 214a corresponding to memory cells on the left side, and a second program channel 213c, a second program channel 213d, a second erase channel 214b corresponding to memory cells on the right side. According to some embodiments, the first program channel 213a extends from the first drain region 211a to an edge portion of the first storage layer 230a facing the first select gate 280a, the second program channel 213b extends from the first drain region 211a to the source region 212, the first erase channel 214a extends from the source region 212 to the first storage layer 230a, the third program channel 213b extends from the second drain region 211b to an edge portion of the second storage layer 230b facing the second select gate 280b, the fourth program channel 213b extends from the second drain region 211b to the source region 212, and the second erase channel 214b extends from the source region 212 to the second storage layer 230b. Wherein the process of performing a program operation, an erase operation, and a read operation on the left memory cell and the right memory cell is similar. The program operation, the erase operation, and the read operation will be described below with reference to the memory cell on the left side.

According to some embodiments, when performing a programming operation, a positive voltage (e.g., 0.9-1.6 v) higher than the threshold voltage is applied to the first select gate 280a, and a positive voltage (e.g., 4.5-7 v) is applied to the source (i.e., the source region 212) to provide a strong lateral electric field, and a negative current (e.g., 1 μa) is injected into the first drain region 211a, at this time, a portion of hot electrons are injected into the first memory layer 230a through the first programming channel 213a due to the electron source injection effect, and a portion of hot electrons migrate to the source through the second programming channel 213 b.

According to some embodiments, when an erase operation is performed, a higher negative voltage (e.g., -5V to 10V) is applied to the first control gate 250a, a higher positive voltage (e.g., -5V to 10V) is applied to the source region 212 to form a voltage difference between the first control gate 250a and the source region 212 and the first memory layer 230a, and the first drain region 211a is set to 0V or floating, at which point holes are injected into the first memory layer 230a due to BTBT (Band to Band Tunneling) effect.

According to some embodiments, when a read operation is performed, a positive voltage (e.g., 1.8V) is applied to the first select gate 280a, a positive voltage (e.g., 0-1.8V) is applied to the first control gate 250a, a lower positive voltage (e.g., 0.6V) is applied to the first drain region 211a, and the source region 212 is set to 0V, at this time, the state of the memory cell is determined by the magnitude of the current value between the source and drain terminals.

Fig. 8 is a circuit schematic diagram of a memory cell array 800 according to some embodiments of the present disclosure. It should be appreciated that the numbers of memory cells, word lines, bit lines, source lines, and erase lines in fig. 8 are merely illustrative, and that any of the above numbers may be adjusted to achieve larger or smaller scale arrays of memory cells depending on the actual application requirements.

As shown in fig. 8, the memory cell array 800 includes a plurality of memory cells (e.g., memory cell 810 shown in fig. 8). According to some embodiments, each memory cell includes a select transistor and a storage transistor connected in series, for example, memory cell 810 in fig. 8 includes a select transistor 811 and a storage transistor 812, wherein a fixed address memory cell may be selected for operation by select transistor 811 and storage transistor 812 may store information.

According to some embodiments, the memory cells of each row correspond to one word line, e.g., in fig. 8, the memory cells of the upper row correspond to word line WLn-1, the memory cells of the lower row correspond to word line WLn, and each word line is connected to the gate of a select transistor in the corresponding memory cell. According to some embodiments, the memory cells of each column correspond to one bit line, e.g., in fig. 8, the memory cells of the left column correspond to bit line BLn-1, the memory cells of the middle column correspond to bit line BLn, the memory cells of the right column correspond to bit line bln+1, and each bit line is connected to the drain of a select transistor in the corresponding memory cell. According to some embodiments, memory cells of two adjacent rows correspond to one source line, for example, in fig. 8, memory cells of two upper and lower rows each correspond to a source line SL, and each source line is connected to a source of a storage transistor in the corresponding memory cell. According to some embodiments, the source lines of all memory cells in each sector in the memory are electrically connected together. According to some embodiments, in the memory cell array 800, each row of memory cells corresponds to one control line, e.g., in fig. 8, the upper row of memory cells corresponds to control line CGn-1, the lower row of memory cells corresponds to control line CGn, and each control line is connected to the control gate of a storage transistor in the corresponding memory cell;

According to some embodiments, the drain of the select transistor in the memory cell corresponds to, for example, the first drain region 211a in the semiconductor device 700 shown in fig. 7, the gate of the select transistor in the memory cell corresponds to, for example, the first select gate 280a in the semiconductor device 700 shown in fig. 7, the storage layer of the store transistor in the memory cell corresponds to the first storage layer 230a in the semiconductor device 700 shown in fig. 7, the control gate of the store transistor in the memory cell corresponds to the first control gate 230a in the semiconductor device 700 shown in fig. 7, and the source of the store transistor in the memory cell corresponds to the source region 212 in the semiconductor device 700 shown in fig. 7.

Fig. 9A-9B are top plan views of memory cell arrays according to some embodiments of the present disclosure. As shown in fig. 9A, the memory cell array 900 includes a plurality of bit lines BLn-1, BLn, and bln+1, a plurality of word lines WLn-1 and WLn, and a source line SL.

According to some embodiments, the memory cells of each column correspond to the same bit line, e.g., as shown in FIG. 9A, both memory cells of the left column correspond to bit line BLn-1. It should be appreciated that although not shown, the bit line structures of memory cells of the same column are electrically connected.

According to some embodiments, the memory cells of each row correspond to the same word line, e.g., as shown in FIG. 9A, the three memory cells of the upper row each correspond to word line WLn 1. According to some embodiments, as shown in fig. 9A, each word line extends through multiple memory cells in the same row.

According to some embodiments, the memory cells of each row correspond to one control line, e.g., in fig. 9A, the memory cells of the upper row correspond to control line CGn-1, the memory cells of the lower row correspond to control line CGn, and each control line is connected to a memory layer in the corresponding memory cell.

According to some embodiments, memory cells of adjacent rows correspond to the same source line, e.g., as shown in fig. 9A, six memory cells in both upper and lower rows correspond to source line SL. According to some embodiments, as shown in fig. 9A, a source line SL extends in the substrate through adjacent rows of memory cells, wherein the source line communicates with source regions in a plurality of bit lines.

The memory cell array 900 shown in fig. 9B differs from the memory cell array 900 shown in fig. 9A in that instead of the source lines SL extending through the plurality of bit lines in the substrate, corresponding tungsten plugs (e.g., corresponding tungsten plugs Wn-1 of bit lines BLn-1) are provided on each bit line, and the respective tungsten plugs are connected by metal lines to communicate with the source regions in the plurality of bit lines.

The present disclosure provides a method of manufacturing a semiconductor device including sequentially forming a first oxide layer, a select gate layer, and a hard mask layer on a substrate, etching the hard mask layer and the select gate layer to form a gate stack composed of the hard mask layer and a remaining portion of the select gate layer, forming a first storage structure on a first side of the gate stack and a first gate region, and forming a second storage structure on a second side of the gate stack and a second gate region, wherein the first gate region is located on one side of the first side of the gate stack, the second gate region is located on one side of the second side of the gate stack, forming a first control gate on the first storage structure, and forming a second control gate on the second storage structure, etching the gate stack to form a first opening through the hard mask layer and the select gate layer, forming a drain region in a portion of the substrate located below the first opening, and forming a first storage region in the substrate on a side of the first control gate opposite the first opening, and forming a source region in the substrate on a side of the second control gate opposite the first opening.

Fig. 10 is a schematic flow chart diagram of a method 1000 of fabricating a semiconductor device according to some embodiments of the present disclosure.

At step S1001, a first oxide layer, a select gate layer, and a hard mask layer are sequentially formed on a substrate.

According to some embodiments, the method 1000 of fabricating further comprises forming shallow trench isolation in the substrate in advance of forming the first oxide layer on the substrate. According to some embodiments, the method 1000 of fabricating further includes pre-implanting a memory cell well (memory cell well) in the substrate prior to forming the first oxide layer on the substrate.

According to some embodiments, step S1001 includes forming a first oxide layer over a substrate, forming a select gate layer over the first oxide layer, and forming a hard mask layer over the select gate layer.

Fig. 11A shows a cross-sectional view of an exemplary structure formed after step S1001. As shown in fig. 11A, semiconductor structure 200 includes, in order from bottom to top, a substrate 1110, a first oxide layer 1120, a select gate layer 1130, and a hard mask layer 1140.

At step S1002, the hard mask layer and the select gate layer are etched to form a gate stack composed of the hard mask layer and the remaining portion of the select gate layer.

According to some embodiments, first, a photolithography process is performed on an upper surface of the hard mask layer to form a photoresist pattern, and then, the hard mask layer and the select gate layer are etched using the formed photoresist pattern as a mask.

Fig. 11B shows a cross-sectional view of an exemplary structure formed after steps S1001-S1002. As shown in fig. 11B, the semiconductor structure 1100 includes, in order from bottom to top, a substrate 1110, a first oxide layer 1120, and a gate stack 1170, wherein the gate stack 1170 selects, in order from bottom to top, the remaining portions of the gate layer 1130 and the hard mask layer 1140.

At step S1003, a first memory structure is formed on a first side of the gate stack and a first gate region, and a second memory structure is formed on a second side of the gate stack and a second gate region, wherein the first gate region is located on one side of the first side of the gate stack and the second gate region is located on one side of the second side of the gate stack.

According to some embodiments, forming a first memory structure on a first side of a gate stack and a first gate region, and forming a second memory structure on a second side of the gate stack and a second gate region, includes sequentially depositing a first memory oxide layer, a memory layer, and a second memory oxide layer on sides and an upper surface of the gate stack and on first and second regions of a substrate, wherein the first and second regions are located on both sides of the gate stack, the first region includes the first gate region, the second region includes the second gate region, removing portions of the first gate oxide layer on the upper surface of the gate stack and on the first and second regions of the substrate, sequentially depositing the first memory oxide layer, the memory layer, and the second memory oxide layer on sides and an upper surface of the gate stack and on non-gate regions and on an upper surface of the gate stack of the substrate, and removing portions of the first memory oxide layer, the memory layer, and the second memory oxide layer on the non-gate region and on the first region, and on the upper surface of the gate stack, wherein the first region and the second region include the non-gate structure is not included in the first region.

According to some embodiments, after etching the hard mask layer and the select gate layer, select gate spacers are formed on both sides of the hard mask layer and the remaining portion of the select gate layer, e.g., a select gate oxide (e.g., silicon oxide) is deposited on both sides of the hard mask layer and the remaining portion of the select gate layer, and the deposited select gate oxide is etched to form the select gate spacers.

According to some embodiments, a memory channel ion (e.g., boron or BF 2) implantation is performed in the first and second regions of the substrate prior to depositing the first gate oxide film on the sides and upper surface of the gate stack and the first and second regions of the substrate.

According to some embodiments, sequentially depositing a first memory oxide layer, a memory layer, and a second memory oxide layer on the sides and upper surface of the gate stack and the first and second regions of the substrate includes depositing an ONO (oxygen-nitrogen-oxygen) material on the sides and upper surface of the gate stack and the first and second regions of the substrate. Portions of the ONO (oxygen-nitrogen-oxygen) material are removed over the non-gate regions of the substrate and over the upper surface of the gate stack to form a first memory structure and a second memory structure.

According to some embodiments, performing memory channel ion implantation in a first region and a second region of a substrate includes performing memory channel lithography to form a photoresist pattern to protect a region where ion implantation is not required, and performing memory channel ion implantation with the formed photoresist pattern as a mask.

According to some embodiments, the memory channel ion implantation is performed in the first region and the second region of the substrate, tilted by a preset angle to adjust the channel of the select gate.

Fig. 11C shows a cross-sectional view of an exemplary structure formed after steps S1001-S1003. As shown in fig. 11C, the semiconductor structure 1100 includes, in order from bottom to top, a substrate 1110, a first oxide layer 1120, and a gate stack 1170, wherein the gate stack 1170 includes, in order from bottom to top, a control gate layer 1130 and a remaining portion of a hard mask layer 1140. The semiconductor structure 1100 further includes a first memory structure 1122a formed on a first side of the gate stack 1170 and the first gate region 1113a, and a second memory structure 1122b formed on a second side of the gate stack 1170 and the second gate region 1113 b.

At step S1004, a first control gate is formed on the first storage structure, and a second control gate is formed on the second storage structure.

According to some embodiments, forming a first control gate over the first memory structure and forming a second control gate over the second memory structure includes depositing a control gate polysilicon over the second memory oxide layer after sequentially depositing a first memory oxide layer, a memory layer, and a second memory oxide layer over the sides and upper surfaces of the gate stack and the first region and the second region of the substrate, and removing portions of the deposited control gate polysilicon to form the first control gate and the second control gate while removing portions of the first memory oxide layer, the memory layer, and the second memory oxide layer over the non-gate region of the substrate and over the upper surface of the gate stack.

According to some embodiments, the deposited first, second, and control gate polysilicon have the same coverage such that the deposited first, second, and control gate polysilicon exhibit a "convex" shape. For example, as described in detail below with reference to fig. 12H.

According to some embodiments, removing portions of the deposited control gate polysilicon to form a first control gate and a second control gate includes planarizing the deposited control gate polysilicon, etching the planarized control gate polysilicon to form a first polysilicon structure and a second polysilicon structure on a first region and a second region of the substrate, respectively, and etching the first polysilicon structure and the second polysilicon structure to form the first control gate and the second control gate, respectively.

According to some embodiments, the deposited control gate polysilicon is planarized to remove the control gate polysilicon deposited over the gate stack. According to some embodiments, the first memory oxide layer, the memory layer, and the second memory oxide layer deposited over the gate stack in the previous step may also be removed during the planarization process of the deposited control gate polysilicon.

According to some embodiments, etching the planarized control gate polysilicon to form first and second polysilicon structures on first and second regions of the substrate, respectively, includes etching shoulders of the "L" shaped select gate polysilicon on both sides of the gate stack to form rectangular shaped first and second polysilicon structures on the first and second regions of the substrate, respectively, for subsequent etching using photoresist or hard mask spacers as a mask to form the first and second control gates. For example, as described in detail below with reference to fig. 12I.

According to some embodiments, etching the first polysilicon structure and the second polysilicon structure to form the first control gate and the second control gate, respectively, includes performing a first photolithography process on the first polysilicon structure and the second polysilicon structure, etching the first polysilicon structure and the second polysilicon structure to form the first control gate and the second control gate, respectively, using a photoresist pattern formed by the first photolithography process as a mask, and removing the photoresist pattern formed by the first photolithography process. For example, as described in detail below with reference to fig. 12I-12J.

According to some embodiments, a first control gate is formed over a first memory structure and a logic well implant is performed in a substrate before a second control gate is formed over a second memory structure, a logic IO gate oxide structure is formed over the substrate, and a logic core gate oxide structure is formed over the substrate.

According to some embodiments, etching the first and second polysilicon structures to form the first and second control gates, respectively, includes forming first and second hard mask spacers on both sides of the gate stack, respectively, the first hard mask spacer being located on the first polysilicon structure and the second hard mask spacer being located on the second polysilicon structure, and etching the first and second polysilicon structures to form the first and second control gates, respectively, with the first and second hard mask spacers as masks. For example, as described in detail below with reference to fig. 13A-13B.

Removing portions of the deposited control gate polysilicon to form the first control gate and the second control gate, according to some embodiments, includes self-aligned etching the deposited control gate polysilicon to form the first control gate and the second control gate, respectively. For example, as described in detail below with reference to fig. 14.

According to some embodiments, the method of fabricating a semiconductor device as described in the present disclosure further includes depositing a logic gate polysilicon on a logic gate region of the substrate while depositing the control gate polysilicon on the second memory oxide layer, and removing portions of the logic gate polysilicon while removing portions of the deposited control gate polysilicon to form the first control gate and the second control gate to form the logic gate.

According to further embodiments, logic gate polysilicon is deposited on the logic gate region of the substrate while control gate polysilicon is deposited on the second memory oxide layer, and portions of the logic gate polysilicon are removed in a different processing step than portions of the deposited control gate polysilicon to form the logic gate.

Fig. 11D shows a cross-sectional view of an exemplary structure formed after steps S1001-S1004. As shown in fig. 11D, the semiconductor structure 1100 includes a first control gate 1180a formed on the first memory structure 1122a, and a second control gate 1180b formed on the second memory structure 1122b, in addition to the substrate 1110, the first oxide layer 1120, and the gate stack 1170, and the first memory structure 1122a formed on the first side of the gate stack 1170 and the first gate region 1113a, and the second memory structure 1122b formed on the second side of the gate stack 1170 and the second gate region 1113 b.

At step S1005, the gate stack is etched to form a first opening through the hard mask layer and the select gate layer.

According to some embodiments, etching the gate stack to form a first opening through the hard mask layer and the remaining portion of the select gate layer includes performing drain lithography to form a photoresist pattern, and etching the gate stack to form the first opening with the formed photoresist pattern as a mask.

Fig. 11E shows a cross-sectional view of an exemplary structure formed after steps S1001-S1005. As shown in fig. 11E, compared to fig. 11D, the first opening 1172 passes through the hard mask layer and the remaining portion of the select gate layer, wherein the hard mask layer and the remaining portion of the select gate layer include gate structures of memory cells belonging to both sides, respectively, i.e., a gate structure consisting of the first select gate 1130a and the first hard mask 1140a on the left side and a gate structure consisting of the second select gate 1130b and the second hard mask 1140b on the right side.

At step S1006, a drain region is formed in a portion of the substrate below the first opening.

According to some embodiments, forming a drain region in a portion of the substrate below the first opening includes performing a lightly doped drain implant in the substrate below the first opening to form a lightly doped drain region in the substrate below the first opening, forming a first drain spacer and a second drain spacer on sides of the gate stack in the first opening, and performing a heavily doped source implant in the substrate below the first opening between the first drain spacer and the second drain spacer to form a heavily doped drain region between the first drain spacer and the second drain spacer.

Fig. 11F shows a cross-sectional view of an exemplary structure formed after steps S1001-S1006. As shown in fig. 11F, in comparison to fig. 11E, the semiconductor device 1100 includes a drain region 1112 in the substrate 1110 below the first opening 1172.

At step S107, a first source region is formed in the substrate on the side of the first control gate opposite the first opening, and a second source region is formed in the substrate on the side of the second control gate opposite the first opening.

Fig. 11G shows a cross-sectional view of an exemplary structure formed after steps S1001-S1007. As shown in fig. 11G, compared to fig. 11F, the semiconductor device 1100 includes a first source region 1111a formed in the substrate 1110 on the side opposite to the first opening 1172 of the first control gate 1180a and a second source region 1111b formed in the substrate 1110 on the side opposite to the first opening 1172 of the second control gate 1180 b.

According to some embodiments, the method for manufacturing the semiconductor device further comprises forming silicide structures on the first control gate, the first source region, the drain region, the second control gate and the second source region.

In conventional semiconductor device fabrication methods, a source region is formed between two adjacent memory cells and beneath the opening, and then a control gate is formed on one side of each memory cell, which deposits excess control gate material in the opening between the two adjacent memory cells when the control gate material is deposited to form the control gate. In the method for manufacturing the semiconductor device according to the disclosure, since the control gates on both sides of the gate stack are formed first and then the source regions under both sides of the gate stack are formed, the redundant control gate material is not deposited in the openings as described above with reference to the conventional manufacturing method, so that the steps for removing the redundant control gate material are reduced, the production cost is reduced, and the steps for depositing conductive polysilicon in more trench regions and removing the deposited polysilicon by using, for example, dry etching are avoided, the increased process risk during etching and the probability of defects on the wafer surface after etching are reduced, and the chip yield is improved.

Fig. 12A-12N are schematic cross-sectional views of steps of a method of fabricating a semiconductor device 1200 according to some embodiments of the present disclosure.

According to some embodiments, as shown in fig. 12A, a semiconductor structure 1200 includes, in order from bottom to top, a substrate 1110, a first oxide layer 1120, a select gate layer 1130, and a hard mask layer 1140, similar to that described with reference to fig. 11A.

According to some embodiments, as shown in fig. 12B, a photoresist is coated on an upper surface of the hard mask layer 1140, a photolithography process is performed to form a photoresist pattern 1150, and the hard mask layer 1140 and the selection gate layer 1130 are etched with the photoresist pattern 1150 as a mask, forming a gate stack including the hard mask layer 1140 and the selection gate layer 1130.

According to some embodiments, as shown in fig. 12C, the photoresist pattern shown in fig. 12B is removed, first select gate spacers 1173a and second select gate spacers 1173B are formed on both sides of the remaining portions of the hard mask layer 1140 and select gate layer 1130, e.g., a select gate oxide is deposited, and the deposited select gate oxide is etched to form the select gate spacers.

According to some embodiments, performing memory channel ion implantation in the first and second regions of the substrate 1110 includes performing memory channel lithography to form a photoresist pattern, thereby protecting regions where ion implantation is not required, and performing memory channel ion implantation with the formed photoresist pattern as a mask, as shown in fig. 12D.

According to some embodiments, as shown in fig. 12E, a first gate oxide film 1191 is deposited on the sides and upper surface of the gate stack, and the first and second regions of the substrate.

According to some embodiments, although not shown in fig. 12E, a first gate oxide film 1191 covering the semiconductor device 1200 is formed on the first and second regions of the substrate 1110, the side and upper surfaces of the gate stack, and the upper surface of the high voltage tube region.

According to some embodiments, as shown in fig. 12F, portions of the first gate oxide film 291 located on the first and second regions and the upper surface of the gate stack are removed to obtain the first and second gate spacers 1171a and 1171b. It should be appreciated that although not shown, a portion of the first gate oxide film 1191 on the high voltage tube region of the substrate 1110 is reserved for subsequent formation of a corresponding oxide structure of the high voltage tube region.

According to some embodiments, as shown in fig. 12G, a first memory oxide layer 1161, a memory layer 1162, and a second memory oxide layer 1163 are sequentially deposited on the sides and upper surface of the gate stack, and the first and second regions of the substrate.

Although not shown in fig. 12G, logic well implants may be performed in substrate 1110, logic IO gate oxide structures formed on substrate 1110, and logic core gate oxide structures formed on substrate 1110, according to some embodiments.

According to some embodiments, as shown in fig. 12H, a control gate silicide 1180 is formed on the upper surface of the second memory oxide layer 1163. The control gate silicide 1180 has a substantially uniform coverage. Logic gate polysilicon for subsequent formation of the logic gate may be deposited along with control gate silicide 1180 in fig. 12H, according to some embodiments.

According to some embodiments, as shown in fig. 12I, the semiconductor structure 1200 is planarized and polysilicon etched to remove portions of the control gate silicide 1180 to form a first polysilicon structure 1181a located on the first region and a second polysilicon structure 1181b located on the second region, and to remove portions of the first memory oxide layer 1161, the memory layer 1162, and the second memory oxide layer 1163 located on the hard mask layer 1140.

According to some embodiments, as shown in fig. 12J, the first and second polysilicon structures 1181a and 1181b are subjected to a photolithography process, and the first and second polysilicon structures 1181a and 1181b are etched using the photoresist pattern 1193 formed by the photolithography process as a mask to form a first and second control gate 1180a and 1180b, respectively. According to some embodiments, the first memory oxide layer 1161, the memory layer 1162, and the second memory oxide layer 1163 are etched using the photoresist pattern 1193 formed by the photolithography process as a mask to form the first memory structure 1122a and the second memory structure 1122b. According to some embodiments, a logic gate may be formed along with the steps shown in fig. 12J.

According to some embodiments, as shown in fig. 12K, lightly doped drain (lightly doped drain, LDD) implant lithography (e.g., corresponding to photoresist patterns 1194a and 1194b shown in fig. 12K) is performed, and lightly doped drain implant (e.g., arsenic) is performed in the substrate 1110 under the first opening 1172 to form lightly doped drain region 1112. According to some embodiments, the associated process of forming the logic IO/core device may be performed after performing the lightly doped drain implant. According to some embodiments, after performing the lightly doped drain implant, the photoresist patterns 1194a and 1194b may be removed.

According to some embodiments, the P-type drain ion implantation is performed in the substrate region, tilted by a predetermined angle to adjust the channel of the select gate.

According to some embodiments, as shown in fig. 12L, a photolithography process of a source region (for example, corresponding to the photoresist pattern 1195 as shown in fig. 12L) is performed, and source ion implantation is performed in the substrate 1110 of the first control gate 1180a on the side opposite to the first opening 1172 and in the substrate 1110 of the second control gate 1180b on the side opposite to the first opening 1172, to form a first source region 1211a on the side of the first control gate 1180a and a second source region 1211b on the side of the second control gate 1180 b. According to some embodiments, the source ion implantation may be an N-type ion implantation. According to other embodiments, the source ion implantation may include an appropriately increased P-type ion implantation in addition to the N-type ion implantation to adjust the floating gate channel threshold voltage.

According to some embodiments, as shown in fig. 12M, first, a first source spacer 1174a is formed on a side of a first control gate 1180a opposite to a first opening 1172, and a second source spacer 1174b is formed on a side of a second control gate 1180b opposite to the first opening 1172, a first drain spacer 1175a is formed on a side of the first control gate 1180a facing the first opening 1172, and a second drain spacer 1175b is formed on a side of the second control gate 1180b facing the first opening 1172, then, a heavily doped drain implant lithography (e.g., corresponding to photoresist patterns 1196a and 1196b shown in fig. 12M) is performed, and a heavily doped source implant is performed in the substrate 1110 between the first drain spacer 1175a and the second drain spacer 1175b to form a heavily doped drain region 1113 between the first drain spacer 1175a and the second drain spacer 1175 b. According to some embodiments, a baseline logic process (baseline logic process) may be performed after the heavily doped drain implant is performed.

According to some embodiments, a silicide structure is formed on the first control gate, the first source region, the drain region, the second control gate, and the second source region. As shown in fig. 12N, silicide structures 1123a-1123e are formed on the first control gate 1180a, the first source region 1211a, the heavily doped drain region 1113, the second control gate 1180b, and the second source region 1211 b.

Fig. 13A-13B are schematic cross-sectional views of steps of a method of fabricating a semiconductor device 1300 according to some embodiments of the present disclosure.

After forming the first polysilicon structure 1181a located on the first region and the second polysilicon structure 1181b located on the second region as shown in fig. 12I, first and second hard mask spacers 1182a and 1182b are formed on both sides of the semiconductor device 1300, respectively, as shown in fig. 13A, wherein the first hard mask spacer 1182a is located on the first polysilicon structure 1181a and the second hard mask spacer 1182b is located on the second polysilicon structure 1181b, for example, by depositing a hard mask material and etching the hard mask material to form the first and second hard mask spacers 1182a and 1182b.

According to some embodiments, as shown in fig. 13B, the first and second polysilicon structures 1181a and 1181B are etched with the first and second hard mask spacers 1182a and 1182B as masks to form first and second control gates 1180a and 1180B, respectively.

After forming the semiconductor structure 1300 shown in fig. 13B, process steps as described above with reference to fig. 12K-12N may be performed to form a flash memory semiconductor device, according to some embodiments.

Fig. 14 is a schematic cross-sectional view of steps of a method of fabricating a semiconductor device according to some embodiments of the present disclosure.

After forming the first polysilicon structure 1181a located on the first region and the second polysilicon structure 1181b located on the second region as shown in fig. 12I, the deposited select gate polysilicon is self-aligned etched to form a first control gate 1180a and a second control gate 1180b, respectively, as shown in fig. 14, in accordance with some embodiments.

According to some embodiments, after forming the semiconductor structure 1400 as shown in fig. 14, process steps as described above with reference to fig. 12K-12N may be performed to form a flash memory semiconductor device.

Fig. 15 is a schematic cross-sectional view of steps of a method of fabricating a semiconductor device according to some embodiments of the present disclosure.

According to some embodiments, after forming a first gate oxide film 1191 covering the semiconductor device 1100 as shown in fig. 12E, memory channel ion implantation is performed in the first and second regions of the substrate 1110, including performing memory channel lithography to form a photoresist pattern to protect regions where ion implantation is not required, performing memory channel ion implantation with the formed photoresist pattern as a mask, then removing portions of the first gate oxide film 1191 on the upper surfaces of the first and second regions and the gate stack, and removing a portion of the first gate oxide film 291 on the sides of the gate stack to form gate oxide structures 1171a and 1171b on both sides of the gate spacer, as shown in fig. 15. According to some embodiments, a portion of the first gate oxide film 1191 on the sidewalls of the gate stack is preserved by etching (e.g., dry etching and wet etching) the first gate oxide film 1191. According to other embodiments, instead of partially removing the first gate oxide film 1191 on the sides of the gate stack, the first gate oxide film 1191 on the sides of the gate stack is completely removed and then oxide of a certain thickness is formed on the floating gate sidewalls by, for example, polysilicon oxidation.

According to some embodiments, after forming the semiconductor structure 1500 shown in fig. 15, the process steps described above with reference to fig. 12G-12N may be performed to form a flash memory semiconductor device.

Fig. 16 is a schematic cross-sectional structure of a semiconductor device 1600 according to some embodiments of the present disclosure.

According to some embodiments, the semiconductor device 1600 includes a substrate 1110, first oxide layers 1120a and 1120b formed over the substrate 1110, a first select gate 1130a, a first hard mask layer 1140a, a second select gate 1130b, a second hard mask layer 1140b, a first memory structure 1122a, a second memory structure 1122b, a first control gate 1180a, a second control gate 1180b, a first drain region 1211a, a second drain region 1211b, and a source region 1112 located within the substrate 1110.

According to some embodiments, the first memory structure 1122a includes a first memory oxide layer 1161a, a memory layer 1162a on the first memory oxide layer 1161a, and a second memory oxide layer 1163a on the memory layer 1162 a. The second memory structure 1122b includes a first memory oxide layer 1161b, a memory layer 1162b on the first memory oxide layer 1161b, and a second memory oxide layer 1163b on the memory layer 1162 b.

According to some embodiments, semiconductor device 1600 includes two memory cells sharing drain region 1112. According to some embodiments, semiconductor device 1600 includes a first programming channel 1113a, a second programming channel 1113b, a first erase channel 1114a corresponding to a memory cell on the left side, and a second programming channel 1113c, a second programming channel 1113d, a second erase channel 1114b corresponding to a memory cell on the right side. According to some embodiments, a first programming channel 1113a extends from the drain region 1112 to an edge region of the storage layer 1162a facing the first storage oxide layer 1161a, a second programming channel 1113b extends from the source region 1112 to the first source region 1211a, a first erase channel 1114a extends from the first source region 1211a to the storage layer 1162a, a third programming channel 1113c extends from the drain region 1112 to an edge region of the storage layer 1162b facing the first storage oxide layer 1161b, a fourth programming channel 1113d extends from the drain region 1112 to the second source region 1211b, and a second erase channel 1114b extends from the second source region 1211b to the storage layer 1162b. Wherein the process of performing a program operation, an erase operation, and a read operation on the left memory cell and the right memory cell is similar. The program operation, the erase operation, and the read operation will be described below with reference to the memory cell on the left side.

According to some embodiments, when performing a programming operation, a positive voltage (e.g., 0.9-1.6 v) higher than the threshold voltage is applied to the first select gate 1130a, and a positive voltage (e.g., 4.5-7 v) is applied to the first source region 1211a to provide a strong lateral electric field, and a negative current (e.g., 1 μa) is injected into the drain region 1112, at which time, due to the electron source injection effect, a portion of hot electrons are injected into the memory layer 1162a through the first programming channel 1113a, and a portion of hot electrons migrate to the first source region 1211a through the second programming channel 1113 b.

According to some embodiments, when an erase operation is performed, a higher negative voltage (e.g., -5V to 10V) is applied to the first control gate 1180a, a higher positive voltage (e.g., -5V to 10V) is applied to the first source region 1211a to form a voltage difference between the first control gate 1180a and the first source region 1211a, and the drain region 1112 is set to 0V or floating, at which point holes are injected into the first memory layer 1162a due to BTBT (Band to Band Tunneling) effect.

According to some embodiments, when a read operation is performed, the state of the memory cell is determined by applying a positive voltage (e.g., 1.8V) on the first control gate 1180a, a positive voltage (e.g., 1.8V) on the first select gate 1130a, a lower positive voltage (e.g., 0.6V) on the drain region 1112, and setting the first source region 1211a to 0V, at this time, by the magnitude of the current between the source and drain terminals.

Fig. 17 is a circuit schematic diagram of a memory cell array 1700 according to some embodiments of the present disclosure. It should be appreciated that the numbers of memory cells, word lines, bit lines, source lines, and erase lines in fig. 17 are merely illustrative, and that any of the above numbers may be adjusted to achieve larger or smaller scale arrays of memory cells depending on the actual application requirements.

As shown in fig. 17, the memory cell array 1700 includes a plurality of memory cells (e.g., memory cells 1710 shown in fig. 17). According to some embodiments, each memory cell includes a select transistor and a storage transistor connected in series, e.g., memory cell 1710 in fig. 17 includes a select transistor 1711 and a storage transistor 1712, where a fixed address memory cell may be selected for operation by select transistor 1711 and storage transistor 1712 may store information.

According to some embodiments, the memory cells of each row correspond to one word line, e.g., in fig. 17, the memory cells of the upper row correspond to word line WLn-1, the memory cells of the lower row correspond to word line WLn, and each word line is connected to the gate of a select transistor in the corresponding memory cell. According to some embodiments, the memory cells of each column correspond to one bit line, e.g., in fig. 17, the memory cells of the left column correspond to bit line BLn-1, the memory cells of the middle column correspond to bit line BLn, the memory cells of the right column correspond to bit line bln+1, and each bit line is connected to the drain of a select transistor in the corresponding memory cell. According to some embodiments, memory cells of two adjacent rows correspond to one source line, for example, in fig. 17, memory cells of two upper and lower rows each correspond to a source line SL, and each source line is connected to a source of a storage transistor in the corresponding memory cell. According to some embodiments, the source lines of all memory cells in each sector in the memory are electrically connected together. According to some embodiments, in the memory cell array 1700, each row of memory cells corresponds to one control line, e.g., in fig. 17, the upper row of memory cells corresponds to control line CGn-1, the lower row of memory cells corresponds to control line CGn, and each control line is connected to the control gate of a storage transistor in the corresponding memory cell;

According to some embodiments, the drain of the select transistor in the memory cell corresponds to the drain region 1112 in the semiconductor device 1600 shown in fig. 16, the gate of the select transistor in the memory cell corresponds to the first select gate 1130a in the semiconductor device 1600 shown in fig. 16, the storage layer of the store transistor in the memory cell corresponds to the storage layer 1162a in the semiconductor device 1600 shown in fig. 16, the control gate of the store transistor in the memory cell corresponds to the first control gate 1180a in the semiconductor device 1600 shown in fig. 16, and the source of the store transistor in the memory cell corresponds to the first source region 1211a in the semiconductor device 1600 shown in fig. 16.

18A-18B are top plan views of memory cell arrays according to some embodiments of the present disclosure. As shown in fig. 18A, the memory cell array 1800 includes a plurality of bit lines BLn-1, BLn, and bln+1, a plurality of word lines WLn-1 and WLn, and a source line SL.

According to some embodiments, the memory cells of each column correspond to the same bit line, e.g., as shown in FIG. 18A, both memory cells of the left column correspond to bit line BLn-1. It should be appreciated that although not shown, the bit line structures of memory cells of the same column are electrically connected.

According to some embodiments, the memory cells of each row correspond to the same word line, e.g., as shown in FIG. 18A, the three memory cells of the upper row each correspond to word line WLn 1. According to some embodiments, as shown in fig. 18A, each word line extends through multiple memory cells in the same row.

According to some embodiments, each row of memory cells corresponds to one control line, e.g., in fig. 18A, the upper row of memory cells corresponds to control line CGn-1, the lower row of memory cells corresponds to control line CGn, and each control line is connected to a memory layer in the corresponding memory cell.

According to some embodiments, memory cells of adjacent rows correspond to the same source line, e.g., as shown in fig. 18A, six memory cells in both upper and lower rows correspond to source line SL. According to some embodiments, as shown in fig. 18A, a source line SL extends in the substrate through adjacent rows of memory cells, wherein the source line communicates with source regions in a plurality of bit lines.

The memory cell array 1800 shown in fig. 18B differs from the memory cell array 1800 shown in fig. 18A in that instead of the source lines SL extending through the plurality of bit lines in the substrate, corresponding tungsten plugs (e.g., corresponding tungsten plugs Wn-1 of bit lines BLn-1) are provided on each bit line and each tungsten plug is connected by a metal line to communicate with the source regions in the plurality of bit lines.

Some exemplary aspects of the disclosure are described below.

Aspect 1. A method of manufacturing a semiconductor device includes:

Sequentially forming a first oxide layer, a storage layer, a second oxide layer, a control gate layer and a hard mask layer on a substrate;

Etching the hard mask layer, the control gate layer, the second oxide layer, the memory layer, and the first oxide layer to form a gate stack composed of remaining portions of the hard mask layer, the control gate layer, the second oxide layer, the memory layer, and the first oxide layer;

Forming a first gate spacer and a second gate spacer on two sides of the gate stack, respectively, and forming a first select gate oxide structure and a second select gate oxide structure on a first region and a second region of the substrate, respectively, wherein the first region and the second region are located on two sides of the gate stack;

Forming a first select gate on a side of the first gate spacer opposite the gate stack, and forming a second select gate on a side of the second gate spacer opposite the gate stack;

etching the gate stack to form a first opening through the hard mask layer, the control gate layer, the second oxide layer, and the memory layer;

forming a source region in a portion of the substrate under the first opening, and

A first drain region is formed in the substrate on a side of the first select gate opposite the first opening, and a second drain region is formed in the substrate on a side of the second select gate opposite the first opening.

Aspect 2 the method of aspect 1, wherein forming a first gate spacer and a second gate spacer on both sides of the gate stack, respectively, and forming a first select gate oxide structure and a second select gate oxide structure on a first region and a second region of the substrate, respectively, comprises:

Forming control gate spacers on both sides of the gate stack;

Depositing a first gate oxide film on the side and upper surfaces of the gate stack, and the first and second regions of the substrate;

Removing portions of the first gate oxide film on the upper surface of the gate stack and the first and second regions of the substrate to form the first and second gate spacers, and

A first select gate oxide structure and a second select gate oxide structure are formed on the first region and the second region of the substrate, respectively.

Aspect 3 the method of aspect 2, wherein the depositing a first gate oxide film on the side and upper surfaces of the gate stack and the first and second regions of the substrate comprises:

a first gate oxide film is deposited on the sides and upper surface of the gate stack, and the first, second and high voltage tube regions of the substrate.

Aspect 4. The method of aspect 1, further comprising forming a first select gate on a side of the first gate spacer opposite the gate stack, and, prior to forming a second select gate on a side of the second gate spacer opposite the gate stack:

performing logic well implantation in the substrate;

forming a logic IO gate oxide structure on the substrate, and

A logic core gate oxide structure is formed on the substrate.

Aspect 5. The method of aspect 4, wherein forming the first and second select gate oxide structures on the first and second regions of the substrate, respectively, comprises:

The first select gate oxide structure and the second select gate oxide structure are formed on the first region and the second region of the substrate, respectively, while the logic IO gate oxide structure or the logic core gate oxide structure is formed.

Aspect 6 the method of aspect 2, further comprising, prior to depositing a first gate oxide film on the side and upper surfaces of the gate stack and the first and second regions of the substrate:

Select gate channel ion implantation is performed in the first region and the second region of the substrate.

Aspect 7 the method of any one of aspects 1-6, the forming a first select gate on a side of the first gate spacer opposite the gate stack, and forming a second select gate on a side of the second gate spacer opposite the gate stack comprising:

Depositing select gate polysilicon over the first and second select gate oxide structures and over the gate stack, and

Portions of the deposited select gate polysilicon are removed to form the first select gate and the second select gate.

Aspect 8 the method of aspect 7, wherein the removing the portion of the deposited select gate polysilicon to form the first select gate and the second select gate comprises:

The selection of the deposited flattening the grid polysilicon;

etching the select gate polysilicon subjected to the planarization process to form first and second polysilicon structures on the first and second regions of the substrate, respectively, and

The first and second polysilicon structures are etched to form the first and second select gates, respectively.

Aspect 9 the method of aspect 8, wherein the etching the first and second polysilicon structures to form the first and second select gates, respectively, comprises:

performing first photoetching treatment on the first polycrystalline silicon structure and the second polycrystalline silicon structure;

etching the first and second polysilicon structures using the photoresist pattern formed by the first photolithography process as a mask to form the first and second select gates, respectively, and

And removing the photoresist pattern formed by the first photoetching treatment.

Aspect 10 the method of aspect 8, wherein the etching the first and second polysilicon structures to form the first and second select gates, respectively, comprises:

forming a first hard mask spacer and a second hard mask spacer on both sides of the gate stack, respectively, wherein the first hard mask spacer is located on the first polysilicon structure and the second hard mask spacer is located on the second polysilicon structure, and

And etching the first polysilicon structure and the second polysilicon structure by taking the first hard mask spacer and the second hard mask spacer as masks to form the first selection gate and the second selection gate respectively.

Aspect 11 the method of any one of aspects 1-6, wherein the forming a first drain region in the substrate on a side of the first select gate opposite the first opening, and forming a second drain region in the substrate on a side of the second select gate opposite the first opening comprises:

Performing a lightly doped drain implant in the substrate on a side of the first select gate opposite the first opening and in the substrate on a side of the second select gate opposite the first opening to form a first lightly doped drain region on a side of the first select gate and a second lightly doped drain region on a side of the second select gate;

Forming a first drain spacer on a side of the first select gate opposite the first opening, and forming a second drain spacer on a side of the second select gate opposite the first opening;

forming a first source spacer on a side of the first select gate facing the first opening, and forming a second source spacer on a side of the second select gate facing the first opening, and

A heavily doped drain implant is performed in the substrate on a side of the first drain spacer opposite the first opening and in the substrate on a side of the second drain spacer opposite the first opening to form a first heavily doped drain region on a side of the first drain spacer and a second heavily doped drain region on a side of the second drain spacer.

Aspect 12. The method of any one of aspects 1-6, further comprising:

Silicide structures are formed on the first select gate, the first drain region, the source region, the second select gate, and the second drain region.

Aspect 13. A method of manufacturing a semiconductor device includes:

sequentially forming a first oxide layer, a select gate layer and a hard mask layer on a substrate;

etching the hard mask layer and the select gate layer to form a gate stack comprised of the hard mask layer and a remaining portion of the select gate layer;

Forming a first storage structure on a first side of the gate stack and a first gate region, and forming a second storage structure on a second side of the gate stack and a second gate region, wherein the first gate region is located on one side of the first side of the gate stack and the second gate region is located on one side of the second side of the gate stack;

forming a first control gate over the first memory structure and forming a second control gate over the second memory structure;

Etching the gate stack to form a first opening through the hard mask layer and the select gate layer;

Forming a drain region in a portion of the substrate below the first opening, and

A first source region is formed in the substrate on a side of the first control gate opposite the first opening, and a second source region is formed in the substrate on a side of the second control gate opposite the first opening.

Aspect 14 the method of aspect 13, wherein the forming a first memory structure on the first side of the gate stack and the first gate region, and forming a second memory structure on the second side of the gate stack and the second gate region comprises:

Forming a selection gate spacer on both sides of the gate stack;

Depositing a first gate oxide film on side and upper surfaces of the gate stack, and on first and second regions of the substrate, wherein the first and second regions are located on both sides of the gate stack, the first region including the first gate region, the second region including the second gate region;

removing portions of the first gate oxide film on the upper surface of the gate stack and the first and second regions of the substrate;

Sequentially depositing a first memory oxide layer, a memory layer, and a second memory oxide layer on the side and upper surfaces of the gate stack, and the first and second regions of the substrate, and

Portions of the first, storage, and second storage oxide layers on non-gate regions of the substrate and on an upper surface of the gate stack are removed to form the first and second storage structures, wherein the non-gate regions include portions of the first region that are not included in the first gate region and portions of the second region that are not included in the second gate region.

The method of aspect 15, wherein the forming a first control gate over the first memory structure and a second control gate over the second memory structure comprises:

Depositing a control gate polysilicon on the second memory oxide layer after sequentially depositing a first memory oxide layer, a memory layer, and a second memory oxide layer on the side and upper surfaces of the gate stack and the first and second regions of the substrate, and

Portions of the deposited control gate polysilicon are removed to form the first control gate and the second control gate while portions of the first, storage, and second storage oxide layers are removed on non-gate regions of the substrate and on an upper surface of the gate stack.

Aspect 16. The method of aspect 15, the removing the portion of the control gate polysilicon deposited to form the first control gate and the second control gate comprises:

said control of said deposited flattening the grid polysilicon;

Etching the control gate polysilicon subjected to the planarization process to form first and second polysilicon structures on the first and second regions of the substrate, respectively, and

The first and second polysilicon structures are etched to form the first and second control gates, respectively.

Aspect 17 the method of aspect 16, wherein the etching the first and second polysilicon structures to form the first and second control gates, respectively, comprises:

etching the first and second polysilicon structures using the photoresist pattern formed by the first photolithography process as a mask to form the first and second control gates, respectively, and

Aspect 18 the method of aspect 13, further comprising forming a first control gate over the first memory structure, and, prior to forming a second control gate over the second memory structure:

performing logic well implantation in the substrate;

forming a logic IO gate oxide structure on the substrate, and

A logic core gate oxide structure is formed on the substrate.

Aspect 19 the method of aspect 14, further comprising, prior to depositing a first gate oxide film on the side and upper surfaces of the gate stack and the first and second regions of the substrate:

memory channel ion implantation is performed in the first region and the second region of the substrate.

Aspect 20 the method of any one of aspects 13-19, wherein the forming a drain region in a portion of the substrate below the first opening comprises:

Performing lightly doped drain implantation in the substrate below the first opening to form a lightly doped drain region in the substrate below the first opening;

forming a first drain spacer and a second drain spacer on sides of the gate stack in the first opening, and

A heavily doped source implant is performed in the substrate under the first opening between the first drain spacer and the second drain spacer to form a heavily doped drain region between the first drain spacer and the second drain spacer.

Aspect 21 the method of any one of aspects 13-19, further comprising:

Silicide structures are formed on the first control gate, the first source region, the drain region, the second control gate, and the second source region.

Aspect 22. A semiconductor device manufactured by the method according to any one of aspects 1 to 21.

While the disclosure has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative and schematic and are not restrictive in character, the disclosure not being limited to the disclosed embodiments. Variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed subject matter, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps than those listed and the indefinite article "a" or "an" does not exclude a plurality, and the term "plurality" means two or more. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A method of manufacturing a semiconductor device, comprising:

sequentially forming a first oxide layer, a memory layer, a second oxide layer, a control gate layer and a hard mask layer on a substrate;

Forming a first gate spacer and a second gate spacer on both sides of the gate stack, respectively, and forming a first select gate oxide structure and a second select gate oxide structure on the first region and the second region of the substrate, respectively, wherein the method comprises:

Forming control gate spacers on both sides of the gate stack;

Performing a select gate channel ion implantation in a first region and a second region of the substrate;

Depositing oxides with preset thickness on a first area and a second area of the substrate to form a first selective gate oxide structure and a second selective gate oxide structure respectively, wherein the first area and the second area are positioned on two sides of the gate stack body, the thickness of the first gate spacer is larger than that of the first selective gate oxide structure, and the thickness of the second gate spacer is larger than that of the second selective gate oxide structure;

2. The method of claim 1, wherein the depositing a first gate oxide film on the sides and upper surface of the gate stack and the first and second regions of the substrate comprises:

3. The method of claim 1, further comprising forming a first select gate on a side of the first gate spacer opposite the gate stack, and prior to forming a second select gate on a side of the second gate spacer opposite the gate stack:

performing logic well implantation in the substrate;

forming a logic IO gate oxide structure on the substrate, and

A logic core gate oxide structure is formed on the substrate.

4. The method of claim 3, wherein forming a first select gate oxide structure and a second select gate oxide structure on the first region and the second region of the substrate, respectively, comprises:

5. The method of any of claims 1-4, the forming a first select gate on a side of the first gate spacer opposite the gate stack, and the forming a second select gate on a side of the second gate spacer opposite the gate stack comprising:

6. The method of claim 5, wherein the removing the deposited portion of the select gate polysilicon to form the first select gate and the second select gate comprises:

The selection of the deposited flattening the grid polysilicon;

7. The method of claim 6, wherein the etching the first and second polysilicon structures to form the first and second select gates, respectively, comprises:

8. The method of claim 6, wherein the etching the first and second polysilicon structures to form the first and second select gates, respectively, comprises:

9. The method of any of claims 1-4, wherein the forming a first drain region in the substrate on a side of the first select gate opposite the first opening, and the forming a second drain region in the substrate on a side of the second select gate opposite the first opening comprises:

10. The method of any of claims 1-4, further comprising:

11. A method of manufacturing a semiconductor device, comprising:

forming a first memory structure on a first side of the gate stack and a first gate region, and forming a second memory structure on a second side of the gate stack and a second gate region, comprising:

Forming a selection gate spacer on both sides of the gate stack;

depositing a first gate oxide film on a side and an upper surface of the gate stack, and on a first region and a second region of the substrate, wherein the first region and the second region are located on both sides of the gate stack, the first region includes the first gate region, and the second region includes the second gate region, wherein the first gate region is located on one side of a first side of the gate stack, and the second gate region is located on one side of a second side of the gate stack;

performing memory channel ion implantation in the first region and the second region of the substrate;

Removing portions of the first, storage, and second storage oxide layers on non-gate regions of the substrate and on an upper surface of the gate stack to form the first and second storage structures, wherein the non-gate regions include portions of the first region that are not included in the first gate region and portions of the second region that are not included in the second gate region;

12. The method of claim 11, wherein the forming a first control gate over the first storage structure and a second control gate over the second storage structure comprises:

13. The method of claim 12, the removing portions of the deposited control gate polysilicon to form the first control gate and the second control gate comprising:

said control of said deposited flattening the grid polysilicon;

14. The method of claim 13, wherein the etching the first and second polysilicon structures to form the first and second control gates, respectively, comprises:

15. The method of claim 11, further comprising forming a first control gate over the first storage structure and, prior to forming a second control gate over the second storage structure:

performing logic well implantation in the substrate;

forming a logic IO gate oxide structure on the substrate, and

A logic core gate oxide structure is formed on the substrate.

16. The method of any of claims 11-15, wherein the forming a drain region in a portion of the substrate below the first opening comprises:

17. The method of any of claims 11-15, further comprising: