CN114944387B - Common source type power device and manufacturing method thereof - Google Patents
Common source type power device and manufacturing method thereofInfo
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- CN114944387B CN114944387B CN202210564383.XA CN202210564383A CN114944387B CN 114944387 B CN114944387 B CN 114944387B CN 202210564383 A CN202210564383 A CN 202210564383A CN 114944387 B CN114944387 B CN 114944387B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D64/251—Source or drain electrodes for field-effect devices
- H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
本发明公开了一种共源型功率器件及其制作方法，主要解决现有开关器件存在的不能同时进行双向导通和双向阻断的问题，其包括：衬底、过渡层、第一沟道层、第一势垒层、第二沟道层和第二势垒层，这两个沟道层与两个势垒层的左、右两侧均设有台面，这两个台面上分别设有左、右漏极；第二沟道层与第二势垒层的中间均设有N+区，该N+区的下侧位于第二沟道层内，且N+区上部与第一沟道层之间设有凹槽，凹槽内设有阳极与源极；左漏极与源极之间的第二势垒层上设有左P型块和左栅极；右漏极与源极之间的第二势垒层上设有右P型块和右栅极。本发明可同时实现双向导通和双向阻断，减小二极管模式下的开启电压，降低损耗，提升集成度，可作为开关器件。
The present invention discloses a common-source power device and its manufacturing method, which primarily addresses the problem of existing switching devices being unable to simultaneously conduct and block in both directions. The common-source power device comprises: a substrate, a transition layer, a first channel layer, a first barrier layer, a second channel layer, and a second barrier layer. The two channel layers and the two barrier layers are each provided with a mesa on the left and right sides, each of which is provided with a left and right drain electrode, respectively. An N + region is provided between the second channel layer and the second barrier layer. The lower side of the N + region is located within the second channel layer, and a groove is provided between the upper portion of the N + region and the first channel layer. The groove contains an anode and a source electrode. A left P-type block and a left gate are provided on the second barrier layer between the left drain and the source. A right P-type block and a right gate are provided on the second barrier layer between the right drain and the source. The present invention can simultaneously conduct and block in both directions, reduce the turn-on voltage in diode mode, reduce losses, and improve integration, making it suitable for use as a switching device.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a power device which can be used for a power electronic system.
Technical Field
The power device is an important element of a power electronic system and is an important tool for realizing energy conversion and control. Therefore, the performance and reliability of the power device have a decisive influence on various technical indexes and performances of the whole power electronic system. Currently, the performance of Si-based switching devices has approached its theoretical limit and has failed to meet the requirements of high temperature, high voltage, high frequency, high efficiency and high power density of the next generation power electronics systems. The third generation wide bandgap semiconductor material represented by GaN has the characteristics of large bandgap, high saturated electron drift speed, large critical breakdown electric field and stable chemical property, and has unique advantages in preparing a switching device with lower on-resistance, faster switching speed and higher breakdown voltage. In particular to a GaN-based heterojunction structure-based high electron mobility device, namely a GaN-based high electron mobility switching device, which has wide and special application prospect in the national economy and military fields by virtue of excellent power characteristics.
The conventional gallium nitride-based enhanced switching device is based on a GaN-based heterojunction structure and comprises a substrate, a transition layer, a channel layer, a barrier layer, a P-GaN gate, a drain electrode, a source electrode and gate metal, wherein the drain electrode is deposited on the left side of the upper part of the barrier layer, the source electrode is deposited on the right side of the upper part of the barrier layer, the P-GaN gate is deposited on the middle part of the upper part of the barrier layer, and the gate metal is deposited on the upper part of the P-GaN gate, as shown in figure 1. However, in the conventional gan-based enhanced switching device, current in the device can be conducted only in one direction from the drain to the source in the on state, and power can be transferred only from the drain to the source, i.e., the conventional gan-based enhanced switching device can realize unidirectional conduction and unidirectional blocking only. In many fields such as an inverter and an ac-ac converter, it is often required that the device has bidirectional conduction and bidirectional blocking capability, and in order to solve the bidirectional conduction and bidirectional blocking problems, the prior document 99.3％ Efficiency of three-phase inverter for motor drive using GaN-based Gate Injection Transistors,2011Twenty-Sixth Annual IEEE Applied Power Electronics Conference and Exposition(APEC),2011,481-484, proposes a structure in which two gan-based enhanced switching devices are connected in series to construct a bidirectional switch, but when the switch is operated in a diode unidirectional conduction mode, for example, when the device 1 is turned on and the device 2 is turned off, the device 2 forms a diode, the turn-on voltage of the diode is larger and equal to the threshold voltage of the device, so that the conduction loss of the switch is greatly increased when the mode is operated, and therefore, the high threshold voltage Vth and the low reverse turn-on voltage V ON cannot be simultaneously realized when the switch is operated in the diode unidirectional conduction mode. This severely limits the practical application of such a switch.
Therefore, there is a need for developing a high-performance gallium nitride-based enhanced switching device with simple process, good bidirectional conduction and bidirectional blocking characteristics, and low turn-on voltage when the diode is operated in unidirectional conduction mode, so as to meet the urgent needs of electronic power systems for such switching devices.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a common source type power device and a manufacturing method thereof, so as to realize bidirectional conduction and bidirectional blocking characteristics simultaneously, reduce the starting voltage of a switching diode in a unidirectional conduction mode, reduce loss and improve the integration level of the switching device.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
1. The common source type power device comprises a substrate 1, a transition layer 2, a second channel layer 5 and a second barrier layer 6 from bottom to top, and is characterized in that:
A first channel layer 3 and a first barrier layer 4 are inserted between the transition layer 2 and the second channel layer 5, and the first barrier layer 4 is positioned on the upper part of the first channel layer 3;
the left and right sides of the first channel layer 3, the first barrier layer 4, the second channel layer 5 and the second barrier layer 6 are respectively provided with a table top 7, the lower ends of the two table tops 7 are respectively positioned at the upper part of the transition layer 2, and the table tops 7 at the left and right sides are respectively provided with a left drain electrode 8 and a right drain electrode 9;
An N + region 10 is arranged in the middle of the second channel layer 5 and the second barrier layer 6, and the lower side of the N + region 10 is positioned inside the second channel layer 5;
A groove 11 is arranged between the upper part of the N + region 10 and the interior of the first channel layer 3, the upper part and the lower part of the interior of the groove are respectively provided with a source electrode 13 and an anode electrode 12, and the contact surfaces of the two electrodes are positioned at the lower side of the N + region 10;
A left P-type block 14 and a left grid electrode 16 are arranged on the second barrier layer 6 between the left drain electrode 8 and the source electrode 13, and a right P-type block 15 and a right grid electrode 17 are arranged on the second barrier layer 6 between the right drain electrode 9 and the source electrode 13.
Further, the thickness S 1 of the first barrier layer 4 is 2-60 nm, and the thickness S 2 of the second barrier layer 6 is 2-60 nm.
Further, the N + region 10 is an N-type heavily doped region with an implant dose greater than 1×10 20cm-2.
Further, the lower side of the groove 11 is located inside the first channel layer 3, and the distance between the lower side of the groove 11 and the upper surface of the first channel layer 3 is at least 5nm.
Further, the distance t between the upper side of the anode 12 and the lower side of the N + region 10 is >0nm.
Further, the thickness h of the left P-type block 14 and the right P-type block 15 is 10-500 nm, and the doping concentration is 1×10 16～5×1020cm-3.
Further, the left gate 16 is located at an upper portion of the left P-type block 14, and the right gate 17 is located at an upper portion of the right P-type block 15.
Further, the left drain electrode 8 and the right drain electrode 9 are combined by adopting the same metal, and ohmic contact is formed between the left drain electrode and the right drain electrode respectively;
further, the anode 12 adopts a plurality of layers of metals, the bottommost metal is a high work function metal, and schottky contact is formed between the anode 12 and the contacted semiconductor;
further, ohmic contact is formed between the source electrode 13 and the contacted semiconductor.
2. The method for manufacturing the common source type power device is characterized by comprising the following steps of:
a) A GaN-based wide bandgap semiconductor material is epitaxially grown on a substrate 1 to form a transition layer 2 with the thickness of 1-50 mu m;
b) Manufacturing a channel layer and a barrier layer:
b1 Epitaxial GaN material on the transition layer 2 to form a first channel layer 3 with the thickness of 10-200 nm;
B2 A GaN-based wide band gap semiconductor material is epitaxially grown on the first channel layer 3, and a first barrier layer 4 with the thickness S 1 of 2-60 nm is formed;
b3 Epitaxial GaN material on the first barrier layer 4 to form a second channel layer 5 with a thickness of 10-200 nm;
B4 A GaN-based wide band gap semiconductor material is epitaxially grown on the second channel layer 5, and a second barrier layer 6 with the thickness S 2 of 2-60 nm is formed;
c) A mask is manufactured on the second barrier layer 6 for the first time, and etching is carried out on two sides of the second barrier layer 6, the second channel layer 5, the first barrier layer 4 and the first channel layer 3 respectively by using the mask until the upper surface of the transition layer 2 is etched, so that a left mesa 7 and a right mesa 7 are formed;
d) Depositing multiple layers of metals on the left and right table tops 7 respectively by using the mask manufactured in the step C), and performing rapid thermal annealing to form a left drain electrode 8 and a right drain electrode 9, wherein ohmic contact is formed between the two drain electrodes and the contacted semiconductor;
E) Manufacturing masks on the second barrier layer 6, the left drain electrode 8 and the right drain electrode 9 for the second time, performing ion implantation on the second channel layer 5 and the middle position of the second barrier layer 6 by using the masks to form an N + region 10, and ensuring that the first channel layer 3 is not damaged when the implantation dosage and the implantation energy are determined;
F) Manufacturing masks on the second barrier layer 6, the left drain electrode 8, the right drain electrode 9 and the N + region 10 for the third time, and respectively etching the middle part of the N + region 10, the second channel layer 5, the first barrier layer 4 and the first channel layer 3 by using the masks to form a groove 11;
G) Depositing a plurality of layers of metal inside the groove 11 by utilizing the mask manufactured in the step F) to form an anode 12, wherein the anode 12 is in schottky contact with the semiconductor material contacted with the semiconductor material, and then depositing a metal combination on the upper part of the anode 12 to form a source electrode 13, wherein ohmic contact is formed between the source electrode 13 and the second channel layer 5 and between the source electrode 13 and the first barrier layer 4;
H) Forming a P-type layer by extending P-type semiconductor materials on the second barrier layer 6, the left drain electrode 8, the right drain electrode 9, the N + region 10 and the source electrode 13, and then manufacturing a mask on the P-type layer for the fourth time, and etching the P-type layer by using the mask to form a left P-type block 14 and a right P-type block 15;
I) And fifth manufacturing masks are formed on the second barrier layer 6, the left drain electrode 8, the right drain electrode 9, the N + region 10, the source electrode 13, the left P-type block 14 and the right P-type block 15, and multiple layers of metals are deposited on the left P-type block 14 and the right P-type block 15 by utilizing the masks to respectively form a left grid electrode 16 and a right grid electrode 17, so that the whole device is manufactured.
Compared with the traditional gallium nitride-based enhanced switching device, the device has the following advantages:
first, bidirectional conduction and bidirectional blocking characteristics can be achieved.
In the device, as the first channel layer and the first barrier layer are inserted, an electron channel is formed at the contact interface of the first channel layer and the first barrier layer, the channel, the left drain electrode and the anode form a left Schottky diode structure, the channel, the right drain electrode and the anode form a right Schottky diode structure, and the two diodes are distributed back to back, so that electrons have a left current path in the left Schottky diode and a right current path in the right Schottky diode;
Simultaneously, due to the combined action of spontaneous polarization and piezoelectric polarization, a two-dimensional electron gas channel is formed at the contact interface of the second channel layer and the second barrier layer, the channel, the left drain electrode, the source electrode, the left P-type block and the left grid electrode form a left-side switch transistor, the channel, the right drain electrode, the source electrode, the right P-type block and the right grid electrode form a right-side switch transistor, namely, the two transistors are connected through the common source electrode, so that electrons have a rightward current path in the left-side transistor and a leftward current path in the right-side transistor, the electric potentials on the left grid electrode and the right grid electrode can be controlled, the on and off of the left-side transistor and the state of the two diodes can be controlled by applying different voltages on the left drain electrode and the right drain electrode, and the bidirectional on-state and bidirectional blocking characteristics of the device are realized.
Secondly, the device adopts a mode that the switching transistor and the Schottky diode are vertically stacked, and compared with the traditional mode that discrete components are placed on the same PCB for interconnection, parasitic parameters caused by interconnection can be reduced, and the integration level of the switching device is remarkably improved.
Third, the active area between the drain electrode and the source electrode of the switching transistor and the active area between the anode electrode and the drain electrode of the Schottky diode are overlapped in the vertical direction, the drain electrode is used as the cathode electrode of the diode and the drain electrode of the switching transistor, the two back-to-back diodes share the anode electrode, the two transistors share the source electrode, external connection is reduced, and the area of the device in the horizontal direction is greatly reduced.
Fourth, because two embedded schottky diodes are adopted in the device, the device can realize very low turn-on voltage when the device works in the diode unidirectional conduction mode.
Drawings
Fig. 1 is a block diagram of a conventional gallium nitride-based enhanced switching device;
fig. 2 is a structural diagram of a common source type power device of the present invention;
FIG. 3 is a top view of FIG. 2;
FIG. 4 is a schematic diagram of an overall process for fabricating a common source power device according to the present invention;
FIG. 5 is a graph showing the results of a test for the on-state characteristics of the device of the present invention;
fig. 6 is a test result of blocking characteristics of the device of the present invention.
Detailed Description
Embodiments of the present invention are described in further detail below with reference to the accompanying drawings.
Referring to fig. 2 and 3, the common source type power device of the present invention includes a substrate 1, a transition layer 2, a first channel layer 3, a first barrier layer 4, a second channel layer 5, a second barrier layer 6, a mesa 7, a left drain 8, a right drain 9, an N + region 10, a recess 11, an anode 12, a source 13, a left P-type block 14, a right P-type block 15, a left gate 16, and a right gate 17. Wherein:
the substrate 1 is made of silicon carbide or sapphire or silicon or other materials;
The transition layer 2 is positioned at the upper part of the substrate 1 and consists of a plurality of layers of identical or different GaN-based wide forbidden band semiconductor materials, and the thickness of the transition layer is 1-50 mu m;
the first channel layer 3 is positioned at the upper part of the transition layer 2 and is made of a GaN material, and the thickness of the first channel layer is 10-200 nm;
The first barrier layer 4 is positioned at the upper part of the first channel layer 3 and is made of a GaN-based wide forbidden band semiconductor material, and the thickness S 1 is 2-60 nm;
The second channel layer 5 is positioned on the upper part of the first barrier layer 4, is made of GaN material and has a thickness of 10-200 nm;
The second barrier layer 6 is positioned at the upper part of the second channel layer 5 and is made of a GaN-based wide forbidden band semiconductor material, and the thickness S 2 is 2-60 nm;
The number of the table tops 7 is two, and the table tops 7 are respectively positioned at the left side and the right side of the first channel layer 3, the first barrier layer 4, the second channel layer 5 and the second barrier layer 6, and the lower ends of the two table tops 7 are positioned at the upper part of the transition layer 2;
The left drain electrode 8 and the right drain electrode 9 are respectively positioned at the upper parts of the table tops 7 at the left side and the right side, adopt the same multi-layer metal combination, and form ohmic contact with the contacted semiconductors;
the N + region 10 is located in the middle of the second channel layer 5 and the second barrier layer 6, the lower side of the N + region is located in the second channel layer 5, the N + region 10 is an N-type heavily doped region formed by ion implantation, the implantation dose is greater than 1×10 20cm-2, and almost no damage to the first channel layer 3 should be ensured when the implantation depth and dose are selected;
The groove 11 is positioned between the upper part of the N + region 10 and the interior of the first channel layer 3, the lower side of the groove 11 is positioned in the interior of the first channel layer 3, and the distance between the lower side of the groove 11 and the upper surface of the first channel layer 3 is at least 5nm;
the anode 12 is positioned in the groove 11, the distance t between the upper part of the anode 12 and the lower part of the N + region 10 is more than 0nm, the anode 12 adopts a multi-layer metal combination, the bottommost metal is a high work function metal, and Schottky contact is formed between the anode 12 and the contacted semiconductor;
The source electrode 13 is positioned at the upper part of the anode 12, the contact surface of the source electrode 13 and the anode 12 is positioned at the lower side of the N + region 10, and ohmic contact is formed between the source electrode 13 and the contacted semiconductor;
The left P-type block 14 is located on the second barrier layer 6 between the left drain electrode 8 and the source electrode 13, the right P-type block 15 is located on the second barrier layer 6 between the right drain electrode 9 and the source electrode 13, the thicknesses h of the left P-type block 14 and the right P-type block 15 are 10-500 nm, the doping concentrations are 1×10 16～5×1020cm-3, and almost no depletion effect on the first barrier layer 4 is ensured when the thicknesses h of the left P-type block 14 and the right P-type block 15 are determined;
the left gate 16 is located at the upper portion of the left P-type block 14, and the right gate 17 is located at the upper portion of the right P-type block 15.
Referring to fig. 4, three embodiments of the common source type power device manufactured by the present invention are shown below.
In the first embodiment, a common source type power device is manufactured on a silicon carbide substrate, wherein the thicknesses of a first channel layer 3, a first barrier layer 4, a second channel layer 5 and a second barrier layer 6 are respectively 10nm, 2nm, 10nm and 2nm, the implantation dose of an N + region 10 is 5 multiplied by 10 20cm-2,N+, the distance t between the lower part of the region 10 and the upper part of an anode 12 is 1nm, the thicknesses h of a left P-type block 14 and a right P-type block 15 are 10nm, and the doping concentration is 5 multiplied by 10 18cm-3.
Step 1. A transition layer 2 is made of AlN and GaN materials which are epitaxially grown on a silicon carbide substrate 1 from bottom to top, as shown in FIG. 4a.
(1.1) Epitaxial thickness of undoped AlN material with thickness of 100nm on silicon carbide substrate 1 by using metal organic chemical vapor deposition technique, wherein the process conditions of metal organic chemical vapor deposition are that the temperature is 1000 ℃, the pressure is 45Torr, the hydrogen flow is 4400sccm, the ammonia flow is 4400sccm, and the aluminum source flow is 5 mu mol/min;
(1.2) epitaxial thickness of GaN material with thickness of 0.9 μm on AlN material by metal organic chemical vapor deposition technique, and the process conditions are that the temperature is 960 ℃, the pressure is 45Torr, the hydrogen flow is 4400sccm, the ammonia flow is 4400sccm, and the gallium source flow is 120. Mu. Mol/min.
Step 2, a channel layer and a barrier layer are manufactured on the GaN transition layer 2, as shown in FIG. 4b.
(2.1) Epitaxial GaN material on the GaN transition layer 2 by using a metal organic chemical vapor deposition technology to form a first channel layer 3 with the thickness of 10nm, wherein the process conditions of the metal organic chemical vapor deposition are that the temperature is 900 ℃, the pressure is 40Torr, the hydrogen flow is 4000sccm, the ammonia flow is 4000sccm, and the gallium source flow is 90 mu mol/min;
(2.2) forming a first barrier layer 4 by using a metal organic chemical vapor deposition technology on the first channel layer 3, wherein the epitaxial thickness S 1 is 2nm, the aluminum component is undoped Al 0.4Ga0.6 N of 0.4, the process conditions are that the temperature is 980 ℃, the pressure is 45Torr, the hydrogen flow is 4300sccm, the ammonia flow is 4300sccm, the gallium source flow is 35 mu mol/min, and the aluminum source flow is 7 mu mol/min;
(2.3) epitaxial GaN material on the first barrier layer 4 by using a metal organic chemical vapor deposition technology to form a second channel layer 5 with the thickness of 10nm, wherein the process conditions are that the temperature is 900 ℃, the pressure is 40Torr, the hydrogen flow is 4000sccm, the ammonia flow is 4000sccm, and the gallium source flow is 90 mu mol/min;
(2.4) the second barrier layer 6 was formed by using a metal organic chemical vapor deposition technique to epitaxially deposit an undoped Al 0.3Ga0.7 N having a thickness S 2 of 2nm and an aluminum composition of 0.3 on the second channel layer 5, under the process conditions of 980℃at 45Torr, a hydrogen flow rate of 4200sccm, an ammonia flow rate of 4200sccm, a gallium source flow rate of 39. Mu. Mol/min, and an aluminum source flow rate of 5. Mu. Mol/min.
Step3. Mesa 7 is fabricated as shown in fig. 4c.
A mask is manufactured on the second barrier layer 6 for the first time, and the mask is used for etching the two sides of the second barrier layer 6, the second channel layer 5, the first barrier layer 4 and the first channel layer 3 respectively by using a reactive ion etching technology until the upper surface of the transition layer 2 is etched to form a left mesa 7 and a right mesa 7;
The etching adopts the process conditions that the Cl 2 flow is 15sccm, the pressure is 10mTorr, and the power is 100W.
Step 4. Depositing and forming a left drain electrode 8 and a right drain electrode 9, as shown in fig. 4d.
Using the mask manufactured in the step 3 to deposit multi-layer metal on the left and right table tops 7 respectively by using an electron beam evaporation technology, wherein the multi-layer metal adopts Al, ni and Au, the thickness of the multi-layer metal is 0.016 mu m/0.177 mu m/0.058 mu m respectively, and the multi-layer metal is subjected to rapid thermal annealing for 30s in N 2 atmosphere with the temperature of 870 ℃ to form a left drain electrode 8 and a right drain electrode 9, and ohmic contact is formed between the two drain electrodes and a contacted semiconductor;
the deposition process conditions are that the vacuum degree is less than 1.8X10 -3 Pa, the power is 380W, and the evaporation rate is less than
Step 5. N + region 10 is fabricated as shown in fig. 4e.
A mask is manufactured on the second barrier layer 6, the left drain electrode 8 and the right drain electrode 9 for the second time, and ion implantation is carried out on the middle positions of the second channel layer 5 and the second barrier layer 6 by utilizing the mask to form an N + region 10;
The ion implantation process conditions are that the implanted N-type impurity is nitrogen ion, the implantation energy is 17keV, and the implantation dosage is 5 multiplied by 10 20cm-2.
Step 6. Etching to form a groove 11, as shown in fig. 4f.
Manufacturing masks on the second barrier layer 6, the left drain electrode 8, the right drain electrode 9 and the N + region 10 for the third time, and respectively etching the middle part of the N + region 10, the second channel layer 5, the first barrier layer 4 and the first channel layer 3 by using a reactive ion etching technology by using the masks, wherein the etching depth is 19nm, so as to form a groove 11;
The process condition of etching the groove is that the Cl 2 flow is 15sccm, the pressure is 10mTorr, and the power is 100W.
Step 7. An anode 12 is fabricated in the recess 11 as shown in fig. 4g.
Depositing a plurality of layers of metal inside the groove 11 by using the mask manufactured in the step 6 and using an electron beam evaporation technology, wherein the deposited metal is a Ti/Au metal combination, namely, the lower layer is Ti, the upper layer is Au, the thickness of the lower layer is 0.004 mu m/0.002 mu m, an anode 12 is formed, and Schottky contact is formed between the anode 12 and the contacted semiconductor material;
The technological conditions for depositing metal are vacuum degree less than 1.8X10 -3 Pa, power 200W and evaporation rate less than
Step 8. Source electrode 13 is fabricated on anode 12 as shown in fig. 4h.
Using the mask produced in step 6, depositing a plurality of layers of metals Al, ni, au, which have thicknesses of 0.008 μm/0.005 μm/0.006 μm, respectively, on the upper portion of the anode 12 using electron beam evaporation technique, forming a source electrode 13, the source electrode 13 forming ohmic contact with the second channel layer 5, the first barrier layer 4;
The metal deposition process has vacuum degree less than 1.8X10 -3 Pa, power 400W and evaporation rate less than
Step 9, manufacturing a left P-type block 14 and a right P-type block 15, as shown in fig. 4i.
(9.1) Forming a P-type NiO layer on the second barrier layer 6, the left drain electrode 8, the right drain electrode 9, the N + region 10 and the source electrode 13 by using a magnetron sputtering technology, wherein NiO materials with the concentration of 5 multiplied by 10 18cm-3 and the thickness of 10nm are epitaxially doped;
The sputtering process conditions are that the power is 110W, the temperature is 300 ℃, the Ar flow is 20sccm, and the O 2 flow is 30sccm;
(9.2) manufacturing a mask on the P-type NiO layer for the fourth time, and etching the P-type NiO layer by using a reactive ion etching technology by using the mask until the upper surface of the second barrier layer 6 is etched, so as to respectively form a left P-type block 14 and a right P-type block 15;
The etching process conditions are that the Cl 2 flow is 15sccm, the pressure is 10mTorr, and the power is 120W.
Step 10, a left gate 16 and a right gate 17 are fabricated as shown in fig. 4j.
And fifth manufacturing masks on the second barrier layer 6, the left drain electrode 8, the right drain electrode 9, the N + region 10, the source electrode 13, the left P-type block 14 and the right P-type block 15, respectively depositing metal combination Ta/Au on the left P-type block 14 and the right P-type block 15 by using a sputtering technology by utilizing the masks, namely, the lower layer is Ta, the upper layer is Au, the thicknesses of the lower layer and the upper layer are respectively 0.021 mu m/0.28 mu m, and respectively forming a left grid electrode 16 and a right grid electrode 17 to finish the manufacturing of the whole device.
The sputtering process conditions were about 0.1Pa of air pressure, 8sccm of Ar flow, 200 ℃ of substrate temperature, and 150W of target RF power.
In the second embodiment, the first channel layer 3, the first barrier layer 4, the second channel layer 5 and the second barrier layer 6 are respectively formed on the sapphire substrate, the thicknesses of the first barrier layer 4, the second barrier layer 5 and the second barrier layer 6 are 200nm, 60nm, 200nm and 60nm, the injection dose of the N + region 10 is 20nm, the distance t between the lower part of the 2×10 21cm-2,N+ region 10 and the upper part of the anode 12 is 500nm, the thicknesses h of the left P-type block 14 and the right P-type block 15 are 1×10 16cm-3, and the doping concentration is 1×10 16cm-3.
Step one, a transition layer 2 is made of epitaxial GaN material on a sapphire substrate 1, as shown in fig. 4a.
The transition layer 2 was formed by epitaxially growing a GaN material having a thickness of 50 μm on the sapphire substrate 1 using a metal organic chemical vapor deposition technique under process conditions of a temperature of 980 ℃, a pressure of 47Torr, a hydrogen flow rate of 4400sccm, an ammonia flow rate of 4400sccm, and a gallium source flow rate of 120 μmol/min.
And secondly, manufacturing a channel layer and a barrier layer on the GaN transition layer 2, as shown in FIG. 4b.
(2A) Using a metal organic chemical vapor deposition technology to extend GaN material on the GaN transition layer 2 under the process conditions of 900 ℃, 40Torr of pressure, 4000sccm of hydrogen flow, 4000sccm of ammonia flow and 90 mu mol/min of gallium source flow, so as to form a first channel layer 3 with the thickness of 200 nm;
(2b) Forming a first barrier layer 4 by using a metal organic chemical vapor deposition technology under the process conditions that the temperature is 980 ℃, the pressure is 45Torr, the hydrogen flow is 4300sccm, the ammonia flow is 4300sccm, the gallium source flow is 35 mu mol/min, the aluminum source flow is 7 mu mol/min, the epitaxial thickness S 1 on the first channel layer 3 is 60nm, and the aluminum component is 0.2 undoped Al 0.2Ga0.8 N;
(2c) Using a metal organic chemical vapor deposition technology to extend GaN material on the first barrier layer 4 under the process conditions of 900 ℃ of temperature, 40Torr of pressure, 4000sccm of hydrogen flow, 4000sccm of ammonia flow and 90 mu mol/min of gallium source flow, so as to form a second channel layer 5 with the thickness of 200 nm;
(2d) The second barrier layer 6 was formed using a metal organic chemical vapor deposition technique at a temperature of 980 ℃, a pressure of 45Torr, a hydrogen flow of 4200sccm, an ammonia flow of 4200sccm, a gallium source flow of 39 μmol/min, an aluminum source flow of 5 μmol/min, an epitaxial thickness S 2 of 60nm on the second channel layer 5, and an aluminum composition of 0.1 undoped Al 0.1Ga0.9 N.
Step three, the mesa 7 is manufactured as shown in fig. 4c.
A mask is manufactured on the second barrier layer 6 for the first time, and the mask is used for etching the two sides of the second barrier layer 6, the second channel layer 5, the first barrier layer 4 and the first channel layer 3 respectively under the process conditions of Cl 2 flow of 15sccm, pressure of 10mTorr and power of 100W by using a reactive ion etching technology until the upper surfaces of the transition layers 2 are etched to form a left mesa 7 and a right mesa 7.
Step four, depositing and forming a left drain electrode 8 and a right drain electrode 9, as shown in fig. 4d.
The mask manufactured in the step three is utilized, the vacuum degree is less than 1.8X10 -3 Pa, the power is 380W, and the evaporation rate is less thanA multi-layer metal composition is deposited on the left and right mesas 7 using electron beam evaporation techniques, respectively, using Ti, al, ni, au a thickness of 0.226 μm/0.216 μm/0.177 μm/0.158 μm, respectively, and rapid thermal annealing is performed in an N 2 atmosphere at a temperature of 870 ℃ for 30s to form left and right drains 8 and 9, both of which form ohmic contacts with the contacted semiconductor.
Step five, an N + region 10 is fabricated as shown in fig. 4e.
And (3) manufacturing masks on the second barrier layer 6, the left drain electrode 8 and the right drain electrode 9 for the second time, and implanting N-type impurities into the intermediate positions of the second channel layer 5 and the second barrier layer 6 to form an N + region 10 under the process conditions that the implantation energy is 17keV and the implantation dosage is 2 multiplied by 10 21cm-2 by using the masks.
Step six, etching to form a groove 11, as shown in fig. 4f.
And (3) manufacturing masks on the second barrier layer 6, the left drain electrode 8, the right drain electrode 9 and the N + region 10 for the third time, and etching the middle part of the N + region 10, the second channel layer 5, the first barrier layer 4 and the first channel layer 3 by using a reactive ion etching technology under the process conditions of Cl 2 flow of 15sccm, pressure of 10mTorr and power of 100W by using the masks, wherein the etching depth is 340nm, so as to form a groove 11.
Step seven, an anode 12 is fabricated in the recess 11, as shown in fig. 4g.
Using the mask produced in the step six, using electron beam evaporation technique to make vacuum degree less than 1.8X10 -3 Pa, power 200W, evaporation rate less thanA multilayer metal is deposited inside the recess 11, wherein the deposited metal is a W/Au metal combination, i.e. W in the lower layer and Au in the upper layer, with a thickness of 0.035 μm/0.015 μm, forming an anode 12, which anode 12 is in schottky contact with the contacted semiconductor material.
Step eight, a source electrode 13 is manufactured on the upper portion of the anode 12, as shown in fig. 4h.
And (3) using the mask manufactured in the step (six) again, wherein the vacuum degree is less than 1.8X10 -3 Pa, the power is 400W, and the evaporation rate is less thanA multilayer metal Ti, al, ni, au is deposited on the upper part of the anode 12 using electron beam evaporation techniques to a thickness of 0.059/0.068 μm/0.185 μm/0.076 μm, respectively, to form a source 13, which source 13 forms an ohmic contact with the second channel layer 5, the first barrier layer 4.
Step nine, a left P-type block 14 and a right P-type block 15 are fabricated as shown in fig. 4i.
(9A) Using a metal organic chemical vapor deposition technology, forming a P-type GaN layer by using a P-type GaN material with epitaxial doping concentration of 1X 10 16cm-3 and thickness of 500nm on a second barrier layer 6, a left drain electrode 8, a right drain electrode 9, an N + region 10 and a source electrode 13 under the process conditions that the temperature is 950 ℃, the pressure is 40Torr, the hydrogen flow is 4000sccm, a high-purity Mg source is used as a doping agent, the ammonia flow is 4000sccm, and the gallium source flow is 100 mu mol/min;
(9b) And then, a mask is manufactured on the P-type GaN layer for the fourth time, and the mask is utilized to etch the P-type GaN layer by using a reactive ion etching technology under the process conditions of Cl 2 flow of 15sccm, pressure of 10mTorr and power of 120W until the upper surface of the second barrier layer 6 is etched, so that a left P-type block 14 and a right P-type block 15 are respectively formed.
Step ten, a left gate 16 and a right gate 17 are fabricated as shown in fig. 4j.
And a mask is manufactured on the second barrier layer 6, the left drain electrode 8, the right drain electrode 9, the N + region 10, the source electrode 13, the left P-type block 14 and the right P-type block 15 for the fifth time, the flow of Ar is 8sccm under the process conditions that the air pressure is about 0.1Pa, the substrate temperature is fixed at 200 ℃ and the target radio frequency power is 150W, and the mask is utilized to deposit metal combination Gd/Au on the left P-type block 14 and the right P-type block 15 respectively by using a sputtering technology, namely, the lower layer is Gd, the upper layer is Au, the thickness of the lower layer is 0.021 mu m/0.28 mu m, and the left grid 16 and the right grid 17 are formed respectively to finish the manufacturing of the whole device.
In the third embodiment, the first channel layer 3, the first barrier layer 4, the second channel layer 5 and the second barrier layer 6 are respectively formed on the silicon substrate, the thicknesses of the first barrier layer 4, the second barrier layer 5 and the second barrier layer 6 are 40nm, 35nm, 70nm and 20nm, the injection dose of the N + region 10 is 40nm, the distance t between the lower part of the 4×10 22cm-2,N+ region 10 and the upper part of the anode 12 is 40nm, the thicknesses h of the left P-type block 14 and the right P-type block 15 are 120nm, and the doping concentration is 5×10 20cm-3.
Step a. A transition layer 2 is made of AlN and GaN material epitaxially grown on a silicon substrate 1 from bottom to top as shown in fig. 5a.
(A1) Setting the process conditions of 800 ℃, 40Torr of pressure, 4000sccm of hydrogen flow, 4000sccm of ammonia flow and 25 mu mol/min of aluminum source flow, and using a metal organic chemical vapor deposition technology to epitaxially deposit an AlN material with the thickness of 400nm on a silicon substrate 1;
(A2) Setting the technological conditions of 980 ℃ temperature, 45Torr pressure, 4000sccm hydrogen flow, 4000sccm ammonia flow and 120 mu mol/min gallium source flow, and using a metal organic chemical vapor deposition technology to epitaxially deposit GaN material with thickness of 5.6 mu m on the AlN material to finish the manufacture of the transition layer 2.
Step b. A channel layer and a barrier layer are fabricated on the GaN transition layer 2 as shown in fig. 4b.
(B1) Setting the process conditions of 900 ℃ of temperature, 40Torr of pressure, 4000sccm of hydrogen flow, 4000sccm of ammonia flow and 90 mu mol/min of gallium source flow, and using a metal organic chemical vapor deposition technology to extend GaN material on the GaN transition layer 2 to form a first channel layer 3 with the thickness of 40 nm;
(B2) Setting a process condition that the temperature is 980 ℃, the pressure is 45Torr, the hydrogen flow is 4300sccm, the ammonia flow is 4300sccm, the gallium source flow is 35 mu mol/min, the aluminum source flow is 7 mu mol/min, and forming a first barrier layer 4 by using a metal organic chemical vapor deposition technology, wherein the epitaxial thickness S 1 on the first channel layer 3 is 35nm, and the aluminum component is 0.25 undoped Al 0.25Ga0.75 N;
(B3) Setting the process conditions of 900 ℃ of temperature, 40Torr of pressure, 4000sccm of hydrogen flow, 4000sccm of ammonia flow and 90 mu mol/min of gallium source flow, and using a metal organic chemical vapor deposition technology to extend GaN material on the first barrier layer 4 to form a second channel layer 5 with the thickness of 70 nm;
(B4) The second barrier layer 6 was formed using a metal organic chemical vapor deposition technique with an epitaxial thickness S 2 of 20nm on the second channel layer 5, undoped Al 0.3Ga0.7 N with an aluminum composition of 0.3, under process conditions of 980 ℃ and 45Torr, a hydrogen flow of 4200sccm, an ammonia flow of 4200sccm, a gallium source flow of 39 μmol/min, and an aluminum source flow of 5 μmol/min.
Step c. Mesa 7 is made as shown in fig. 4c.
Setting etching process conditions of Cl 2 flow of 15sccm, pressure of 10mTorr and power of 100W, firstly manufacturing a mask on the second barrier layer 6, respectively etching two sides of the second barrier layer 6, the second channel layer 5, the first barrier layer 4 and the first channel layer 3 by using a reactive ion etching technology by using the mask, and etching until the upper surfaces of the transition layers 2 are etched to form a left mesa 7 and a right mesa 7.
Step d. Deposition forms left drain 8 and right drain 9 as shown in fig. 4d.
Setting vacuum degree smaller than 1.8X10 -3 Pa, power 380W, evaporation rate smaller thanUsing the mask produced in step C, depositing a plurality of layers of metals respectively on the left and right mesas 7 using electron beam evaporation technique, the plurality of layers of metals being Ta, ni, au, each having a thickness of 0.016 μm/0.177 μm/0.058 μm, and performing rapid thermal annealing in an atmosphere of N 2 at 870 ℃ for 30s to form left and right drains 8 and 9, both of which are in ohmic contact with the contacted semiconductor.
Step E. N + region 10 is fabricated as shown in FIG. 4e.
The process conditions of ion implantation are that the implanted N-type impurity is arsenic ion, the implantation energy is 19keV, the implantation dosage is 4 multiplied by 10 22cm-2, masks are manufactured on the second barrier layer 6, the left drain electrode 8 and the right drain electrode 9 for the second time, and the masks are used for ion implantation at the middle position of the second barrier layer 6 to form an N + region 10.
Step f. Etching forms the recess 11, fig. 4f.
The etching process conditions are that the Cl 2 flow is 15sccm, the pressure is 10mTorr, the power is 100W, masks are manufactured on the second barrier layer 6, the left drain electrode 8, the right drain electrode 9 and the N + region 10 for the third time, and the masks are used for respectively etching the middle part of the N + region 10, the second channel layer 5, the first barrier layer 4 and the first channel layer 3 by using a reactive ion etching technology, wherein the etching depth is 150nm, so that the groove 11 is formed.
Step g. Anodes 12 are made in grooves 11, fig. 4g.
The technological conditions adopted for depositing metal are that the vacuum degree is less than 1.8X10 -3 Pa, the power is 200W, and the evaporation rate is less thanUsing the mask produced in step F, a multilayer metal is deposited inside the recess 11 using electron beam evaporation technique, wherein the deposited metal is a Ni/Au metal combination, i.e. Ni in the lower layer and Au in the upper layer, with a thickness of 0.015 μm/0.015 μm, respectively, forming an anode 12, the anode 12 being in schottky contact with the contacted semiconductor material.
Setting vacuum degree smaller than 1.8X10 -3 Pa, power 400W, evaporation rate smaller thanUsing the mask produced in step F again, a multilayer of metals Ta, ni, au, respectively 0.018 μm/0.135 μm/0.046 μm thick, was deposited on top of the anode 12 using electron beam evaporation techniques to form a source 13, which source 13 forms an ohmic contact with the contacted semiconductor, as shown in fig. 4h.
Step i. Left P-block 14 and right P-block 15 are fabricated as shown in fig. 4i.
(I1) Setting a target material of copper with the purity of 99.999%, high-purity argon as sputtering gas, high-purity oxygen with the same purity as reaction gas, wherein the vacuum degree of a reaction chamber before sputtering is 2.0X10 -4 Pa, the flow rate of Ar gas is kept to be 20sccm, the flow rate of O 2 is kept to be 10sccm, the air pressure of a deposition chamber is 0.5Pa, the radio frequency power is 35W, the substrate temperature is 200 ℃, and using a magnetron sputtering technology, forming a P-type CuO layer on a second barrier layer 6, a left drain electrode 8, a right drain electrode 9, an N + region 10 and a source electrode 13 by using a CuO material with the epitaxial doping concentration of 5X 10 20cm-3 and the thickness of 120 nm;
(I2) Setting an etching process condition that the Cl 2 flow is 15sccm, the pressure is 10mTorr, and the power is 120W, manufacturing a mask on the P-type CuO layer for the fourth time, and etching the P-type CuO layer by using a reactive ion etching technology by using the mask until the upper surface of the second barrier layer 6 is etched, so as to respectively form a left P-type block 14 and a right P-type block 15.
Step j. Left gate 16 and right gate 17 are fabricated as shown in fig. 4j.
The sputtering process conditions are set to be that the air pressure is about 0.1Pa, the flow rate of Ar is 8sccm, the temperature of the substrate is fixed at 200 ℃, the target radio frequency power is 150W, masks are manufactured on the second barrier layer 6, the left drain electrode 8, the right drain electrode 9, the N + area 10, the source electrode 13, the left P-type block 14 and the right P-type block 15 for the fifth time, the masks are used for respectively depositing metal combinations with Ta as the lower layer and Ni as the upper layer on the left P-type block 14 and the right P-type block 15 by using a sputtering technology, the thicknesses of the metal combinations are respectively 0.021 mu m/0.28 mu m, and the left grid electrode 16 and the right grid electrode 17 are respectively formed to finish the manufacturing of the whole device.
The effect of the present invention can be further illustrated by the following test results.
The result of conducting the device of the second embodiment of the invention is shown in fig. 5, wherein fig. 5 (a) is a forward conducting test result, and fig. 5 (b) is a reverse conducting test result, and as can be seen from fig. 5, the device of the invention has excellent bidirectional conducting characteristics;
The blocking test is carried out on the device in the second embodiment of the invention, and as shown in fig. 6, the device can realize bidirectional blocking, and the forward and reverse break-state breakdown voltages are 861V and-822V respectively, which shows that the device has excellent bidirectional conduction and bidirectional blocking characteristics.
The above description is only three specific embodiments of the invention and does not constitute a limitation of the invention, it will be apparent to those skilled in the art that various modifications and changes in form and details can be made according to the method of the invention without departing from the principle and scope of the invention, but these modifications and changes based on the invention remain within the scope of the claims of the invention.
Claims (10)
1. The common source type power device comprises a substrate (1), a transition layer (2), a second channel layer (5) and a second barrier layer (6) from bottom to top, and is characterized in that:
a first channel layer (3) and a first barrier layer (4) are inserted between the transition layer (2) and the second channel layer (5), and the first barrier layer (4) is positioned at the upper part of the first channel layer (3);
the first channel layer (3), the first barrier layer (4), the second channel layer (5) and the second barrier layer (6) are respectively provided with a table top (7) at the left side and the right side, the lower ends of the two table tops (7) are respectively positioned at the upper part of the transition layer (2), and the table tops (7) at the left side and the right side are respectively provided with a left drain electrode (8) and a right drain electrode (9);
an N+ region (10) is arranged in the middle of the second channel layer (5) and the second barrier layer (6), and the lower side of the N+ region (10) is positioned in the second channel layer (5);
A groove (11) is formed between the upper part of the N+ region (10) and the interior of the first channel layer (3), a source electrode (13) and an anode (12) are respectively arranged on the upper part and the lower part of the interior of the groove, and the contact surfaces of the two electrodes are positioned on the lower side of the N+ region (10);
a left P-type block (14) and a left grid electrode (16) are arranged on the second barrier layer (6) between the left drain electrode (8) and the source electrode (13), and a right P-type block (15) and a right grid electrode (17) are arranged on the second barrier layer (6) between the right drain electrode (9) and the source electrode (13).
2. The device according to claim 1, characterized in that the thickness S 1 of the first barrier layer (4) is 2-60 nm and the thickness S 2 of the second barrier layer (6) is 2-60 nm.
3. The device according to claim 1, characterized in that the n+ region (10) is an N-type heavily doped region with an implant dose greater than 1 x 10 20cm-2.
4. A device as claimed in claim 1, characterized in that the recess (11) is located on the underside inside the first channel layer (3) and that the recess (11) is located at a distance of at least 5nm from the upper surface of the first channel layer (3).
5. A device according to claim 1, characterized in that the distance t between the upper side of the anode (12) and the lower side of the n+ region (10) is >0nm and is not greater than the sum of the thicknesses of the first barrier layer (4) and the second channel layer (5).
6. The device of claim 1, wherein the thickness h of the left P-type block (14) and the right P-type block (15) is 10-500 nm, and the doping concentration is 1 x 10 16～5×1020cm-3.
7. The device of claim 1, wherein:
the left grid electrode (16) is positioned at the upper part of the left P-type block (14);
The right grid electrode (17) is positioned at the upper part of the right P-type block (15).
8. The device of claim 1, wherein:
the left drain electrode (8) and the right drain electrode (9) are combined by adopting the same metal, ohmic contact is formed between the semiconductor and the contact semiconductor;
the anode (12) adopts a plurality of layers of metals, the bottommost metal is a high work function metal, and Schottky contact is formed between the anode (12) and the contacted semiconductor;
Ohmic contact is formed between the source electrode (13) and the contacted semiconductor.
9. A method of making a common source power device comprising the steps of:
a) A GaN-based wide band gap semiconductor material is epitaxially grown on a substrate (1) to form a transition layer (2) with the thickness of 1-50 mu m;
b) Manufacturing a channel layer and a barrier layer:
b1 Epitaxial GaN material on the transition layer (2) to form a first channel layer (3) with the thickness of 10-200 nm;
B2 A GaN-based wide bandgap semiconductor material is epitaxially grown on the first channel layer (3) to form a first barrier layer (4) with the thickness S 1 of 2-60 nm;
B3 A GaN material is epitaxially grown on the first barrier layer (4) to form a second channel layer (5) with the thickness of 10-200 nm;
b4 A GaN-based wide bandgap semiconductor material is epitaxially grown on the second channel layer (5) to form a second barrier layer (6) with the thickness S 2 of 2-60 nm;
C) Firstly manufacturing a mask on the second barrier layer (6), and respectively etching two sides of the second barrier layer (6), the second channel layer (5), the first barrier layer (4) and the first channel layer (3) by using the mask until the upper surface of the transition layer (2) is etched to form a left mesa (7) and a right mesa (7);
d) Depositing multiple layers of metals on the left and right table tops (7) respectively by utilizing the mask manufactured in the step C), and performing rapid thermal annealing to form a left drain electrode (8) and a right drain electrode (9), wherein ohmic contact is formed between the two drain electrodes and the contacted semiconductor;
E) Manufacturing masks on the second barrier layer (6), the left drain electrode (8) and the right drain electrode (9) for the second time, and performing ion implantation on the middle positions of the second channel layer (5) and the second barrier layer (6) by using the masks to form an N+ region (10), wherein the first channel layer (3) is ensured not to be damaged when the implantation dosage and the implantation energy are determined;
F) Manufacturing masks on the second barrier layer (6), the left drain electrode (8), the right drain electrode (9) and the N+ region (10) for the third time, and respectively etching the middle part of the N+ region (10), the second channel layer (5), the first barrier layer (4) and the first channel layer (3) by using the masks to form grooves (11);
G) Depositing a plurality of layers of metal inside the groove (11) by utilizing the mask manufactured in the step F) to form an anode (12), wherein the anode (12) is in schottky contact with the semiconductor material contacted with the anode, and then depositing a metal combination on the upper part of the anode (12) to form a source electrode (13), wherein ohmic contact is formed between the source electrode (13) and the second channel layer (5) and between the source electrode and the first barrier layer (4);
H) Forming a P-type layer by extending P-type semiconductor materials on the second barrier layer (6), the left drain electrode (8), the right drain electrode (9), the N+ region (10) and the source electrode (13), and then manufacturing a mask on the P-type layer for the fourth time, and etching the P-type layer by using the mask to form a left P-type block (14) and a right P-type block (15);
I) And fifth manufacturing masks on the second barrier layer (6), the left drain electrode (8), the right drain electrode (9), the N+ region (10), the source electrode (13), the left P-type block (14) and the right P-type block (15), and depositing multiple layers of metals on the left P-type block (14) and the right P-type block (15) by utilizing the masks to respectively form a left grid electrode (16) and a right grid electrode (17) so as to finish the manufacturing of the whole device.
10. The method according to claim 9, wherein:
the epitaxy technology used in the steps A), B) and H) comprises a metal organic chemical vapor deposition technology, a magnetron sputtering technology and a molecular beam epitaxy technology;
the metal deposition process used in the steps D), G) and I) comprises an electron beam evaporation process and a sputtering process.
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