CN114975107A - A method of forming a semiconductor pattern and a method of manufacturing a semiconductor device - Google Patents

Abstract

Specifically, the present disclosure may provide a method of forming a semiconductor pattern and a method of manufacturing a semiconductor device. The method of forming a semiconductor pattern may include, but is not limited to, the steps of: providing a semiconductor substrate, and forming a first film layer on the semiconductor substrate. A sacrificial layer is formed on the first film layer, and a first pattern is formed on the sacrificial layer. A second pattern is formed in the sacrificial layer, wherein the second pattern and the first pattern form a target pattern, and then the target pattern is transferred to the first film layer. The manufacturing method of the semiconductor device includes, but is not limited to, the method of forming a semiconductor pattern of the present disclosure. The present disclosure can generate a new pattern on the basis of the generated pattern, and the generated pattern and the new pattern together form a final pattern, so as to solve the problem that the existing pitch multiplication technology cannot be applied to some special patterns. The present disclosure is easy to realize the technical effect of multiplying the pitch, can better form complex semiconductor patterns with small pitches, and has a wide application range.

Description

A method of forming a semiconductor pattern and a method of manufacturing a semiconductor device

technical field

The present disclosure relates to the technical field of semiconductor device processing, and more particularly, the present disclosure can provide a method for forming a semiconductor pattern and a method for manufacturing a semiconductor device.

Background technique

As the integration of semiconductor devices becomes higher and higher, the size of the semiconductor patterns becomes smaller and smaller, and the pitch of the semiconductor patterns becomes smaller and smaller. In order to cope with the problem of smaller pitches of semiconductor patterns, resolution-enhancing solutions such as double lithography (LELE, Lithography etch lithography etch) have emerged. The double lithography technology can specifically split the design layout into two masks, and use two lithography to transfer the pattern to the substrate; double lithography technology is widely used in 22nm, 20nm and even 14nm technology nodes. However, in the process of semiconductor device processing, it is found that the existing dual lithography technology still has great limitations for the formation of complex semiconductor patterns with small pitches.

SUMMARY OF THE INVENTION

In order to solve the problem that it is difficult to form complex semiconductor patterns with small pitches in the prior art, the present disclosure can provide a method for forming semiconductor patterns and a method for manufacturing a semiconductor device, so as to form desired semiconductor patterns according to actual conditions.

To achieve the above technical purpose, the present disclosure can provide a method for forming a semiconductor pattern, the method including but not limited to at least one of the following steps. A semiconductor substrate is provided, and a first film layer is formed on the semiconductor substrate. A sacrificial layer is formed on the first film layer, and a first pattern is formed on the sacrificial layer. A second pattern is formed in the sacrificial layer based on the first pattern, wherein the second pattern and the first pattern form a target pattern. Specifically, the present disclosure forms the second pattern based on spacers formed in preset voids, the spacers including a first spacer layer and a second spacer layer. The target pattern can then be transferred to the first film layer.

To achieve the above technical purpose, the present disclosure can also provide a method for manufacturing a semiconductor device. The manufacturing method of the semiconductor device may include, but is not limited to, the method of forming a semiconductor pattern in any embodiment of the present disclosure.

The beneficial effects of the present disclosure are:

Compared with the prior art, the technical solution provided by the present disclosure can generate a new pattern on the basis of the generated pattern, and the generated pattern and the new pattern together form the final pattern, so as to solve the problem of the existing pitch multiplication technology. Applicable to some special graphics problems. The present disclosure can more easily realize the technical effect of pitch doubling, so as to better form complex semiconductor patterns with small pitches. The technical solution provided by the present disclosure can be designed and used in the stage of layout drawing of an integrated circuit, and has outstanding advantages such as wide application range and easy realization in technology.

Description of drawings

FIG. 1 shows a schematic cross-sectional structure diagram of a device after a first pattern is formed on a sacrificial layer in one or more embodiments of the present disclosure.

FIG. 2 shows a schematic cross-sectional structure diagram of a device after depositing a second film layer in one or more embodiments of the present disclosure.

FIG. 3 shows a schematic cross-sectional structure diagram of a device after coating a third film layer in one or more embodiments of the present disclosure.

FIG. 4 shows a schematic cross-sectional structure diagram of the device after etching the third film layer in one or more embodiments of the present disclosure.

FIG. 5 shows a schematic cross-sectional structure diagram of a device in which spacers are formed after etching the second film layer in one or more embodiments of the present disclosure.

FIG. 6 is a schematic diagram illustrating the cross-sectional structure of the device after the target pattern is formed on the first film layer in one or more embodiments of the present disclosure.

7 illustrates a schematic diagram of forming a first pattern using a double lithography (LELE) method and forming a second pattern using a spacer self-alignment method in one or more embodiments of the present disclosure.

FIG. 8 is a schematic diagram illustrating the relationship among preset gap widths, spacer widths, second spacer layer thicknesses, and pitches of the first patterns in an integrated circuit layout design in one or more embodiments of the present disclosure.

In the figure,

100. A semiconductor substrate.

200. A first film layer.

300. A sacrificial layer.

400, the second film layer; 401, the groove; 402, the second spacer layer.

500, the third film layer; 501, the first spacer layer.

Detailed ways

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not to scale, some details have been exaggerated for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships are only exemplary, and in practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art should Regions/layers with different shapes, sizes, relative positions can be additionally designed as desired.

In the context of this disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. element. In addition, if a layer/element is "on" another layer/element in one orientation, then when the orientation is reversed, the layer/element can be "under" the other layer/element.

As shown in FIGS. 1 to 8 , one or more embodiments of the present disclosure can provide a method of forming a semiconductor pattern, which method may include, but is not limited to, a multi-patterning method. More specifically, the method may include, but is not limited to, at least one of the following steps.

As shown in FIG. 1 , a semiconductor substrate 100 is first provided, and at least one first film layer 200 is formed on the semiconductor substrate 100 . Next, a sacrificial layer 300 is formed on the first film layer 200 , and a first pattern can be formed on the sacrificial layer 300 ; the present disclosure can also form one or more preset voids while forming the first pattern on the sacrificial layer 300 . The semiconductor substrate 100 involved in the present disclosure may be, for example, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon germanium substrate, a III-V compound semiconductor substrate substrates or epitaxial thin film substrates obtained by performing selective epitaxial growth (SEG), etc. The first film layer 200 involved in the present disclosure may be, for example, a polysilicon film or a carbon film or the like. The sacrificial layer 300 may be, for example, a hard mask or the like. It should be understood that the sacrificial layer 300 involved in the present disclosure is a film layer that needs to be removed after the target pattern (ie, the final pattern) is formed.

As shown in FIG. 7 , forming the first pattern on the sacrificial layer 300 during the implementation of the present disclosure includes: forming the first pattern on the sacrificial layer 300 by adopting a double photolithography (LELE) process. Wherein, the double lithography may include: forming a first partial pattern through the first lithography and etching, and forming a second partial pattern through the second lithography and etching, the first partial pattern and the second partial pattern together constitute the requirements of the present disclosure The first pattern formed. The specific implementation details of the dual lithography process can be selected from conventional technologies, which will not be repeated in the embodiments of the present disclosure. It is understandable that, in some embodiments of the present disclosure, a triple lithography (LELELE) process or other achievable methods may also be used to process the first pattern on the sacrificial layer 300 , which can be realized by those skilled in the art.

As shown in FIG. 2 , a second film layer 400 is then deposited on the first film layer 200 , and the second film layer 400 covers the sacrificial layer 300 . In the process of depositing the material of the second film layer, based on one or more preset voids that can be formed in the previous process, there are grooves 401 on the second film layer 400 . The groove 401 is formed at a predetermined space, and the groove 401 disposed at the predetermined space has a certain depth and the bottom surface and the side surface are both the second film layer 400 . The second film layer 400 involved in the present disclosure may be, for example, a silicon oxide film such as a silicon oxide film or a silicon nitride film, or a silicon nitride film.

As shown in FIG. 3 , a third film layer 500 is coated on the second film layer 400 , and the upper surface of the third film layer 500 may be relatively flat. The third film layer 500 in the present disclosure may be, for example, SOH (Spin-on Hardmask, spin-on hardmask) or photoresist.

As shown in FIG. 4 , after the third film layer 500 is etched, the second film layer 400 is exposed, so as to use the third film layer 500 remaining in the groove 401 on the second film layer 400 to form the first spacer layer of the present disclosure 501. More specifically, the present disclosure can realize the formation of the first spacer layer 501 in the preset gap through dry etch back. During the dry etchback process, the present disclosure can etch the third film layer 500 toward the substrate until the first spacer layer 501 is formed in the groove 401 .

As shown in FIG. 5 , after etching the second film layer 400 , the first film layer 200 is exposed, so as to form a second spacer layer 402 between the first spacer layer 501 and the first film layer 200 . The present disclosure uses the first spacer layer 501 as a mask to etch the second film layer 400 , and the second spacer layer 402 may be formed between the first spacer layer 501 and the first film layer 200 by dry etching. Therefore, the present disclosure can form a spacer including the first spacer layer 501 and the second spacer layer 402, and it can be seen that the spacer and the sacrificial layer 300 can be used together to form the second pattern. Specifically, the present disclosure forms spacers in preset voids in the sacrificial layer 300 , and the spacers are formed on the first film layer 200 . The present disclosure realizes that the second pattern is formed in the sacrificial layer 300 based on the first pattern, so that a complex semiconductor pattern with a smaller pitch can be obtained. It can be seen that the present disclosure can generate a second pattern based on the first pattern, wherein the second pattern and the first pattern together form a target pattern (ie, a final pattern).

It is understandable that the second pattern formed based on the spacer (Spacer) in the solution of the present disclosure is a self-aligned (Self-aligned pattern) pattern, that is, the present disclosure can utilize the generated pattern to generate the self-aligned pattern.

As shown in FIG. 6 , the target pattern is transferred onto the first film layer 200 . More specifically, on the basis of the structure shown in FIG. 5 , the present disclosure performs dry etching on the first film layer 200 by using the sacrificial layer 300 with the target pattern and the spacer as a mask, and the first film layer 200 is dry-etched on the first film layer 200 The target pattern is formed, so as to realize the transfer of the semiconductor pattern, thereby achieving the technical purpose of the present disclosure. It can be understood that the present disclosure can expose the semiconductor substrate 100 when the first film layer 200 is etched, and remove the sacrificial layer 300 and the spacer including the first spacer layer 501 and the second spacer layer 402 after the etching is completed , the structure shown in Figure 6 is obtained. The target pattern formed by the present disclosure can be either a regular pattern repeated according to a certain rule, or an irregular pattern randomly arranged according to actual needs. It can be seen that the technical solution provided by the present disclosure has a wide application range.

In some embodiments of the present disclosure, target patterns may be formed on the semiconductor substrate 100 . Specifically, after transferring the target pattern to the first film layer 200 , the method further includes: transferring the target pattern on the first film layer 200 to the semiconductor substrate 100 . In a specific implementation process, the present disclosure can use the first film layer 200 as a mask to etch the semiconductor substrate 100 . After the etching is completed, a target pattern is formed on the semiconductor substrate 100 .

As shown in FIG. 8 , and in combination with FIG. 7 and FIG. 6 , the present disclosure may use a to represent the preset gap width (ie, pattern forming space), and b to represent the spacer width (ie, the width of the self-aligned pattern, Width of self-aligned pattern), c represents the pitch in the first pattern (that is, pattern-forming prohibited space), and t represents the thickness of the second spacer layer (that is, the thickness of the deposition film forming the spacer, Thickness of deposition film ).

More specifically, using the integrated circuit layout design rule (Layout design rule) of the technical solution of the present disclosure:

The preset void width a is greater than or equal to the sum of the spacer width b and twice the thickness t of the second spacer layer, that is, a≥b+2t; the spacing c in the first pattern is less than twice the thickness t of the second spacer layer, That is, c<2t.

Based on the above integrated circuit layout design rules, the present disclosure can determine the position of the preset void, the spacer width, and the deposited film thickness and other parameters during layout design, so the technical solution provided by the present disclosure is more reasonable in design and more reliable. powerful.

It can be understood that the present disclosure can also provide a method for manufacturing a semiconductor device, which may include, but is not limited to, the method for forming a semiconductor pattern in any embodiment of the present disclosure. The semiconductor devices involved in the present disclosure may include, but are not limited to, semiconductor memory devices, logic devices, and the like. The semiconductor memory device can be, for example, a dynamic random access memory (DRAM, Dynamic Random Access Memory). The dynamic random access memory can include a plurality of memory cells arranged in a matrix structure, each memory cell having a transistor and a memory cell controlled by the transistor. composed of semiconductor capacitors. The semiconductor devices provided based on the technical solutions of the present disclosure can be applied to electronic devices, which may include but are not limited to smart phones, computers, tablet computers, wearable devices, artificial intelligence devices, and mobile power supplies.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as those described above. Additionally, although the various embodiments have been described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

Embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims (10)

1. A method of forming a semiconductor pattern, comprising:

providing a semiconductor substrate, and forming a first film layer on the semiconductor substrate;

forming a sacrificial layer on the first membrane layer;

forming a first pattern on the sacrificial layer;

forming a second pattern within the sacrificial layer based on the first pattern; wherein the second pattern and the first pattern constitute a target pattern;

transferring the target pattern to the first film layer.

2. The method of forming a semiconductor pattern according to claim 1, wherein the forming a second pattern in the sacrificial layer based on the first pattern comprises:

forming spacers in the predetermined voids in the sacrificial layer, the spacers and the sacrificial layer being used to form the second pattern;

wherein the spacer is formed on the first film layer.

3. The method of forming a semiconductor pattern according to claim 2, wherein the forming spacers in the predetermined voids in the sacrificial layer comprises:

forming a first spacing layer in the preset gap;

forming a second spacer layer between the first spacer layer and the first film layer;

wherein the spacer comprises the first spacer layer and the second spacer layer.

4. The method of forming a semiconductor pattern according to claim 3, wherein the forming a first spacer layer in the predetermined gap comprises:

depositing a second film layer on the first film layer, wherein the second film layer is provided with a groove which is arranged at the preset gap;

and coating a third film layer on the second film layer, and exposing the second film layer after etching the third film layer so as to form a first spacing layer in the groove on the second film layer.

5. The method of forming a semiconductor pattern according to claim 4, wherein the forming a second spacer layer between the first spacer layer and the first film layer comprises:

and exposing the first film layer after etching the second film layer so as to form the second spacing layer between the first spacing layer and the first film layer.

6. The method for forming a semiconductor pattern according to any one of claims 3 to 5,

the predetermined void width is greater than or equal to the sum of the spacer width and twice the second spacer thickness.

7. The method for forming a semiconductor pattern according to any one of claims 3 to 5,

the pitch in the first pattern is less than twice the thickness of the second spacer layer.

8. The method of forming a semiconductor pattern according to claim 1, wherein the forming a first pattern on the sacrificial layer comprises:

and forming a first pattern on the sacrificial layer by adopting a double photoetching mode or a triple photoetching mode.

9. The method of forming a semiconductor pattern according to claim 1, further comprising, after the transferring the target pattern onto the first film layer:

transferring the target pattern on the first film layer to the semiconductor substrate.

10. A method for manufacturing a semiconductor device, comprising the method for forming a semiconductor pattern according to any one of claims 1 to 9.

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