CN114978134B - Switch buffer circuit, temperature compensation control circuit and voltage-controlled oscillator - Google Patents
Switch buffer circuit, temperature compensation control circuit and voltage-controlled oscillator Download PDFInfo
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- CN114978134B CN114978134B CN202210485340.2A CN202210485340A CN114978134B CN 114978134 B CN114978134 B CN 114978134B CN 202210485340 A CN202210485340 A CN 202210485340A CN 114978134 B CN114978134 B CN 114978134B
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- 239000000872 buffer Substances 0.000 title claims abstract description 152
- 230000003139 buffering effect Effects 0.000 claims abstract description 58
- 239000003990 capacitor Substances 0.000 claims description 58
- 230000008859 change Effects 0.000 claims description 34
- 230000000630 rising effect Effects 0.000 claims description 12
- 238000010586 diagram Methods 0.000 description 12
- 238000000034 method Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 238000007599 discharging Methods 0.000 description 6
- 230000006870 function Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/02—Details
- H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/002—Switching arrangements with several input- or output terminals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
- H03K17/284—Modifications for introducing a time delay before switching in field effect transistor switches
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention relates to a switch buffer circuit which can receive a plurality of control words for a plurality of switches to be buffered. Each control word in the plurality of control words is in one-to-one correspondence with each switch to be buffered of the plurality of switches to be buffered, and each control word in the plurality of control words is used for closing or opening a corresponding switch to be buffered in the plurality of switches to be buffered. And wherein the switch buffer circuit may comprise an select module for selecting one of the plurality of control words and providing the selected one to a buffer module described below, and a buffer module for buffering the one selected by the select module and outputting the buffered control word to a switch to be buffered corresponding to the control word. According to the invention, a temperature compensation control circuit and a voltage-controlled oscillator are also provided.
Description
Technical Field
The present invention relates to the field of electronic circuits, and in particular, to a switch buffer circuit, and a temperature compensation control circuit and a voltage controlled oscillator including the switch buffer circuit.
Background
The characteristic that the inductive current or the capacitive voltage cannot change suddenly can be utilized in the electronic circuit to design a buffer circuit for switch buffering, for example, an RC buffer circuit is often used in a microelectronic component to make a corresponding switch be closed or opened slowly so that the corresponding component is switched into the circuit slowly. The problem with using existing RC snubber circuits in microelectronic devices is that the snubber circuit is typically made up of larger resistors and capacitors to achieve the desired switch on time, which results in the snubber circuit occupying a larger area, and further occupying more area by using multiple pairs of resistors and capacitors for multiple switches, respectively.
For example, in a voltage-controlled oscillator of a phase-locked loop, in order to compensate for the oscillation frequency misalignment caused by temperature variation, a plurality of temperature compensation capacitors are often controlled to be connected as required to form a temperature compensation circuit, and if the temperature compensation capacitors are connected suddenly, an additional frequency process is generated, which easily causes a large overshoot, and the frequency of the phase-locked loop changes suddenly, so that it is desirable that the temperature compensation capacitors are connected slowly into the circuit. The use of the RC snubber circuit formed by a large resistor and a large capacitor in the temperature compensation circuit may cause an area occupied by the resistor and the capacitor to be too large, and the use of tens of sets of temperature capacitors (for example, 32 sets of temperature capacitors are commonly used) in the temperature compensation circuit of the voltage-controlled oscillator may result in the use of a plurality of RC snubber circuits, further increasing the area occupied by components.
Disclosure of Invention
In view of the above problems, the present invention is directed to provide a switching buffer circuit capable of significantly reducing the area of the buffer circuit while improving the switching buffer effect, and a temperature compensation control circuit and a voltage controlled oscillator including the same.
A switch buffer circuit of an aspect of the invention may receive a plurality of control words for a plurality of switches to be buffered. Each control word in the plurality of control words is in one-to-one correspondence with each switch to be buffered of the plurality of switches to be buffered, and each control word in the plurality of control words is used for closing or opening one corresponding switch to be buffered of the plurality of switches to be buffered. And wherein the switch buffer circuit may comprise an select module for selecting one of the plurality of control words and providing the selected one to a buffer module described below, and a buffer module for buffering the one selected by the select module and outputting the buffered control word to a switch to be buffered corresponding to the control word.
Optionally, the selecting module may include a first selection switch, a second selection switch, and a plurality of through switches. The first selection switch is used for selecting one control word in the plurality of control words. The second selection switch is used for selecting a switch to be buffered corresponding to the control word selected by the first selection switch. And each through switch in the plurality of through switches corresponds to each control word in the plurality of control words in a one-to-one manner, and is used for enabling the selection of the first selection switch and the second selection switch to be invalid so as to directly output a corresponding control word in the plurality of control words to a corresponding switch to be buffered.
Optionally, the first selection switch and the plurality of through switches may be configured to: the first selection switch selects a changed control word of the plurality of control words, and the through switches corresponding to the changed control word are disabled, while the through switches corresponding to the control words not selected by the first selection switch are enabled.
Optionally, after the buffering module completes the buffering of the control word, the pass-through switch corresponding to the buffered control word may be enabled.
Optionally, after the control word input end of the switch to be buffered corresponding to the changed control word also completes the corresponding control word change, after a predetermined time period elapses, the through switch corresponding to the buffered control word may be enabled.
Alternatively, the first selection switch and the second selection switch may take the form of single pole multiple position switches.
Alternatively, the switch to be buffered may be an active MOS transistor switch, and the control word is input to a gate of the active MOS transistor switch.
Optionally, the buffer module may include a current source and a buffer capacitor, the current source being configured to charge or discharge the buffer capacitor.
Optionally, the buffer module may further include a reset switch, and the reset switch is configured to reset the buffer capacitor.
Alternatively, the current source may include a first current source, a second current source, and the reset switch includes a second reset switch and a first reset switch, wherein the first current source and the first reset switch are connected between the first selection switch and the second selection switch, the second current source and the second reset switch are connected between the first selection switch and the second selection switch and are connected in parallel with the first current source and the first reset switch, the ground terminal is connected between the second current source and the second reset switch, and one end of the buffer capacitor is grounded and the other end is connected to the first selection switch and the second selection switch.
Alternatively, when the control word in which the rising edge change occurs among the plurality of control words is selected by the first selection switch, the second reset switch and the first current source may be enabled, and the first reset switch and the second current source may be disabled. And when the control word with the falling edge change in the plurality of control words is selected by the first selection switch, the first reset switch and the second current source can be enabled, and the second reset switch and the first current source can be disabled.
Another aspect of the present invention provides a temperature compensation control circuit, which may include a digital controller, a switch buffer circuit as any one of the previous, a plurality of switches to be buffered, and a plurality of temperature compensation capacitor banks corresponding to the plurality of switches to be buffered one by one. The digital controller outputs a plurality of control words to the switch buffer circuit according to a desired temperature compensation value, the switch buffer circuit receives the plurality of control words and outputs the plurality of control words processed by the switch buffer circuit to a plurality of switches to be buffered, and each switch to be buffered in the plurality of switches to be buffered enables or disables a corresponding temperature compensation capacitor group according to each corresponding control word in the received plurality of control words.
Yet another aspect of the invention provides a voltage controlled oscillator that may include a temperature compensated control circuit as previously described.
As described above, according to the switch buffer circuit of the present invention, the buffer module can be shared on a plurality of control word input lines, so that the occupied area of the switch buffer circuit is greatly reduced, and the buffer module can be further designed using a current source, which in turn further reduces the occupied area. Therefore, the open-loop buffer circuit can provide good switch buffering and simultaneously realize the effect of remarkably reducing the occupied area of the switch buffer circuit.
Drawings
FIG. 1 illustrates a block diagram of a switch buffer circuit 100 according to some embodiments of the invention;
fig. 2 shows a schematic circuit diagram of a switch buffer circuit 200 comprising an interface module according to an embodiment;
fig. 3 shows a schematic diagram of a switch buffer circuit 300 according to a certain embodiment of the invention;
FIG. 4A shows a schematic diagram of a switch buffer circuit 400 according to another embodiment of the invention;
FIG. 4B illustrates a rising edge buffering control timing diagram for the switch buffer circuit 400 of FIG. 4A according to an example;
FIG. 5 shows a schematic diagram of a temperature compensation control circuit 500 according to an embodiment of the invention.
Detailed Description
The following description is of some of the various embodiments of the invention and is intended to provide a basic understanding of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention.
For the purposes of brevity and explanation, the principles of the present invention are described herein with reference primarily to exemplary embodiments thereof. However, those skilled in the art will readily appreciate that the same principles are equally applicable to all types of switched buffer circuits and that these same principles can be implemented therein, and that any such variations do not depart from the true spirit and scope of this patent application.
Moreover, in the following description, reference is made to the accompanying drawings that illustrate certain exemplary embodiments. Electrical, mechanical, logical, and structural changes may be made to these embodiments without departing from the spirit and scope of the invention. In addition, while a feature of the invention may have been disclosed with respect to only one of several implementations/embodiments, such feature may be combined with one or more other features of the other implementations/embodiments as may be desired and/or advantageous for any given or identified function. The following description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims and their equivalents.
Words such as "comprising" and "comprises" mean that, in addition to having elements (modules) and steps which are directly and explicitly stated in the description and the claims, the technical solution of the invention does not exclude the case of having other elements (modules) and steps which are not directly or explicitly stated.
In this context, "control word" is intended to mean a control signal for the closing or opening of a switch, for example, in an active MOS transistor switch, a high level or a low level may be input at the gate of the switch to control the closing or opening of the switch. In some examples, the control word may be to control the switches by means of a digital control signal, e.g. a digital signal "1" for closing the switches and a digital signal "0" for opening the switches. It will be appreciated that the control word is generated on demand, for example, when it is desired to close or open several switches, a plurality of binary control signals 1 and 0 for closing or opening the several switches may be generated by an external device (e.g., an analog-to-digital converter). For convenience of description, the control word is explained hereinafter with binary control signals 1 and 0, but it is to be understood that the present invention is not limited to this one form of control word.
In this context, "switch to be buffered" is intended to mean a switch that needs to buffer a control word so that the switch achieves the effect of slowly closing or slowly opening. For example, in an example of using digital signals 1 and 0 as control words and using an active MOS transistor as a switch to be buffered, a rising edge time of 0 to 1 or a falling edge time of 1 to 0 may be made longer so that the gate of the active MOS transistor slowly rises to 1 or falls to 0.
Fig. 1 illustrates a block diagram of a switch buffer circuit 100 according to some embodiments of the invention.
As shown in fig. 1, the switch buffer circuit 100 receives n control words for n switches to be buffered, each control word in the n control words corresponds to one switch to be buffered of the n switches to be buffered, and each control word is used to close or open one switch to be buffered corresponding to the control word, for example, the 2 nd control word in 8-bit control words corresponds to the 2 nd switch to be buffered in 8 switches to be buffered. The switch buffer circuit 100 comprises an selecting module 120 for selecting one of the input n control words and providing the selected one to a buffer module 110 described below, and a buffer module 110 for buffering the selected one control word. For simplicity, the n control word inputs on the n input lines for the inputs of the n control words are denoted by din < n:1> in fig. 1, and the n outputs for the n control words to the n switches to be buffered after passing through the switch buffer circuit 100 are denoted by dout < n:1 >.
Specifically, a control word is selected at the selecting module 120 (for example, an input line of the control word is selected) and the buffering module 110 is connected to the input line of the control word, so that the control word needs to pass through the buffering module 110 first and then be input to the switch to be buffered corresponding to the control word. The buffering module 110 is configured to buffer the control word input thereto, so that the control word is slowly output from the corresponding dout < n:1> to the corresponding switch to be buffered, for example, when a certain switch to be buffered needs to be slowly closed, the input control word 1 may pass through the buffering module 110, so that the control word at the output end of the control word in dout < n:1> of the buffering module 110 is slowly raised from original 0 to 1. The buffering module 110 may use various forms of buffering circuits, for example, an existing RC buffering circuit may be used to buffer an input control word.
In this way, the selecting module 120 may input only the control word that needs to be buffered into the buffering module 110, and the other control words that do not need to be buffered are not accessed into the buffering module 110 (and are still directly connected to the corresponding switch to be buffered), so that the buffering module 110 can share the input control words. For example, when there are 4 switches to be buffered (n = 4), the original control word input is 0000,4 switches to be buffered are all in an open state, and if it is necessary to close one of the switches to be buffered, the control word 0100 may be input to close the 3 rd switch to be buffered (i.e., the switch to be buffered whose control word changes from 0 to 1), the selecting and connecting module 120 selects the control word changing from 0 to 1 at this time and connects the buffering module 110 to a corresponding one of the input lines din <4:1> of the control word, and the buffering module 110 is used to make the rising edge of 0 to 1 rise slowly (i.e., buffer the control word). If the next time the input control word is 0101, for example, the control word that produces a 0 to 1 change is 4 th, the selecting module 120 may instead select the input line of the control word and access the buffering module 110 into the input line of the control word. By analogy, the selecting and connecting module 110 can enable one buffering module 110 to be applied to buffering of multiple control words, so that sharing of the buffering module 110 is realized, and thus circuit occupation area caused by accessing multiple buffering modules 110 can be reduced.
Therefore, the selective connection module can be any circuit structure for realizing the selective connection of the module. As an example, fig. 2 shows a schematic circuit diagram of a switch buffer circuit 200 including an interface module according to an embodiment. As shown in fig. 2, the switch buffer circuit 200 includes a buffer module 210 and a selection module 220, and the selection module 220 includes a first selection switch 221, a second selection switch 222, and a plurality of through switches 223 (for convenience of description, n input lines are represented by one line < n:1> having one through switch 223 in fig. 2). The first selection switch 221 selects one of the plurality of control words, the second selection switch 222 selects one to-be-buffered switch corresponding to the selected one control word, and each through switch 223 of the plurality of through switches corresponds to each control word of the plurality of control words in a one-to-one correspondence, each through switch 223 being configured to disable the selection of the first selection switch 221 and the second selection switch 222 and directly output the control word to the corresponding one to-be-buffered switch.
Specifically, when a control word needs to be buffered, the first selection switch 221 and the second selection switch 222 may be controlled to select an input line on which the control word is located, and the buffer module 210 is connected to the input line, so that the control word is processed by the input buffer module 210, and is buffered by the buffer module 210 and output to a corresponding switch to be buffered. The activation of the corresponding through switch 223 on the input line accessed by the buffer module 210 may enable the control word to be directly input to the switch to be buffered through the through switch 223, bypassing the first selection switch 221, the buffer module 210 and the second selection switch 222, so that the activation of the through switch 223 disables the selection of the first selection switch 221 and the second selection switch 222. In this way, when the buffering module 210 is no longer needed for buffering, the corresponding pass-through switch 223 may be enabled to disable the access of the buffering module 210, and the buffering module 210 and the first and second selection switches 221 and 222 may be reused for control word buffering of other input lines, which realizes efficient sharing of the buffering module 210.
In some embodiments, the first selection switch 221 may be controlled to select a changed control word of the plurality of control words, and the pass switches 223 corresponding to the changed control word are disabled, while the pass switches 223 corresponding to control words not selected by the first selection switch 221 are enabled. When the control word changes, which means that the corresponding switch to be buffered may need to complete the process from closed to open or from open to closed, the first selection switch 221 may be controlled to select the changed control word, and the second selection switch 222 correspondingly selects the corresponding switch to be buffered, so that the changed control word may be accessed to the buffering module 210 for buffering. At the same time or before, the corresponding through switch 223 should be disabled in order to avoid the selection failure of the first selection switch 221 and the second selection switch 222. While the other unchanged control words are not input into the buffer module 210, their through switches 223 are enabled to enable them to be directly input into the corresponding switches to be buffered. The buffering module 210 buffers the changed control word to make the change of the control word slower, for example, if the time for the control word at the input end of the buffering module 210 to change from the original state to another state (for example, from a digital potential of 0 to 1) is T1, the time for the control word at the output end of the buffering module 210 to change is T2 which is greater than T1. Thus, the buffer module 210 buffers the control word input of the switch to be buffered, and can effectively prevent the problems of too large overshoot and the like caused by sudden change of the control word of the switch to be buffered.
In some embodiments, after the buffer module 210 completes the control word buffering, the pass switch 223 corresponding to the buffered control word is enabled. Specifically, if the buffering module 210 completes buffering and outputs the control word to the corresponding switch to be buffered, the input line of the control word no longer needs to be accessed to the buffering module 210. At this time, since the input control word of the switch to be buffered is already buffered, the through switch on the line on which the control word is located may be enabled, so that the control word bypasses the first selection switch 221, the buffering module 210, and the second selection switch 222 to be directly output to the corresponding switch to be buffered. For example, when an n = 8-bit control word is input, if the control word 00010000 changes to 00010001, the first selection switch 221 and the second selection switch 222 may be controlled to select the input line on which the 1 st control word (which has a control word change from 0 to 1) is located, while the through switch 223 of the input line is disabled, and the 1 st control word is input into the buffer module 210 for buffering and output to the corresponding switch to be buffered, so that the control word of the switch to be buffered may be slowly changed from 0 to 1. While the other 7 control words are unchanged, the 7 through switches of the 7 control words are always enabled so that they are still directly input to the corresponding 7 switches to be buffered. When the control word input of the switch to be buffered corresponding to the 8 th control word has changed from 0 to 1, the buffering module 210 may not be accessed any more (the control word corresponding to din and the control word corresponding to dout are both 1), at this time, the corresponding through switch 223 may be enabled first to enable the control word to be directly input to the switch to be buffered through the through switch, and then the buffering module 210 is unlocked to be accessed so that the through switch can be used for buffering other control words or the next time the control word changes.
In some embodiments, the through switch corresponding to the buffered control word may be enabled after a predetermined period of time has elapsed after the control word input of the switch to be buffered corresponding to the changed control word also completes the corresponding control word change. A predetermined time period is reserved, and more time margins can be provided to fully ensure that the control word input end of the switch to be buffered also completes corresponding control word change. For example, if the buffering module 210 extends the control word change time to 1ms (i.e. after at least 1ms, the corresponding switch to be buffered completes the input control word change), a reserved time of 10ms may be set, so that the system can ensure that the control word is sufficiently buffered and then the corresponding through switch 223 is enabled to bypass the line where the buffering module 210 is located.
In some embodiments, the first selection switch and the second selection switch may take the form of single pole multiple position switches. In this way, the first selection switch 221 and the second selection switch 222 can be made to select only the input line on which one control word is located at a time, to facilitate implementation of buffer module sharing in the case of using a single buffer module for a single control word.
In some embodiments, the switch to be buffered may be an active MOS transistor switch, and the control word is input to a gate of the active MOS transistor switch. In this way, the slow closing and opening of the switch to be buffered can be further realized by controlling the grid voltage potential of the active MOS tube switch.
Fig. 3 shows a schematic diagram of a switch buffer circuit 300 according to some embodiment of the invention, which shows one form of buffer module 310. The buffer module 310 includes a current source 311 and a buffer capacitor 312, the current source 311 is configured to charge or discharge the buffer capacitor 312. Corresponding to the control word change in the input buffer module 310, the internal circuit of the buffer module 310 may be designed such that the discharging and charging processes of the buffer capacitor 312 generate a blocking effect on the control word change, so that the control word cannot be abruptly changed and the change time is prolonged. For example, when the buffer module 310 is selected into the input line where the control word changes from 0 to 1, the buffer module 310 may simultaneously charge the buffer capacitor 312 by using the current source 311, so that the potential of the output end of the buffer module 310 changes more slowly, thereby achieving the buffering effect, and similarly, in the control word from 1 to 0, the buffer capacitor 312 may be simultaneously discharged, thereby achieving the buffering effect. In this embodiment, since the current source 311 can be designed very small, the use of the current source 311 allows the area of the buffer module 310 to be further reduced compared to a buffer circuit using a capacitive resistive RC form. For example, when a control word change time of 1ms needs to be implemented, a capacitor of 100pF is generally required to be matched with a large resistor of 10M Ω in the RC buffer circuit, and the change time T is achieved by using a form of charging and discharging the capacitor by a current source, the magnitude of current required to be supplied can be obtained according to the formula T = C × V/I (where V is the magnitude of rising voltage, I is the magnitude of current for charging and discharging the capacitor, and C is the magnitude of capacitance value of the capacitor), the change time of 100pF and 1ms only needs 100nA of current to be supplied, and such a small current allows a sufficiently small current source 311 design, so that the area of the whole buffer module 310 is greatly reduced compared with the RC buffer circuit.
Preferably, as shown in fig. 3, the buffer module 310 may further set a reset switch 313 for resetting the buffer capacitor 312. For example, before the buffer module 310 is selected into the input line on which the control word changing from 0 to 1 is located, the reset switch 313 may be enabled to set the voltage level at both ends of the buffer capacitor 312 to 0 (e.g., to ground both ends thereof at the same time), and then the current source 311 may be enabled to charge the buffer capacitor 312 at the same time when the buffer module 310 is selected into the input line on which the control word is located, as described above. The reset switch 313 can enable the buffer capacitor to erase the residual potential state in the last charging and discharging process as soon as possible, so that the buffer module 310 can better perform the buffering function.
Fig. 4A shows a schematic diagram of a switch buffer circuit 400 according to another embodiment of the invention, which shows a buffer module 410 in one specific form. For convenience of description, the selection module 420 is illustrated in the form of the first selection switch, the second selection switch, and the plurality of through switches in fig. 2 described above.
Specifically, as shown in fig. 4A, the buffer module 410 includes a first current source 412, a second current source 411, a buffer capacitor 415, a first reset switch 413, and a second reset switch 414, where the first current source 412 and the first reset switch 413 are connected between a first selection switch 421 and a second selection switch 422, the second current source 411 and the second reset switch 414 are connected between the first selection switch 421 and the second selection switch 422 and connected in parallel with the first current source 412 and the first reset switch 413, a ground terminal is connected between the second current source 411 and the second reset switch 414, one end of the buffer capacitor 415 is grounded, and the other end is connected to the first selection switch 421 and the second selection switch 422.
Further, the switch buffer circuit 400 may be configured to enable the second reset switch 414 and the first current source 412, and disable the first reset switch 413 and the second current source 411 when the control word (for example, from digital potential 0 to 1) with a rising edge change in the plurality of control words is selected by the first selection switch 421, so that the buffer capacitor 415 is reset to 0 first and then the rising edge change of the control word is buffered by charging the buffer capacitor 415; when a control word with a falling edge change occurs in the plurality of control words selected by the first selection switch 421, the first reset switch 413 and the second current source 411 are enabled, and the second reset switch 414 and the first current source 412 are disabled, so that the buffer capacitor 415 is reset to 1 first, and then the falling edge change of the control word is buffered by discharging the buffer capacitor 415.
In particular, it can be appreciated that the control word on each control word input line of switch buffer circuit 400 is always 0 or always 1, i.e., in a steady state, during the time period when no change in the control word has occurred at input terminals din < n:1> of switch buffer circuit 400 and during the time period after the change has been completed at output terminals dout < n:1 >. At this time, the first selection switch 421, the second selection switch 422, the first current source 412, the second current source 411, the first reset switch 413, and the second reset switch 414 are all in the disabled state, and only each through switch 423 is enabled. In the steady state, the last state erase of the buffer capacitor 415 (i.e. setting the buffer capacitor 415 to 0 or 1) may be completed, and then the buffering operation may be performed for the rising edge and the falling edge of the control word, as follows.
For a rising edge change of the control word:
1) In a stable state where the input of the control word is always 0 before changing, the second reset switch 414 is enabled, the two ends of the buffer capacitor 415 are grounded and 0 is connected to erase the previous state, and then the second reset switch 414 is disabled;
2) When the control word input at din changes from 0 to 1 (rising edge), the control word input line is selected and accessed to the buffer module 410 for the process of buffering the control word, which is as follows: enabling the first current source 412, and at the same time, disabling the corresponding through switch 423 and simultaneously enabling the first selection switch 421 and the second selection switch 422 to select the input line on which the control word is located, so that the buffer capacitor 415 is charged and thus the control word of the corresponding dout can be slowly raised from 0 to 1 at the same time;
3) When the corresponding dout control word rises to 1, the corresponding pass switch 423 may be enabled first, and then wait for a desired period of time (e.g., 10ms as described above), and then open the first selection switch 421 and the second selection switch 422 to unlock the buffer module 410 and take over by the pass switch 423.
For a falling edge change of the control word:
1) Enabling the first reset switch 413, setting the buffer capacitor 415 to 1, and then disabling the first reset switch 413;
2) When the control word input at din changes from 1 to 0 (falling edge), the control word input line is selected and accessed to the buffer module 410 for the process of buffering the control word, which is specifically as follows: enabling the second current source 411, while at the same time disabling the corresponding through switch 423 and simultaneously causing the first selection switch 421 and the second selection switch 422 to select the input line on which the control word is located, so that the buffer capacitor 415 is discharged and thus the control word of the corresponding dout may be simultaneously slowly dropped from 1 to 0;
3) When the corresponding dout control word falls to 0, the corresponding pass-through switch 423 may be enabled, and then wait for a desired period of time (e.g., 10ms as described above), and then open the first selection switch 421 and the second selection switch 422 to unlock the buffer module 410 and take over by the pass-through switch 423.
It will be appreciated that the erase step of setting the buffer capacitor 415 to 0 or 1 may be performed more than once after the control word of dout has completed the corresponding control word change.
In the buffer module 410, since the first current source 411 and the second current source 412 can be designed to be very small, the buffer module 410 of the present invention avoids the problem of the occupation area caused by the RC buffer circuit. Moreover, with the selecting module 420, a plurality of control word input lines can share one buffer module 410, which further reduces the occupied area of the switch buffer circuit.
Fig. 4B illustrates a rising edge buffering control timing diagram of the switch buffer circuit 400 of fig. 4A according to an example. In the figure din pre < n:1> represents the previous control word input state and din < n:1> represents the current control word input state. For example, when the control word is changed from din _ pre <4:1> =0000 to din <4:1> =0001 (i.e., it changes to potential 1 in the figure), the second reset switch 414 is first enabled so that both ends of the buffer capacitor 415 are grounded and 0 is juxtaposed, and the first reset switch 413 is always in the disabled state. Then, one of the potentials at the first selection switch 421 that changes according to the control word is the potential 1, the other potentials remain the potential 0, the potential of the corresponding through switch 423 is set to 0, and the potentials of the other through switches 423 remain the potential 1.
Fig. 5 shows a schematic diagram of a temperature compensation control circuit 500 according to an embodiment of the present invention, which may include a digital controller 510, a switch buffer circuit 520 as described in any of the embodiments, a plurality of switches to be buffered 530, and a plurality of temperature compensation capacitor sets in one-to-one correspondence with the plurality of switches to be buffered. For convenience of description, n control words output by the digital controller 510 on n output pins thereof and input to the switch buffer circuit 520 are denoted by din < n:1> in fig. 5, and n control words output from the switch buffer circuit 520 and input to corresponding n switches to be buffered 530, each for turning on or off a corresponding set of temperature compensation capacitors (fig. 5 is shown as a set of 2, but is not limited thereto), are denoted by dout < n:1 >.
In fig. 5, the digital controller 510 outputs a plurality of control words to the switch buffer circuit 520 according to a desired temperature compensation value, for example, when the system detects a certain temperature variation through a temperature sensor, the digital controller 510 may call the number of corresponding temperature compensation capacitors that need to be turned on or off and are pre-stored in the memory according to the temperature variation, and implement real-time temperature compensation by using the temperature compensation capacitors according to the temperature variation by generating the control words for controlling the switches of the temperature compensation capacitors (i.e., the switches to be buffered). Switch buffer circuit 520 receives the plurality of control words and outputs the plurality of control words processed by the switch buffer circuit (e.g., buffers control word changes on an input line of a switch to be buffered on which the control words change) to the plurality of switches to be buffered. Each to-be-buffered switch 530 of the plurality of to-be-buffered switches turns on or off the corresponding temperature compensation capacitor group according to each corresponding control word of the plurality of received control words, for example, when a control word changes, the switch buffer circuit 520 may make the change process slower, so that the corresponding to-be-buffered switch 530 slowly turns on or off the temperature compensation capacitor group to which it is connected.
In yet another aspect, the invention also includes a voltage controlled oscillator that may include a temperature compensated control circuit as previously described. The switch buffer circuit is introduced into the temperature compensation circuit of the voltage-controlled oscillator, so that the temperature compensation capacitor bank of the temperature compensation circuit can be slowly switched on or switched off, and the problems that additional frequency overshoots are generated due to sudden switching-on and switching-off of the temperature compensation capacitor bank and the overshoots are too large are solved. For example, in a phase-locked loop using a voltage-controlled oscillator, the invention effectively avoids the loss of lock and system errors caused by sudden switching on and off of the temperature compensation capacitor bank.
In summary, the switch buffer circuit, the temperature compensation control circuit and the voltage-controlled oscillator of the invention share one buffer function module among a plurality of switches to be buffered, thereby greatly reducing the occupied area of the buffer function module. And, can further use very small current source to carry on charging and discharging in the buffer function module, have further reduced the area occupied, still realize the effective buffering of the on-off control word at the same time.
The switch buffer circuit, the temperature compensation control circuit and the voltage-controlled oscillator of the invention are mainly described above. Although only a few embodiments of the present invention have been described in detail, those skilled in the art will appreciate that the present invention may be embodied in many other forms without departing from the spirit or scope thereof. Accordingly, the present examples and embodiments are to be considered as illustrative and not restrictive, and various modifications and substitutions may be made therein without departing from the spirit and scope of the present invention as defined by the appended claims.
Claims (6)
1. A switch buffer circuit, wherein the switch buffer circuit receives a plurality of control words for a plurality of switches to be buffered, wherein each of the plurality of control words corresponds one-to-one to each of the plurality of switches to be buffered, wherein each of the plurality of control words is used to close or open a corresponding one of the plurality of switches to be buffered, and wherein the switch buffer circuit comprises:
a selecting module for selecting one of the plurality of control words and providing the selected one to the following buffer module; and
a buffer module for buffering one control word selected by the selection module and outputting the buffered one control word to a switch to be buffered corresponding to the one control word,
wherein, the selection module includes:
a first selection switch for selecting one of the plurality of control words;
the second selection switch is used for selecting a switch to be buffered corresponding to the control word selected by the first selection switch; and
a plurality of pass-through switches, each of the plurality of pass-through switches corresponding to each of the plurality of control words in a one-to-one manner, each of the plurality of pass-through switches being configured to disable selection of the first selection switch and the second selection switch to directly output a corresponding one of the plurality of control words to a corresponding one of the switches to be buffered,
wherein the first selection switch and the plurality of pass switches are configured to: the first selection switch selects a changed control word of the plurality of control words, and the pass-through switches corresponding to the changed control word are disabled, while the pass-through switches corresponding to control words not selected by the first selection switch are enabled, and after the buffer module completes the buffering of the control words, the pass-through switches corresponding to the buffered control words are enabled,
and wherein the buffer module includes a current source configured to charge or discharge the buffer capacitor, a buffer capacitor, and a reset switch for resetting the buffer capacitor, the current source including a first current source and a second current source, the reset switch including a first reset switch and a second reset switch, wherein the first current source and the first reset switch are connected between the first selection switch and the second selection switch, the second current source and the second reset switch are connected between the first selection switch and the second selection switch and in parallel with the first current source and the first reset switch, a ground terminal is connected between the second current source and the second reset switch, the buffer capacitor has one end grounded and the other end connected to the first selection switch and the second selection switch, when the first selection switch selects a control word of a rising edge change among the plurality of control words, the second reset switch and the first current source are enabled, and the first reset switch and the second current source are disabled, when the first selection switch selects a falling edge change among the plurality of control words, the first reset switch and the second reset switch are disabled, and the current source is disabled.
2. The switch buffer circuit according to claim 1, wherein after a predetermined period of time has elapsed after the control word input of the switch to be buffered corresponding to the changed control word also has completed the corresponding control word change, the through switch corresponding to the buffered control word is enabled.
3. The switch snubber circuit of claim 1, wherein the first selection switch and the second selection switch are in the form of single-pole multiple-position switches.
4. The switch buffer circuit of claim 1, wherein the switch to be buffered is an active MOS transistor switch, and wherein the control word is input to a gate of the active MOS transistor switch.
5. A temperature compensation control circuit comprising a digital controller, a switch buffer circuit according to any one of claims 1 to 4, a plurality of switches to be buffered, a plurality of temperature compensation capacitor banks in one-to-one correspondence with the plurality of switches to be buffered, wherein:
the digital controller outputs a plurality of control words to the switch buffer circuit according to a desired temperature compensation value,
the switch buffer circuit receives the plurality of control words and outputs the plurality of control words processed by the switch buffer circuit to the plurality of switches to be buffered,
and each switch to be buffered in the plurality of switches to be buffered enables the corresponding temperature compensation capacitor group to be switched on or switched off according to each corresponding control word in the plurality of received control words.
6. A voltage controlled oscillator comprising the temperature compensated control circuit of claim 5.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210485340.2A CN114978134B (en) | 2022-05-06 | 2022-05-06 | Switch buffer circuit, temperature compensation control circuit and voltage-controlled oscillator |
| PCT/CN2022/092735 WO2023212976A1 (en) | 2022-05-06 | 2022-05-13 | Switch buffer circuit, temperature compensation control circuit, and voltage-controlled oscillator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210485340.2A CN114978134B (en) | 2022-05-06 | 2022-05-06 | Switch buffer circuit, temperature compensation control circuit and voltage-controlled oscillator |
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| Publication Number | Publication Date |
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| CN114978134A CN114978134A (en) | 2022-08-30 |
| CN114978134B true CN114978134B (en) | 2023-03-24 |
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| CN202210485340.2A Active CN114978134B (en) | 2022-05-06 | 2022-05-06 | Switch buffer circuit, temperature compensation control circuit and voltage-controlled oscillator |
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| CN (1) | CN114978134B (en) |
| WO (1) | WO2023212976A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110908270A (en) * | 2019-11-19 | 2020-03-24 | 复旦大学 | A constant slope digital time converter and its control method |
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| US7171601B2 (en) * | 2003-08-21 | 2007-01-30 | Credence Systems Corporation | Programmable jitter generator |
| US7463869B2 (en) * | 2004-06-29 | 2008-12-09 | Texas Instruments Incorporated | Low noise high isolation transmit buffer gain control mechanism |
| US7432773B2 (en) * | 2005-10-26 | 2008-10-07 | Microchip Technology Incorporated | Method, system and apparatus for reducing oscillator frequency spiking during oscillator frequency adjustment |
| US8004337B2 (en) * | 2007-01-30 | 2011-08-23 | Dolpan Audio, Llc | Digital delay circuit |
| CN102130668A (en) * | 2010-01-20 | 2011-07-20 | 上海华虹Nec电子有限公司 | Time-delay circuit |
| WO2017220133A1 (en) * | 2016-06-21 | 2017-12-28 | Telefonaktiebolaget Lm Ericsson (Publ) | Snubber circuit operable with a power converter |
| CN107517067B (en) * | 2017-09-01 | 2020-01-21 | 深圳市海能达通信有限公司 | Control circuit for reducing power consumption of interphone and interphone |
| US10459510B1 (en) * | 2019-01-17 | 2019-10-29 | Qualcomm Incorporated | Power chain with delay adaptive switches |
| CN109995365B (en) * | 2019-03-06 | 2020-09-01 | 杭州城芯科技有限公司 | Frequency synthesizer based on switched capacitor array temperature compensation circuit |
| CN110649922B (en) * | 2019-10-26 | 2022-12-20 | 复旦大学 | A digital clock frequency multiplier |
| US11431348B2 (en) * | 2020-02-21 | 2022-08-30 | Semiconductor Components Industries, Llc | Two-capacitor digital-to-analog converter |
| CN113422578B (en) * | 2021-07-07 | 2025-02-18 | 思澈科技(南京)有限公司 | A RC oscillator and temperature compensation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110908270A (en) * | 2019-11-19 | 2020-03-24 | 复旦大学 | A constant slope digital time converter and its control method |
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| WO2023212976A1 (en) | 2023-11-09 |
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