CN114978158A - Charge pump circuit for phase locked loop - Google Patents

Abstract

The invention provides a charge pump circuit for a phase-locked loop, which relates to the technical field of integrated circuit radio frequency circuits. The device includes: a bias circuit; a main charge pump core circuit for generating a low mismatch current, including a charging branch, a switching branch and a discharging branch, and the switching branch is respectively connected with the charging branch and the discharging branch; Wherein, the bias circuit is used to respectively generate the bias voltages required by the charging branch and the discharging branch; the charging branch includes a first operational amplifier and is provided with a first node and a second node, and the charging branch is used for adopting the first operational amplifier. An operational amplifier is clamped to make the potentials of the first node and the second node equal; the discharge branch includes a second operational amplifier and is provided with a third node and a fourth node, and the discharge branch is used for using the second operational amplifier to perform Clamp so that the potentials of the third node and the fourth node are equal. The present invention increases the voltage output range of the charge pump while ensuring a smaller mismatch current.

Description

Charge Pump Circuit for Phase Locked Loop

technical field

The present invention relates to the technical field of integrated circuit radio frequency circuits, and in particular, to a charge pump circuit for a phase-locked loop.

Background technique

With the advent of the era of 5G and the Internet of Things, the data transmission rate in modern communication systems continues to increase, and clock signals with low jitter and low spurious are becoming more and more important. In the process of modulation/demodulation in a wireless communication system, if the spurious of the clock signal is too large, it will cause crosstalk to adjacent channels, which will reduce the signal-to-noise ratio of the signal and deteriorate the communication quality.

In the current wireless communication system, the clock signal is usually provided by a phase-locked loop, and the charge pump phase-locked loop has become a classic phase-locked loop implementation due to its high performance and low power consumption. As shown in FIG. 1 , the existing charge pump phase locked loop includes a frequency discriminator 101 , a charge pump 102 , a low-pass filter 103 , a voltage controlled oscillator 104 , a frequency divider 105 and other modules. Among them, the charge pump 102 is a core module in the phase-locked loop of the charge pump, and its main function is to convert the error signal generated by the pre-stage frequency discriminator 101 into a charge and inject it into the low-pass filter 103, thereby controlling the voltage-controlled oscillator. 104 produces a signal of the correct frequency.

The charge pump presents four states of charge, discharge, dead zone prevention and high resistance during operation. When the phase-locked loop is in the locked state, the charge pump is in a dead-band and high-impedance state. In the anti-dead-zone state, the charge pump needs to have a small mismatch current, so as not to cause the charge pump to lose lock and cause output spurs; in the high-impedance state, the charge branch and discharge need to present a high impedance to the Vcont port characteristic.

Therefore, the performance of the charge pump has a significant impact on the overall performance of the phase-locked loop, including: (1) The mismatch of the upper and lower currents of the charge pump is the main source of spurs in the phase-locked loop; (2) The current size of the charge pump affects the The noise of the phase-locked loop; (3) the output voltage range of the charge pump determines the input voltage range of the voltage-controlled oscillator.

Therefore, how to realize a charge pump with low mismatch, low noise and wide output range is a technical problem to be solved urgently by those skilled in the art.

SUMMARY OF THE INVENTION

In view of the above problems, the present invention provides a charge pump circuit for a phase-locked loop, which increases the voltage output range of the charge pump while ensuring a smaller mismatch current.

The charge pump circuit for phase-locked loop provided by the present invention includes: a bias circuit 301; a main charge pump core circuit 302 for generating low mismatch current, including a charging branch 303, a switching branch 304 and a discharging branch circuit 305, the switching branch 304 is connected to the charging branch 303 and the discharging branch 305 respectively; wherein, the bias circuit 301 is used to generate the bias voltage required by the charging branch 303 and the discharging branch 305 respectively; the charging branch 303 It includes a first operational amplifier OP1, and is provided with a first node N1 and a second node N2, and the charging branch 303 is used for clamping with the first operational amplifier OP1, so that the potentials of the first node N1 and the second node N2 are equal; The discharge branch 305 includes a second operational amplifier OP2, and is provided with a third node N3 and a fourth node N4. The discharge branch 305 is used for clamping by using the second operational amplifier OP2, so that the third node N3 and the fourth node N4 are clamped. potentials are equal.

Further, the current of the first node N1 and the current of the third node N3 are equal.

Further, the bias circuit 301 includes a current source I1, a first resistor R1, a second resistor R2, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, and a fifth PMOS transistor MP5 and the sixth PMOS transistor MP6, wherein: the current source I1, the first resistor R1, the fifth NMOS transistor MN5 and the seventh NMOS transistor MN7 are sequentially connected in series between the power supply terminal VDD and the ground terminal GND, and the gate of the fifth NMOS transistor MN5 The pole is connected to the connection point of the current source I1 and the first resistor R1, the gate of the seventh NMOS transistor MN7 is connected to the connection point of the first resistor R1 and the fifth NMOS transistor MN5; the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the second resistor R2, the sixth NMOS transistor MN6 and the eighth NMOS transistor MN8 are sequentially connected in series between the power supply terminal VDD and the ground terminal GND, and the gate of the fifth PMOS transistor MP5 is connected to the second resistor R2 and the sixth PMOS transistor At the connection point of MP6, the gate of the sixth PMOS transistor MP6 is connected to the connection point of the second resistor R2 and the sixth NMOS transistor MN6, the gate of the sixth NMOS transistor MN6 is connected to the gate of the fifth NMOS transistor MN5, and the eighth NMOS transistor The gate of the transistor MN8 is connected to the gate of the seventh NMOS transistor MN7.

Further, the sixth NMOS transistor MN6 and the fifth NMOS transistor MN5 have the same size, and the eighth NMOS transistor MN8 and the seventh NMOS transistor MN7 have the same size.

Further, the charging branch 303 further includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3 and a fourth PMOS transistor MP4, wherein: the first PMOS transistor MP1 is connected in series with the power supply terminal VDD and the first operation Between the forward input terminals of the amplifier OP1, the second PMOS transistor MP2 is connected in series between the power supply terminal VDD and the reverse input terminal of the first operational amplifier OP1, the gate of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2 Commonly connected to the gate of the fifth PMOS transistor MP5 of the bias circuit 301; the third PMOS transistor MP3 is connected in series between the forward input terminal of the first operational amplifier OP1 and the discharge branch 305, and the gate of the third PMOS transistor MP3 is connected to the The gate of the sixth PMOS transistor MP6 of the bias circuit 301 is connected to the gate; The output terminals of the operational amplifier OP1 are connected; the first node N1 and the second node N2 are respectively set at the forward input terminal and the reverse input terminal of the first operational amplifier OP1.

Further, the size of the first PMOS transistor MP1 is twice the size of the fifth PMOS transistor MP5 of the bias circuit 301, and the size of the third PMOS transistor MP3 is twice the size of the sixth PMOS transistor MP6 of the bias circuit 301; The size of the second PMOS transistor MP2 is 10 times the size of the first PMOS transistor MP1, and the size of the fourth PMOS transistor MP4 is 10 times the size of the third PMOS transistor MP3.

Further, the discharge branch 305 further includes a first NMOS transistor MN1 , a second NMOS transistor MN2 , a third NMOS transistor MN3 and a fourth NMOS transistor MN4 , wherein: the first NMOS transistor MN1 is connected in series with the third NMOS transistor MN1 of the charging branch 303 Between the PMOS transistor MP3 and the forward input terminal of the second operational amplifier OP2, the second NMOS transistor MN2 is connected in series between the switching branch 304 and the reverse input terminal of the second operational amplifier OP2; the third NMOS transistor MN3 is connected in series Between the forward input terminal of the second operational amplifier OP2 and the ground terminal GND, the fourth NMOS transistor MN4 is connected in series between the reverse input terminal of the second operational amplifier OP2 and the ground terminal GND; the gate of the third NMOS transistor MN3 The gate of the fourth NMOS transistor MN4 is commonly connected to the gate of the seventh NMOS transistor MN7 of the bias circuit 301, the gate of the first NMOS transistor MN1 is connected to the gate of the fifth NMOS transistor MN5 of the bias circuit 301, and the second NMOS transistor The gate of MN2 is connected to the output terminal of the second operational amplifier OP2; the third node N3 and the fourth node N4 are respectively set at the forward input terminal and the reverse input terminal of the second operational amplifier OP2.

Further, the size of the first NMOS transistor MN1 is twice the size of the fifth NMOS transistor MN5, the size of the third NMOS transistor MN3 is twice the size of the seventh NMOS transistor MN7; the size of the second NMOS transistor MN2 is the size of the first NMOS transistor MN2 The size of the transistor MN1 is 10 times larger, and the size of the fourth NMOS transistor MN4 is 10 times the size of the third NMOS transistor MN3.

Further, the switch branch 304 includes a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, a fourth transmission gate TG4 and a third operational amplifier OP3, wherein: the first transmission gate TG1, the third transmission gate TG3 is serially connected between the charging branch 303 and the discharging branch 305 in sequence; the second transmission gate TG2 and the fourth transmission gate TG4 are serially connected between the charging branch 303 and the discharging branch 305 in sequence; The forward input terminal is connected to the connection point of the second transmission gate TG2 and the fourth transmission gate TG4; the reverse input terminal of the third operational amplifier OP3 is connected to the output terminal and connected to the first transmission gate TG1 and the third transmission gate At the connection point of TG3.

信号来驱动；第三传输门TG3的正控制端和第四传输门TG4的负控制端由鉴频鉴相器产生的DW信号来驱动，第三传输门TG3的负控制端和第四传输门TG4的正控制端由鉴频鉴相器产生的

信号来驱动；电荷泵电路的输出节点Vcont设置于第二传输门TG2与第四传输门TG4之间。Further, the positive control terminal of the first transmission gate TG1 and the negative control terminal of the second transmission gate TG2 are driven by the UP signal generated by the frequency discriminator, the negative control terminal of the first transmission gate TG1 and the second transmission gate TG2. The positive control terminal is generated by the frequency and phase detector

The positive control terminal of the third transmission gate TG3 and the negative control terminal of the fourth transmission gate TG4 are driven by the DW signal generated by the frequency discriminator, the negative control terminal of the third transmission gate TG3 and the fourth transmission gate The positive control terminal of TG4 is generated by the frequency discriminator

The output node Vcont of the charge pump circuit is set between the second transmission gate TG2 and the fourth transmission gate TG4.

Compared with the prior art, the charge pump circuit for the phase-locked loop provided by the present invention has at least the following beneficial effects:

(1) The present invention proposes a new charge pump circuit. While ensuring low current mismatch, the output voltage range of the charge pump can be increased by increasing the impedance of the charging branch and the discharging branch, which can greatly improve the charge pump. the output spurs, and increase the output frequency of the charge pump phase-locked loop under the same conditions.

(2) The present invention utilizes the characteristics of high gain and low input offset voltage of the operational amplifier to ensure accurate current copying and can greatly increase the output impedance of the circuit, thereby reducing the current mismatch and improving the voltage output range of the charge pump, and then Improve the frequency output range and spurious performance of the phase-locked loop under the same conditions.

Description of drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

Fig. 1 schematically shows the structure diagram of the charge pump phase-locked loop of the prior art;

FIG. 2 schematically shows a structural diagram of a charge pump circuit for a phase-locked loop according to an embodiment of the present invention.

[Description of reference numerals]

current technology:

101-frequency discriminator; 102-charge pump circuit; 103-low-pass filter; 104-voltage controlled oscillator; 105-frequency divider;

Embodiment of the present invention:

301-bias circuit; 302-main charge pump core circuit; 303-charging branch; 304-switching branch; 305-discharging branch;

I1-current source; R1-first resistor; R2-second resistor; MP1-first PMOS transistor; MP2-second PMOS transistor; MP3-third PMOS transistor; MP4-fourth PMOS transistor; MP5-fifth PMOS transistor Transistor; MP6-sixth PMOS transistor;

MN1-first NMOS transistor; MN2-second NMOS transistor; MN3-third NMOS transistor; MN4-fourth NMOS transistor; MN5-fifth NMOS transistor; MN6-sixth NMOS transistor; MN7-seventh NMOS transistor; MN8 - an eighth NMOS transistor;

OP1 - the first operational amplifier; OP2 - the second operational amplifier; OP3 - the third operational amplifier;

TG1-first transmission gate;TG2-second transmission gate;TG3-third transmission gate;TG4-fourth transmission gate;

N1-first node; N2-second node; N3-third node; N4-fourth node;

VDD-power terminal; GND-ground terminal; Vcont-output node.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings. Obviously, the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

The terminology used herein is for the purpose of describing specific embodiments only, and is not intended to limit the present invention. The terms "comprising", "comprising" and the like as used herein indicate the presence of stated features, steps, operations and/or components, but do not preclude the presence or addition of one or more other features, steps, operations or components.

In the present invention, unless otherwise expressly specified and limited, terms such as "installation", "connection", "connection" and "fixation" should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection, It can be a mechanical connection or an electrical connection or can communicate with each other; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal communication between the two elements or the interaction relationship between the two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

All terms (including technical and scientific terms) used herein have the meaning as commonly understood by one of ordinary skill in the art, unless otherwise defined. It should be noted that terms used herein should be construed to have meanings consistent with the context of the present specification and should not be construed in an idealized or overly rigid manner.

FIG. 1 schematically shows a structure diagram of a charge pump phase-locked loop in the prior art.

As shown in FIG. 1 , the existing charge pump phase locked loop includes a frequency discriminator 101 , a charge pump 102 , a low-pass filter 103 , a voltage controlled oscillator 104 , a frequency divider 105 and other modules. Wherein, the frequency discriminator 101 compares the reference clock and the signal of the voltage-controlled oscillator 104 after frequency division by the frequency divider 105, outputs the UP signal and the DW signal to control the charge pump 102, and the charge pump 102 passes through the switch circuit, The error signal output by the frequency discriminator 101 is converted into a current signal and injected into the low-pass filter 103 to generate a voltage signal for controlling the voltage-controlled oscillator 104, and a clock signal of the required frequency is formed through loop feedback. The main purpose of the present invention is to optimize the specific circuit structure of the charge pump 102 .

In view of this, embodiments of the present invention provide a charge pump circuit for a phase-locked loop, which has the characteristics of low mismatch and high output voltage range.

FIG. 2 schematically shows a structural diagram of a charge pump circuit according to an embodiment of the present invention.

As shown in FIG. 2 , an embodiment of the present invention provides a charge pump circuit for a phase-locked loop, including a bias circuit 301 and a main charge pump core circuit 302 . The main charge pump core circuit 302 is used to generate low mismatch current, and includes a charging branch 303 , a switching branch 304 and a discharging branch 305 , and the switching branch 304 is connected to the charging branch 303 and the discharging branch 305 respectively. The bias circuit 301 is used to generate the bias voltages required by the charging branch 303 and the discharging branch 305 respectively.

The charging branch 303 includes a first operational amplifier OP1, and is provided with a first node N1 and a second node N2. The charging branch 303 is used for clamping by using the first operational amplifier OP1, so that the first node N1 and the second node N2 are clamped. potentials are equal.

The discharge branch 305 includes a second operational amplifier OP2, and is provided with a third node N3 and a fourth node N4. The discharge branch 305 is used for clamping by using the second operational amplifier OP2, so that the third node N3 and the fourth node N4 are clamped. potentials are equal.

Therefore, the charging branch 303 uses the first operational amplifier OP1 for clamping, and controls the current of the second node N2 to accurately replicate the current of the first node N1. In addition, the setting of the first operational amplifier OP1 greatly improves the impedance of the charging branch 303 through the current negative feedback technology. Similarly, the discharge branch 305 uses the second operational amplifier OP2 for clamping, and controls the current of the fourth node N4 to accurately replicate the current of the third node N3. Moreover, the setting of the second operational amplifier OP2 greatly improves the impedance of the discharge branch 305 through the current negative feedback technology.

Further, the current of the first node N1 and the current of the third node N3 are equal. Therefore, the setting of the first operational amplifier OP1 and the second operational amplifier OP2 ensures that the current of the charging branch is equal to the current of the discharging branch, increases the impedance of the charging branch and the discharging branch, and reduces the voltage of the output node Vcont It affects the current of the charging branch and the discharging branch, thereby increasing the voltage output range of the charge pump.

According to the embodiment of the present invention, the first operational amplifier OP1 is added to the charging branch 303 to clamp the potentials of the first node N1 and the second node N2, and the second operational amplifier OP2 is added to the discharging branch 305 to clamp the potential of the third node N1 and the second node N2. The potentials of the node N3 and the fourth node N4 are clamped to suppress the mismatch between the charging current and the discharging current. While ensuring low mismatch current, the current negative feedback technology is used to increase the output impedance of the charging branch 303 and the discharging branch 305, reducing the influence of the output node Vcont voltage on the charging current and discharging current, and ensuring low loss. At the same time, the output voltage range of the charge pump is improved.

As shown in FIG. 2, specifically, the bias circuit 301 includes a current source I1, a first resistor R1, a second resistor R2, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, and an eighth NMOS transistor MN8, the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6.

The current source I1, the first resistor R1, the fifth NMOS transistor MN5 and the seventh NMOS transistor MN7 are serially connected between the power supply terminal VDD and the ground terminal GND in sequence, and the gate of the fifth NMOS transistor MN5 is connected to the current source I1 and the seventh NMOS transistor MN5. At the connection point of a resistor R1, the gate of the seventh NMOS transistor MN7 is connected to the connection point of the first resistor R1 and the fifth NMOS transistor MN5.

The fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the second resistor R2, the sixth NMOS transistor MN6 and the eighth NMOS transistor MN8 are sequentially connected in series between the power supply terminal VDD and the ground terminal GND, and the gate of the fifth PMOS transistor MP5 is connected to To the connection point of the second resistor R2 and the sixth PMOS transistor MP6, the gate of the sixth PMOS transistor MP6 is connected to the connection point of the second resistor R2 and the sixth NMOS transistor MN6, and the gate of the sixth NMOS transistor MN6 is connected to the fifth The gate of the NMOS transistor MN5 is connected to the gate, and the gate of the eighth NMOS transistor MN8 is connected to the gate of the seventh NMOS transistor MN7.

Further, the sixth NMOS transistor MN6 and the fifth NMOS transistor MN5 have the same size, and the eighth NMOS transistor MN8 and the seventh NMOS transistor MN7 have the same size.

Therefore, in the bias circuit 301, the first resistor R1, the fifth NMOS transistor MN5 and the seventh NMOS transistor MN7 constitute a self-biased low-voltage cascode circuit, which converts the current of the current source I1 into the discharge branch. The required bias voltage ensures that the current is accurately replicated without consuming excess current and at the same time increasing the voltage swing. Similarly, the second resistor R2, the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 also form a self-biased low-voltage cascode circuit, which ensures accurate current replication without consuming excess current and increases the voltage swing at the same time. width. In addition, NMOS transistors MN6 and MN8 are used to accurately replicate the current source current, so that R2 and MP5 and MP6 form a self-biased low-voltage cascode circuit and R1, MN5 and MN7 form a self-biased low-voltage cascode circuit with equal currents.

Continuing as shown in FIG. 2 , specifically, the charging branch 303 further includes a first PMOS transistor MP1 , a second PMOS transistor MP2 , a third PMOS transistor MP3 and a fourth PMOS transistor MP4 .

The first PMOS transistor MP1 is connected in series between the power supply terminal VDD and the forward input terminal of the first operational amplifier OP1, and the second PMOS transistor MP2 is connected in series between the power supply terminal VDD and the reverse input terminal of the first operational amplifier OP1. During this time, the gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2 are commonly connected to the gate of the fifth PMOS transistor MP5 of the bias circuit 301 .

The third PMOS transistor MP3 is connected in series between the forward input terminal of the first operational amplifier OP1 and the discharge branch 305 , and the gate of the third PMOS transistor MP3 is connected to the gate of the sixth PMOS transistor MP6 of the bias circuit 301 . The fourth PMOS transistor MP4 is connected in series between the inverting input end of the first operational amplifier OP1 and the switch branch 304 , and the gate of the fourth PMOS transistor MP4 is connected to the output end of the first operational amplifier OP1 .

The first node N1 and the second node N2 are respectively set at the forward input terminal and the reverse input terminal of the first operational amplifier OP1.

Therefore, in the charging branch 303, the biases of the first PMOS transistor MP1, the second PMOS transistor MP2 and the third PMOS transistor MP3 are all generated by the bias circuit 301, and the bias of the fourth PMOS transistor MP4 is generated by the first operation The output of amplifier OP1 is generated. MP1 and MP3 are used to initially amplify the current, and MP2, MP4, and OP1 are used to generate high-precision, high-impedance current sources.

Further, the size of the first PMOS transistor MP1 is twice the size of the fifth PMOS transistor MP5 of the bias circuit 301 , and the size of the third PMOS transistor MP3 is twice the size of the sixth PMOS transistor MP6 of the bias circuit 301 . The size of the second PMOS transistor MP2 is 10 times the size of the first PMOS transistor MP1, and the size of the fourth PMOS transistor MP4 is 10 times the size of the third PMOS transistor MP3.

Continuing as shown in FIG. 2 , specifically, the discharge branch 305 further includes a first NMOS transistor MN1 , a second NMOS transistor MN2 , a third NMOS transistor MN3 and a fourth NMOS transistor MN4 .

The first NMOS transistor MN1 is connected in series between the third PMOS transistor MP3 of the charging branch 303 and the forward input terminal of the second operational amplifier OP2, and the second NMOS transistor MN2 is connected in series between the switching branch 304 and the second operational amplifier OP2. between the inverting inputs of amplifier OP2. The third NMOS transistor MN3 is connected in series between the forward input terminal of the second operational amplifier OP2 and the ground terminal GND, and the fourth NMOS transistor MN4 is connected in series between the reverse input terminal of the second operational amplifier OP2 and the ground terminal GND.

The gate of the third NMOS transistor MN3 and the gate of the fourth NMOS transistor MN4 are commonly connected to the gate of the seventh NMOS transistor MN7 of the bias circuit 301 , the gate of the first NMOS transistor MN1 and the gate of the fifth NMOS transistor MN5 of the bias circuit 301 The poles are connected to each other, and the gate of the second NMOS transistor MN2 is connected to the output terminal of the second operational amplifier OP2.

The third node N3 and the fourth node N4 are respectively disposed at the forward input terminal and the reverse input terminal of the second operational amplifier OP2.

Therefore, in the discharge branch 305, the biases of the first NMOS transistor MN1, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are all generated by the bias circuit 301, and the bias of the second NMOS transistor MN2 is generated by the second operation output of amplifier OP2 to generate. MN1 and MN3 are used to initially amplify the current, and MN2, MN4, and OP2 are used to generate high-precision, high-impedance current sources.

Further, the size of the first NMOS transistor MN1 is twice the size of the fifth NMOS transistor MN5, and the size of the third NMOS transistor MN3 is twice the size of the seventh NMOS transistor MN7. The size of the second NMOS transistor MN2 is 10 times the size of the first NMOS transistor MN1, and the size of the fourth NMOS transistor MN4 is 10 times the size of the third NMOS transistor MN3. Therefore, by setting the width-to-length ratio of MN2 and MN4 to be several times that of MN5 and MN7 in the discharge branch 305 , the current of several times the current source I1 can be obtained.

Continuing as shown in FIG. 2 , specifically, the switching branch 304 includes a first transmission gate TG1 , a second transmission gate TG2 , a third transmission gate TG3 , a fourth transmission gate TG4 and a third operational amplifier OP3 . The first transmission gate TG1 and the third transmission gate TG3 are serially connected between the charging branch 303 and the discharging branch 305 in sequence; the second transmission gate TG2 and the fourth transmission gate TG4 are serially connected between the charging branch 303 and the discharging branch 305 in sequence. Between branch 305.

The forward input terminal of the third operational amplifier OP3 is connected to the connection point between the second transmission gate TG2 and the fourth transmission gate TG4; the reverse input terminal of the third operational amplifier OP3 is connected to the output terminal and connected to the first transmission gate At the connection point of TG1 and the third transmission gate TG3.

信号来驱动。UP信号与

信号是一对相反的信号，当UP信号为高电平，

信号为低电平时，电荷泵电路通过充电支路303对低通滤波器充电；当UP信号为高电平，

信号为低电平时，充电支路303对输出端口呈现高阻态，防止电流泄露使锁相环失锁。Further, the positive control terminal of the first transmission gate TG1 and the negative control terminal of the second transmission gate TG2 are driven by the UP signal generated by the frequency discriminator, the negative control terminal of the first transmission gate TG1 and the second transmission gate TG2. The positive control terminal is generated by the frequency discriminator of the previous stage

signal to drive. UP signal with

The signal is a pair of opposite signals, when the UP signal is high,

When the signal is at a low level, the charge pump circuit charges the low-pass filter through the charging branch 303; when the UP signal is at a high level,

When the signal is at a low level, the charging branch 303 presents a high-impedance state to the output port to prevent current leakage from causing the phase-locked loop to lose lock.

信号来驱动。DW信号与

信号是一对相反的信号，当DW信号为高电平，

信号为低电平时，低通滤波器通过电荷泵电路的放电支路305放电；当DW信号为高电平，

信号为低电平时，放电支路305对输出端口呈现高阻态，防止电流泄露导致电荷泵失锁。The positive control terminal of the third transmission gate TG3 and the negative control terminal of the fourth transmission gate TG4 are driven by the DW signal generated by the frequency discriminator, the negative control terminal of the third transmission gate TG3 and the positive control terminal of the fourth transmission gate TG4 The terminal is generated by the frequency and phase detector

signal to drive. DW signal with

The signal is a pair of opposite signals, when the DW signal is high,

When the signal is at a low level, the low-pass filter discharges through the discharge branch 305 of the charge pump circuit; when the DW signal is at a high level,

When the signal is at a low level, the discharge branch 305 presents a high-impedance state to the output port to prevent current leakage from causing the charge pump to lose lock.

In this embodiment, the output node Vcont of the charge pump circuit is disposed between the second transmission gate TG2 and the fourth transmission gate TG4, and is also connected to the forward input terminal of the third operational amplifier OP3. The inverting input end of the third operational amplifier OP3 is connected to the output end to form a unity gain amplifier, and Vcont and Vcont' are clamped to reduce the charge sharing effect and output stray.

Based on the above disclosure, the basic working principle of the charge pump circuit for the phase-locked loop according to the embodiment of the present invention is as follows:

A self-biased low-voltage cascode circuit is formed by the first resistor R1, the fifth NMOS transistor MN5, and the seventh NMOS transistor MN7, and the current generated by the current source I1 is accurately copied to generate the bias of the discharge branch 305. The second resistor R2 , the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 also form a self-biased low-voltage cascode circuit to generate a bias for the charging branch 303 . Since the current of the bias circuit 301 also generates noise, the current of the bias circuit 301 is biased in the low current mode, and the size of the second NMOS transistor MN2 and the fourth NMOS transistor MN4 of the discharge branch 305 The size of the fifth NMOS transistor MN5 and the seventh NMOS transistor MN7 of the bias circuit 301 , the transistors of the charging branch 303 , the second PMOS transistor MP2 and the fourth PMOS transistor MP4 are several times larger than that of the fifth PMOS transistor of the bias circuit 301 . MP5 and the sixth PMOS transistor MP6 can obtain a current several times that of the current source I1, so that the current of the charge pump reaches the required value.

However, in this process, due to the existence of the channel length modulation effect of the transistor, the transistor still cannot accurately copy the current of the bias circuit, which leads to the mismatch between the charging branch and the discharging branch, which makes the output signal of the phase-locked loop stray. .

In the embodiment of the present invention, the operational amplifiers OP1 and OP2 are respectively added to the charging branch and the discharging branch to clamp the drains of the transistors MP1 and MP2, the drains of MN3 and MN4 to make the voltages equal and eliminate the channel length of the transistors. Modulation effect to achieve accurate replication of current. At the same time, different from the traditional solution, in the embodiment of the present invention, by adding an operational amplifier and using current negative feedback, the output impedance of the charging branch and the discharging branch is greatly increased, and the effect of the output port voltage on the charging and discharging current is reduced. The effect allows the circuit to achieve a high output voltage range while maintaining low mismatch.

The switch circuit 304 keeps the circuit in an on state by replacing the traditional switch with a transmission gate, and then through the third operational amplifier OP3, the charge sharing effect can be reduced, and the linearity and stray performance of the charge pump can be further improved.

It should also be noted that the cadence simulation shows that under the condition of 1V working voltage, under the condition of 0.2-0.8V output voltage, the current deviation between the charging branch and the discharging branch is less than 0.1%. It can be seen from this that the embodiment of the present invention has a simple structure, is easy to integrate, and is suitable for use in a high-performance charge pump phase-locked loop.

To sum up, an embodiment of the present invention provides a charge pump circuit for a phase-locked loop, including a bias circuit 301 and a main charge pump core circuit 302 . The embodiment of the present invention generates a bias voltage for the low voltage cascodes MN1 and MN3 through the first resistor R1, the fifth NMOS transistor MN5 and the seventh NMOS transistor MN7, the second resistor R2, the fifth PMOS transistor MP5 and the seventh NMOS transistor MN7. The six PMOS transistors MP6 generate a bias voltage for the low voltage cascodes MP1 and MP3 to accurately replicate the current of the current source I1 while increasing the output range of the charge pump.

In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", etc. are based on those shown in the accompanying drawings The orientation or positional relationship is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Throughout the drawings, the same elements are denoted by the same or similar reference numbers. Conventional structures or constructions will be omitted when they may obscure the understanding of the present invention. And the shape, size and positional relationship of each component in the figure do not reflect the actual size, proportion and actual positional relationship.

Similarly, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together into a single embodiment, figure or in the description. Description with reference to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc. means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example includes in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In addition, the terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature defined as "first", "second" may expressly or implicitly include one or more of that feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise expressly and specifically defined. Furthermore, the word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. Unless stated otherwise, the expressions "about", "about", "substantially" and "about" mean within 10%, preferably within 5%.

The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present invention in further detail. It should be understood that the above descriptions are only specific embodiments of the present invention, and are not intended to limit the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (10)

1. A charge pump circuit for a phase locked loop, comprising:

a bias circuit (301);

the main charge pump core circuit (302) is used for generating low mismatch current and comprises a charging branch circuit (303), a switching branch circuit (304) and a discharging branch circuit (305), wherein the switching branch circuit (304) is respectively connected with the charging branch circuit (303) and the discharging branch circuit (305);

wherein the bias circuit (301) is used for generating bias voltages required by the charging branch circuit (303) and the discharging branch circuit (305), respectively;

the charging branch (303) comprises a first operational amplifier (OP1) and is provided with a first node (N1) and a second node (N2), and the charging branch (303) is used for clamping by using the first operational amplifier (OP1) to enable the potentials of the first node (N1) and the second node (N2) to be equal;

the discharging branch (305) comprises a second operational amplifier (OP2), a third node (N3) and a fourth node (N4) are arranged, and the discharging branch (305) is used for clamping by using the second operational amplifier (OP2) to enable the potentials of the third node (N3) and the fourth node (N4) to be equal.

2. The charge pump circuit for a phase locked loop of claim 1, wherein the current of the first node (N1) and the current of the third node (N3) are equal.

3. The charge pump circuit for a phase locked loop of claim 1, wherein the bias circuit (301) comprises a current source (Il), a first resistor (R1), a second resistor (R2), a fifth NMOS transistor (MN5), a sixth NMOS transistor (MN6), a seventh NMOS transistor (MN7), an eighth NMOS transistor (MN8), a fifth PMOS transistor (MP5), and a sixth PMOS transistor (MP6), wherein:

the current source (I1), the first resistor (R1), the fifth NMOS transistor (MN5) and the seventh NMOS transistor (MN7) are sequentially connected in series between a power supply terminal (VDD) and a ground terminal (GND), the gate of the fifth NMOS transistor (MN5) is connected to a connection point of the current source (I1) and the first resistor (R1), and the gate of the seventh NMOS transistor (MN7) is connected to a connection point of the first resistor (R1) and the fifth NMOS transistor (MN 5);

the fifth PMOS transistor (MP5), the sixth PMOS transistor (MP6), the second resistor (R2), the sixth NMOS transistor (MN6), and the eighth NMOS transistor (MN8) are sequentially connected in series between the power supply terminal (VDD) and the ground terminal (GND), the gate of the fifth PMOS transistor (MP5) is connected to a connection point of the second resistor (R2) and the sixth PMOS transistor (MP6), the gate of the sixth PMOS transistor (MP6) is connected to a connection point of the second resistor (R2) and the sixth NMOS transistor (MN6), the gate of the sixth NMOS transistor (MN6) is connected to the gate of the fifth NMOS transistor (MN5), and the gate of the eighth NMOS transistor (MN8) is connected to the gate of the seventh NMOS transistor (MN 7).

4. The charge pump circuit of claim 3, wherein the sixth NMOS transistor (MN6) is the same size as the fifth NMOS transistor (MN5), and the eighth NMOS transistor (MN8) is the same size as the seventh NMOS transistor (MN 7).

5. The charge pump circuit for a phase locked loop according to claim 3, wherein the charging branch (303) further comprises a first PMOS transistor (MP1), a second PMOS transistor (MP2), a third PMOS transistor (MP3), and a fourth PMOS transistor (MP4), wherein:

the first PMOS transistor (MP1) is connected in series between the power supply terminal (VDD) and the positive input terminal of the first operational amplifier (OP1), the second PMOS transistor (MP2) is connected in series between the power supply terminal (VDD) and the negative input terminal of the first operational amplifier (OP1), and the grid of the first PMOS transistor (MP1) and the grid of the second PMOS transistor (MP2) are connected to the grid of a fifth PMOS transistor (MP5) of the bias circuit (301);

the third PMOS transistor (MP3) is connected in series between the positive input end of the first operational amplifier (OP1) and the discharge branch (305), and the gate of the third PMOS transistor (MP3) is connected with the gate of the sixth PMOS transistor (MP6) of the bias circuit (301);

the fourth PMOS transistor (MP4) is connected in series between the inverting input terminal of the first operational amplifier (OP1) and the switching branch (304), and the gate of the fourth PMOS transistor (MP4) is connected with the output terminal of the first operational amplifier (OP 1);

the first node (N1) and the second node (N2) are respectively arranged at a positive input end and a negative input end of the first operational amplifier (OP 1).

6. The charge pump circuit for phase locked loops according to claim 5, wherein the size of the first PMOS transistor (MP1) is 2 times the size of a fifth PMOS transistor (MP5) of the bias circuit (301), and the size of the third PMOS transistor (MP3) is 2 times the size of a sixth PMOS transistor (MP6) of the bias circuit (301);

the size of the second PMOS transistor (MP2) is 10 times the size of the first PMOS transistor (MP1), and the size of the fourth PMOS transistor (MP4) is 10 times the size of the third PMOS transistor (MP 3).

7. The charge pump circuit for a phase locked loop of claim 5, wherein the discharge branch (305) further comprises a first NMOS transistor (MN1), a second NMOS transistor (MN2), a third NMOS transistor (MN3), and a fourth NMOS transistor (MN4), wherein:

the first NMOS transistor (MN1) is connected in series between a third PMOS transistor (MP3) of the charging branch (303) and a positive input terminal of the second operational amplifier (OP2), and the second NMOS transistor (MN2) is connected in series between the switching branch (304) and a negative input terminal of the second operational amplifier (OP 2);

the third NMOS transistor (MN3) is connected in series between the forward input terminal of the second operational amplifier (OP2) and the ground terminal (GND), and the fourth NMOS transistor (MN4) is connected in series between the inverting input terminal of the second operational amplifier (OP2) and the ground terminal (GND);

the gate of the third NMOS transistor (MN3) and the gate of the fourth NMOS transistor (MN4) are commonly connected to the gate of a seventh NMOS transistor (MN7) of the bias circuit (301), the gate of the first NMOS transistor (MN1) is connected with the gate of a fifth NMOS transistor (MN5) of the bias circuit (301), and the gate of the second NMOS transistor (MN2) is connected with the output end of the second operational amplifier (OP 2);

the third node (N3) and the fourth node (N4) are respectively arranged at a positive input end and a negative input end of the second operational amplifier (OP 2).

8. The charge pump circuit for phase-locked loop of claim 7, wherein the size of the first NMOS transistor (MN1) is 2 times the size of the fifth NMOS transistor (MN5), and the size of the third NMOS transistor (MN3) is 2 times the size of the seventh NMOS transistor (MN 7);

the size of the second NMOS transistor (MN2) is 10 times the size of the first NMOS transistor (MN1), and the size of the fourth NMOS transistor (MN4) is 10 times the size of the third NMOS transistor (MN 3).

9. The charge pump circuit for a phase locked loop according to claim 1, wherein the switching branch (304) comprises a first transmission gate (TG1), a second transmission gate (TG2), a third transmission gate (TG3), a fourth transmission gate (TG4), and a third operational amplifier (OP3), wherein:

the first transmission gate (TG1) and the third transmission gate (TG3) are sequentially connected in series between the charging branch (303) and the discharging branch (305); the second transmission gate (TG2) and the fourth transmission gate (TG4) are sequentially connected in series between the charging branch (303) and the discharging branch (305);

the positive input end of the third operational amplifier (OP3) is connected to the connection point of the second transmission gate (TG2) and the fourth transmission gate (TG4), and the negative input end of the third operational amplifier (OP3) is connected to the output end and is connected to the connection point of the first transmission gate TG1 and the third transmission gate TG 3.

10. The charge pump circuit of claim 9, wherein the positive control terminal of the first transmission gate (TG1) and the negative control terminal of the second transmission gate (TG2) are driven by an UP signal generated by a phase frequency detector, and the negative control terminal of the first transmission gate (TG1) and the positive control terminal of the second transmission gate (TG2) are driven by an UP signal generated by the phase frequency detector

Signal to drive;

the positive control end of the third transmission gate (TG3) and the negative control end of the fourth transmission gate (TG4) are driven by DW signals generated by the phase frequency detector, and the negative control end of the third transmission gate (TG3) and the positive control end of the fourth transmission gate (TG4) are driven by DW signals generated by the phase frequency detector

Signal to drive;

an output node (Vcont) of the charge pump circuit is disposed between the second transmission gate (TG2) and a fourth transmission gate (TG 4).

Images