CN114996074B - Chip reset verification method, device and equipment supporting multiple space domains - Google Patents
Chip reset verification method, device and equipment supporting multiple space domainsInfo
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- CN114996074B CN114996074B CN202210718687.7A CN202210718687A CN114996074B CN 114996074 B CN114996074 B CN 114996074B CN 202210718687 A CN202210718687 A CN 202210718687A CN 114996074 B CN114996074 B CN 114996074B
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
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Abstract
The embodiment of the invention provides a chip reset verification method, device and equipment supporting multiple spatial domains, which comprises the steps of packaging an independent reusable general verification component for reset signals in a verification platform, driving the reset signals to a reset signal input port of a design to be tested in a reset_phase stage during simulation so as to reset the design to be tested, monitoring the state of the reset signals by using the verification component related to the reset signals, jumping back to the reset_phase stage when the simulation is about to be finished, carrying out heavy load replacement on the verification platform by using a factor heavy load mechanism, restarting to execute a random test sequence after jumping back to the reset_phase, obtaining the actual response of the design to be tested to the random test sequence, and comparing the actual response with a predicted response so as to verify the reset function of the design to be tested. The invention solves the problem of resetting scene test of a plurality of clocks and corresponding resetting space domains possibly existing in the DUT.
Description
Technical Field
The present invention relates to the field of chip design, and in particular, to a method, apparatus, device, and medium for chip reset verification supporting multiple spatial domains.
Background
When verifying a design under test (DUT, design under test) during chip design, it is often necessary to consider the verification under a reset scenario, that is, to set a reset signal to an active state to reset the design under test during normal simulation operation of the design under test, and after a delay of a period of clock cycles, release the reset signal to restart the DUT, and verify whether the restarted DUT can work normally.
Typically, the designer resets the design under test at any point in the simulation process, which is likely to disrupt the running state of the test platform (testbench), causing unexpected problems. Meanwhile, a plurality of clocks and corresponding reset space domains can exist in the DUT, so that the test of the reset scene of the chips with the plurality of space domains in the same test platform is a complex and troublesome problem, and no existing scheme capable of being followed is available at present to perfectly solve the problem.
Disclosure of Invention
In view of the above, the present invention aims to provide a chip reset verification method, device, apparatus and medium method, device and medium for supporting multiple spatial domains, so as to improve the above-mentioned problems.
The embodiment of the invention provides a chip reset verification method supporting multiple spatial domains, which comprises the following steps:
In the verification platform, independent reusable general verification components are packaged for reset signals, wherein the independent verification components are positioned in different spatial domains;
During simulation, driving a reset signal to a reset signal input port of a design to be tested in a reset_phase stage through the universal verification component so as to reset the design to be tested, and monitoring the state of the reset signal by utilizing a verification component related to the reset signal;
Jumping back to reset_phase stage when the simulation is about to end;
The method comprises the steps that a factor reloading mechanism is used for reloading and replacing the verification platform, so that after jumping back to reset_phase, a random test sequence is restarted to be executed, and the test of a reset scene with a plurality of clocks and corresponding reset space domains in the design to be tested is completed;
and obtaining the actual response of the design to be tested to the random test sequence, and comparing the actual response with the predicted response to verify the reset function of the design to be tested.
Preferably, encapsulating a reset signal with a separate reusable generic authentication component specifically comprises:
creating a reset interface model to transmit a reset signal to the design to be tested;
Creating a transaction data type related to a reset signal, wherein the transaction data type comprises two data variable members which are respectively used for representing the delay time before reset and the effective duration time of the reset signal and restraining the delay time and the effective duration time of the reset signal to a reasonable expected range;
creating a stimulus sequence for generating a reset signal;
Creating a driver for driving an excitation sequence of the reset signal, driving the reset signal according to reset delay and duration time information in the transaction data type related to the reset signal, and applying the reset signal to a reset signal input port of the design to be tested;
creating a reset monitor to monitor the reset signal and package the reset signal into a corresponding transaction data type;
Creating a reset sequencer to arbitrate the stimulus sequence of the reset signal and transmit to the driver;
the various components described above in relation to the reset signal are packaged as agents to generate reusable generic authentication components.
Preferably, each component related to the reset signal is encapsulated as an agent to generate a reusable universal verification component, which specifically includes:
declaring a driver, a sequencer, a monitor and a configuration object contained in the exemplary proxy package, wherein the configuration object is used for configuring the number of times of effectively resetting a reset signal of a design to be tested in the whole simulation process;
In the reset_phase of UVM, if the agent is judged to be in a UVM_ACTIVE mode, calling an excitation sequence for executing a reset signal, thereby completing effective reset of a corresponding reset signal of the to-be-tested design;
judging whether the number of effective reset times is smaller than the number of previous configuration times when uvm _shutdown_phase which is about to end simulation is executed in a phase callback function phase_ready_to_end, if so, calling a jump method of phase to jump back to reset_phase to reset again, and executing a test of starting a random test sequence to send a reset function in main_phase again after reset.
Preferably, monitoring the state of the reset signal with a verification component associated with the reset signal comprises:
An interface method for monitoring a synchronous hardware reset signal is provided in a reset interface model for waiting for the reset signal to be activated and waiting for the reset signal to be released, respectively.
Preferably, monitoring the state of the reset signal with a verification component associated with the reset signal further comprises:
Two parallel threads are realized in a monitor of the input/output port signal of the design to be tested, one thread is used for monitoring data on the input/output port signal of the design to be tested and packaging the data into a transaction data type and then broadcasting the transaction data type to other components in the verification platform, the other thread is used for monitoring that a waiting reset signal is activated, and monitoring, packaging and broadcasting the port signal of the design to be tested are stopped when the reset signal is effective.
Preferably, monitoring the state of the reset signal with a verification component associated with the reset signal further comprises:
two parallel threads are implemented in a driver for driving an input signal sequence, one thread being used to acquire and drive an input excitation sequence of a design to be tested onto an input port of the design to be tested, the other thread being used to monitor for waiting for a reset signal to be activated, and stopping driving and resetting signals on an input interface bus when the reset signal is valid.
Preferably, monitoring the state of the reset signal with a verification component associated with the reset signal further comprises:
In a sequencer for arbitrating and transmitting an input stimulus sequence, there is no need to monitor a reset valid signal, and after a phase jump, all sequences running on the sequencer in arbitrate are automatically stopped and the sequencer is reset to an idle state.
Preferably, obtaining an actual response of the design under test to the random test sequence, and comparing the actual response with a predicted response to verify a reset function of the design under test, specifically including:
two parallel threads are implemented in a scoreboard component for comparing the output results of the design under test and the reference model, one thread is used for predicting the response and comparing with the actual response output by the design under test, the other thread is used for monitoring that a waiting reset signal is activated, and when the reset signal is valid, the internal logic is cleared.
The embodiment of the invention also provides a chip reset verification device supporting multiple space domains, which comprises:
the device comprises an encapsulation unit, a resetting unit and a resetting unit, wherein the encapsulation unit is used for encapsulating an independent reusable general verification component for the resetting signal in a verification platform, and the independent verification components are positioned in different spatial domains in the verification platform;
The reset unit is used for driving a reset signal to a reset signal input port of a design to be tested in a reset_phase stage through the universal verification component during simulation so as to reset the design to be tested, and monitoring the state of the reset signal by utilizing the verification component related to the reset signal;
the jump unit is used for jumping back to the reset_phase stage when the simulation is about to end;
The reloading unit is used for reloading and replacing the verification platform by using a factor reloading mechanism, so that after jumping back to reset_phase, the execution of the random test sequence is restarted, and the test of a reset scene with a plurality of clocks and corresponding reset space domains in the design to be tested is completed;
and the verification unit is used for obtaining the actual response of the design to be tested to the random test sequence, and comparing the actual response with the predicted response so as to verify the reset function of the design to be tested.
The embodiment of the invention also provides a chip reset verification device supporting multiple spatial domains, which comprises a memory and a processor, wherein a computer program is stored in the memory, and the computer program can be executed by the processor so as to realize the chip reset verification method supporting multiple spatial domains.
The invention provides a phase jump method to supplement a test method of a design to be tested in a reset scene, and simultaneously combines a factor reloading mechanism and a domain mechanism of UVM to realize the support of a chip reset test scene of multiple space domains, thereby solving the reset scene test problem of multiple clocks and corresponding reset space domains possibly existing in a DUT.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a diagram of an authentication platform architecture for a reset scenario.
Fig. 2 is a detailed partitioning and execution sequence diagram of the UVM phase mechanism.
Fig. 3 is a schematic diagram of a single clock domain digital logic circuit composition.
FIG. 4 is a schematic diagram of a multi-clock domain digital logic circuit
Fig. 5 is a flowchart of a chip reset verification method supporting multiple spatial domains according to a first embodiment of the present invention.
Fig. 6 is a schematic structural diagram of a chip reset verification device supporting multiple spatial domains according to a second embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
For a better understanding of the technical solution of the present invention, the following detailed description of the embodiments of the present invention refers to the accompanying drawings.
It should be understood that the described embodiments are merely some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
The embodiments of the present invention provide a method, an apparatus and a device for chip reset verification supporting multiple spatial domains, which comprehensively apply a phase mechanism of UVM, a factor reload mechanism and a domain mechanism to facilitate understanding of the present invention, and the mechanism related to the present invention is described below.
(1) Phase mechanism
The appearance of the phase mechanism is to unify the execution sequence of codes in simulation, so long as the sequence is complied with by everybody, the problem of difficult debugging caused by disordered code sequence can not occur, thereby helping to realize the reusability of codes and providing a unified standard for code simulation execution control.
The phase of UVM is mainly divided into three parts, as follows:
build phases, this stage is used to configure, build and connect a hierarchical authentication platform.
Run-TIME PHASES this stage consumes simulation time and generates and runs test cases.
Clean up phases this stage is used to collect and print simulation results.
A specific division is shown in fig. 2.
The phases are predefined functions or tasks, and are automatically invoked and executed according to a certain sequence. Common phases mainly include build, connect, run and report, which complete the setup, connection, operation, and reporting of the components, respectively.
In run_phase, the user typically needs to go through the following excitation sequence if the test is to be completed:
1. Powering up
2. Resetting
3. Configuration register
4. Performing test stimulus to complete target test content
5. Waiting for DUT to complete testing
In a simple way, the user can complete all the excitation sequences in run_phase, or in another way, if the above typical sequences can be divided into different intervals, the corresponding excitation can be executed according to the intervals, the test can be more layered and more refined simulation control can be realized. Therefore, run_phase can be further divided into 12 phases parallel to the right in fig. 2, and the execution sequence is from top to bottom.
For example, the above five steps are all originally completed in run_phase, and can now be completed by dispersing into the following phases:
1. Power-up- & gt pre_reset_phase
2. Reset → reset_phase
3. Configuration register → configuration_phase
4. Executing test stimulus to complete target test content- & gtmain_phase
5. Wait for DUT to finish testing- & gt shutDown_phase
(2) Factor reloading mechanism
The most important factor reloading mechanism of the UVM is the reloading function of the UVM, and the replacement of components (components) or objects (objects) of the existing verification platform can be realized, so that the verification platform can be reused conveniently.
In order to use the reloading function of the factory mechanism of UVM, the following three points are needed:
(1) An object or component is registered with a factory using macro 'uvm _object_units (T) or' uvm _component_units (T).
(2) A component or object is constructed using the type_name:: type_id:: create () instead of the new constructor.
(3) The class that is reloaded needs to be the parent class of the reloaded class.
Two heavy load using modes are supported, and the two heavy load using modes are respectively:
1. Replacing all components or objects A in the verification platform with components or objects B
2. Replacing part of component or object A with component or object B in verification platform
(3) Domain mechanism
As shown in fig. 3, the digital chip is composed of a stack of digital logic circuits, which are divided into a combinational logic circuit and a sequential logic circuit.
The sequential logic circuit is controlled by a clock (clk in fig. 3), and the data is synchronized and registered by rising edge or falling edge in a beat-to-beat manner like a heartbeat, while the combinational logic is a logic operation such as and, or, not, exclusive or, etc., and the path delay of the combinational logic circuit is different according to the complexity of the operation, but the setup time and the hold time of the sequential logic circuit need to be satisfied.
The general combinational logic circuit is between the two sets of flip-flops, and the operation process in fig. 3 is approximately:
The data input (data_in in fig. 3) is entered, then registered through a register (block formed by D, Q, CLK in fig. 3), then operated through a section of combinational logic, finally registered through a group of registers and output operation result (data_out in fig. 3), and the whole digital circuit is synchronized by a clock clk, which is equivalent to completing the processing and transmission of circuit signals according to the transitions of clk, so that the circuit is said to operate based on the clock of clk, and then the area of the circuit based on the clock of clk can be called as clk clock domain.
The DUT of fig. 3 has only one clk clock domain, and the case where there are multiple clock domains on one DUT is seen below. As shown in fig. 4:
At this time, there are two clock domains, respectively, the circuits operating based on clk1 and clk2 clocks in fig. 4, which are independent of each other.
In fact, often when verification is performed, it is often encountered that the Design Under Test (DUT) is based on multiple clock domains, how are the two mutually independent parts reset, configure, and start up, respectively?
By default, all components (components) in the verification platform are located in the same spatial domain (domain). However, to implement resetting, configuring, and starting two clock domains of the same DUT, but independent of each other, it is necessary to have the two independent portions located in two different domains, respectively.
By separating the two clock domains by means of these two domains, the subdivisions of Run-time in the two clock domains, which consume simulation time, can Run asynchronously, independently of each other.
Note, however, that here domains can only isolate the subdivided Run-time subdivision phases, and for other phases they are still synchronized, i.e. the run_phases of both domains remain synchronized, and other non-simulation time consuming functional phases are synchronized.
The present invention will be described in more detail below in connection with the above mechanism.
Referring to fig. 5, a first embodiment of the present invention provides a chip reset verification method supporting multiple spatial domains, which includes:
s101, in the verification platform, independent reusable general verification components are packaged for the reset signal, wherein in the verification platform, the independent verification components are located in different spatial domains.
In this embodiment, based on the domin mechanism described above, the verification components of the verification platform of this embodiment that are independent of each other are respectively located in two different domains. Thus, the clock domains can be separated by the independent domains, so that the subdivisions of Run-time consuming simulation time in the clock domains can Run asynchronously and independently of each other.
Specifically, in the present embodiment, step S101 includes:
creating a reset interface model to transmit a reset signal to the design to be tested;
Creating a transaction data type related to a reset signal, wherein the transaction data type comprises two data variable members which are respectively used for representing the delay time before reset and the effective duration time of the reset signal and restraining the delay time and the effective duration time of the reset signal to a reasonable expected range;
creating a stimulus sequence for generating a reset signal;
Creating a driver for driving an excitation sequence of the reset signal, driving the reset signal according to reset delay and duration time information in the transaction data type related to the reset signal, and applying the reset signal to a reset signal input port of the design to be tested;
creating a reset monitor to monitor the reset signal and package the reset signal into a corresponding transaction data type;
Creating a reset sequencer to arbitrate the stimulus sequence of the reset signal and transmit to the driver;
the various components described above in relation to the reset signal are packaged as agents to generate reusable generic authentication components.
The method specifically comprises the following steps:
declaring a driver, a sequencer, a monitor and a configuration object contained in the exemplary proxy package, wherein the configuration object is used for configuring the number of times of effectively resetting a reset signal of a design to be tested in the whole simulation process;
In the reset_phase of UVM, if the agent is judged to be in a UVM_ACTIVE mode, calling an excitation sequence for executing a reset signal, thereby completing effective reset of a corresponding reset signal of the to-be-tested design;
judging whether the number of effective reset times is smaller than the number of previous configuration times when uvm _shutdown_phase which is about to end simulation is executed in a phase callback function phase_ready_to_end, if so, calling a jump method of phase to jump back to reset_phase to reset again, and executing a test of starting a random test sequence to send a reset function in main_phase again after reset.
S102, driving a reset signal to a reset signal input port of a design to be tested in a reset_phase stage through the universal verification component during simulation so as to reset the design to be tested, and monitoring the state of the reset signal by utilizing the verification component related to the reset signal.
In this embodiment, after the universal verification component is obtained, by declaring and instantiating a reset signal excitation sequence (reset_sequence), the reset_phase stage in the simulation process can be started to generate a reset signal to a reset signal input port of the design to be tested. The method comprises the steps of carrying out random constraint configuration on effective reset times in a reset configuration object corresponding to an independent space domain in configuration_phase, so that reset effective excitation with random quantity is generated and applied to a reset signal port corresponding to a design to be tested, and random function test under a repeated reset scene is completed.
In this embodiment, monitoring the state of the reset signal with the verification component associated with the reset signal includes:
An interface method for monitoring a synchronous hardware reset signal is provided in a reset interface model for waiting for the reset signal to be activated and waiting for the reset signal to be released, respectively.
Two parallel threads are realized in a monitor of the input/output port signal of the design to be tested, wherein one thread is used for monitoring data on the input/output port signal of the design to be tested and packaging the data into a transaction data type and then broadcasting the transaction data type to other components in the verification platform, the other thread is used for monitoring that a waiting reset signal is activated, and when the reset signal is effective, monitoring, packaging and broadcasting of the port signal of the design to be tested are stopped. After that, the waiting reset signal is released, the design to be tested enters a normal operating state, and then the above-mentioned process is repeated continuously.
Two parallel threads are also implemented in the driver for driving the input signal sequence, one for taking and driving the design-under-test input stimulus sequence element (sequence_item) onto the input port of the design-under-test, and the other for monitoring. Waiting for the reset signal to be activated, stopping driving and resetting the signal on the input interface bus when the reset signal is valid. After that, the waiting reset signal is released, the design to be tested enters a normal operating state, and then the above-mentioned process is repeated continuously.
In a sequencer for arbitrating and transmitting an input stimulus sequence, there is no need to monitor a reset valid signal, and after a phase jump, all sequences running on the sequencer in arbitrate are automatically stopped and the sequencer is reset to an idle state.
S103, jumping back to the reset_phase stage when the simulation is about to end.
Specifically, the method can jump back to reset_phase when the simulation is about to end, which is equivalent to resetting the design to be tested in the simulation process, and then re-executing the random test sequence in main_phase, wherein if the random test sequence of the basic function is adopted, the method is equivalent to performing the basic function test of the design to be tested in the reset scene.
S104, carrying out reloading replacement on the verification platform by using a factor reloading mechanism, so that after jumping back to reset_phase, restarting to execute a random test sequence to finish the test of a reset scene with a plurality of clocks and corresponding reset space domains in the design to be tested.
Specifically, in this embodiment, the reloading replacement is performed on the verification platform of multiple spatial domains according to the factor reloading mechanism, which is mainly used for restarting the random test sequence after phase jump, so as to complete the test of the reset scene where multiple clocks and corresponding reset spatial domains exist in the design to be tested
And the verifying component is subjected to heavy-load replacement in the build_phase by using a factor mechanism, so that after the clock reset signal corresponding to the independent space domain is effectively reset, the corresponding random test sequence is retransmitted to apply the input stimulus to the design to be tested.
S105, obtaining the actual response of the design to be tested to the random test sequence, and comparing the actual response with the predicted response to verify the reset function of the design to be tested.
In this embodiment, after the random test sequence is applied to the design under test, the design under test operation is waited for to complete, and the corresponding actual response is returned.
Then, two parallel threads are implemented in the scoreboard component for comparing the output results of the design under test and the reference model, one for predicting the response and comparing with the actual response of the design under test output, the other for monitoring the wait for reset signal to be activated, and when the reset signal is valid, the internal logic is cleared.
In summary, the invention provides a phase jump method to supplement the test method of the design to be tested in the reset scene, and combines the factor reloading mechanism and domain mechanism of UVM to realize the support of the chip reset test scene of multiple space domains, thereby solving the reset scene test problem of multiple clocks and corresponding reset space domains possibly existing in the DUT.
Referring to fig. 6, a second embodiment of the present invention further provides a chip reset verification apparatus supporting multiple spatial domains, which includes:
an encapsulation unit 210, configured to encapsulate an independent reusable general purpose authentication component for the reset signal in an authentication platform, where the authentication components independent of each other are located in different spatial domains;
The reset unit 220 is configured to drive a reset signal to a reset signal input port of a design to be tested in a reset_phase stage through the general verification component during simulation, so as to reset the design to be tested, and monitor a state of the reset signal by using a verification component related to the reset signal;
a jumping unit 230 for jumping back to the reset_phase phase when the simulation is about to end;
The reloading unit 240 is configured to reload the verification platform by using a factor reloading mechanism, so that after the jump back to reset_phase, the execution of the random test sequence is restarted, so as to complete the test of the reset scenario in which a plurality of clocks and corresponding reset spatial domains exist in the design to be tested;
and the verification unit 250 is configured to obtain an actual response of the design to be tested to the random test sequence, and compare the actual response with a predicted response to verify a reset function of the design to be tested.
The third embodiment of the present invention further provides a chip reset verification device supporting multiple spatial domains, which includes a memory and a processor, where the memory stores a computer program, and the computer program can be executed by the processor to implement the chip reset verification method supporting multiple spatial domains as described above.
The fourth embodiment of the present invention further provides a computer readable storage medium, where a computer program is stored, where the computer program can be executed by a processor of a device where the computer readable storage medium is located, so as to implement the chip reset verification method supporting multiple spatial domains as described above.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other manners. The apparatus and method embodiments described above are merely illustrative, for example, flow diagrams and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present invention may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, an electronic device, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. The storage medium includes a U disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, an optical disk, or other various media capable of storing program codes. It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
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