CN115000174A - Semiconductor device, forming method thereof and electronic equipment - Google Patents

Abstract

The application discloses a semiconductor device and a forming method thereof, and an electronic device, wherein the semiconductor device comprises: a substrate in which an active electrode layer is formed; a plurality of discrete gate structures located within the substrate, the bottom of the gate structures being located on the surface of the source layer; and the drain electrodes are positioned in the substrate at two sides of the top of the grid structure, and each drain electrode is positioned between two adjacent grids. The common source scheme can be realized by the corresponding semiconductor device, the size of the formed semiconductor device can be reduced, and the area utilization rate of the chip is improved.

Description

Semiconductor device, method for forming the same, and electronic device

technical field

The present application relates to the field of semiconductor technology, and in particular, to a semiconductor device, a method for forming the same, and an electronic device.

Background technique

Single-chip dual MOS (field effect transistor) integration technology has been widely used in fast charging and other schemes. The common drain connection scheme shown in Figure 1a is often used in the fast charging circuit shown in Figure 1b. The above common-drain connection scheme in the test found that: (1) During wireless charging, the BUS (bus) terminal voltage VBUS is the wireless terminal voltage minus the voltage drop of the Q2 tube (the tube voltage drop is low, ignored here), and the internal voltage of Q1 The voltage drop of drain D1 is VBUS-VFD; (2) When the cable is inserted (assuming that the USB terminal voltage VUSB is greater than the wireless terminal voltage Vwireless), the wireless terminal MOS has not been turned off or the VBUS voltage still exists, and the wired terminal MOS has not been turned on, The voltage difference between the two ends of the NMOS on the left side of Q1 is VUSB-VBUS, VBUS is the bus voltage, and a large peak current will flow (depending on the voltage difference), which will have an impact on the MOS body diode and affect the reliability of the system; in addition, there is no wired connection. Complete isolation from the wireless charging port, there is a potential safety hazard.

SUMMARY OF THE INVENTION

In view of this, the present application provides a semiconductor device, a method for forming the same, and an electronic device to solve the problem that the existing common-drain connection scheme affects the reliability of the system and has potential safety hazards.

A semiconductor device provided by this application includes:

a substrate, a source layer is formed in the substrate;

a plurality of discrete gate structures located in the substrate, the bottom of the gate structure is located on the surface of the source layer;

A plurality of drains are located in the substrate on both sides of the top of the gate structure, and each of the drains is located between two adjacent gates.

Optionally, the semiconductor device further includes: a source connection structure electrically connected to the source layer.

Optionally, the plurality of gate structures include a plurality of first gate structures and a plurality of second gate structures, the drains located between adjacent first gate structures are first drains, and the drains located at adjacent second gates The drain between the structures is the second drain;

The semiconductor device further includes: a first drain connection structure interconnected with the first drain; and a second drain connection structure interconnected with the second drain.

Optionally, the semiconductor device further includes: a dielectric layer on the surface of the substrate;

The source connection structure includes: a first conductive plug located in the dielectric layer and a source connection region located on the surface of the dielectric layer;

The first drain connection structure includes: a second conductive plug located in the dielectric layer and a first drain connection region located on the surface of the dielectric layer, and the second conductive plug is connected to the first drain between the connection region and each corresponding first drain; the second drain connection structure includes: a third conductive plug located in the dielectric layer and a second drain connection region located on the surface of the dielectric layer, so The third conductive plugs are connected between the second drain connection regions and the corresponding second drains.

Optionally, the semiconductor device further includes: a source connection portion between the first gate structure and the second gate structure, and the first conductive plug connects the source connection portion and the source Extreme connection area.

Optionally, the semiconductor device further includes: a passivation layer covering the dielectric layer, the first drain connection region, the second drain connection region and the source connection region, the passivation The layer has a first opening that exposes interconnection sites of the first drain connection region, the second drain connection region, and the source connection region.

Optionally, the source connection structure is disposed on the backside of the substrate.

Optionally, the gate structure includes: a gate and a gate dielectric layer between the gate and the substrate.

Optionally, the gate includes a first partial gate at the top and a second partial gate at the bottom; the first partial gate and the second partial gate are interconnected.

Optionally, the substrate further includes a doping layer; the gate structure and the drain structure are formed in the doping layer.

The present application also provides a method for forming a semiconductor device, comprising:

providing a substrate, the substrate including a source layer and a doped layer on the surface of the source layer;

A plurality of gates are formed in the doped layer, and drains are formed between two adjacent gates.

Optionally, the plurality of gate structures include a plurality of first gate structures and a plurality of second gate structures, the drains located between adjacent first gate structures are first drains, and the drains located between adjacent second gate structures The drain between the pole structures is the second drain.

Optionally, the forming method further includes:

Within the doped layer, a source connection portion connecting the source layer is formed, and the source connection portion is located between the first gate structure and the second gate structure.

Optionally, the method for forming the source connection portion includes:

Digging a hole between the first gate structure and the second gate structure to form a first through hole exposing the source layer;

Filling the first through hole with source material to obtain the source connection portion.

Optionally, the forming method further includes:

After forming the drains, a source connection structure is formed to connect the source connection parts, and a first drain connection structure of each of the first drains and a second drain connection structure of each of the first drains are formed .

Optionally, the method for forming the source connection structure, the first drain connection structure and the second drain connection structure includes:

forming a dielectric layer on the surface of the doped layer;

The dielectric layer is etched to form second through holes corresponding to the source connection portion, each of the first drains and each of the second drains, and conductive material is filled into each of the second through holes to form all the second through holes. a first conductive plug corresponding to the source connection portion, a second conductive plug corresponding to each of the first drains, and a third conductive plug corresponding to each of the second drains;

A conductive layer is formed on the surface of the dielectric layer, and the conductive layer is patterned to form a source connection region connected to the first conductive plug, a first drain connection region connected to each second conductive plug, and a first drain connection region connected to each of the first conductive plugs. The second drain connection region of the three conductive plugs.

Optionally, the forming method further includes:

forming a passivation layer covering the dielectric layer, the first drain connection region, the second drain connection region and the source connection region; the passivation layer has a first opening, the first Openings expose interconnection portions of the first drain connection region, the second drain connection region, and the source connection region.

Optionally, the method for forming the substrate includes:

providing a substrate, and doping the inside of the substrate to form the source layer and the doping layer on the surface of the source layer;

Alternatively, a substrate is provided, a surface of the substrate is doped to form a source layer on the surface of the substrate, and a doped layer is epitaxially formed on the surface of the source layer.

Optionally, the forming method further includes:

etching the back side of the substrate to form a first opening exposing the back side of the source layer part;

A source connection structure is formed in the first opening.

Optionally, the method for forming a plurality of gates in the doped layer further comprises:

etching the doped layer to form a plurality of trenches, forming an oxide layer on the sidewalls of each of the trenches, and filling each of the trenches with a semiconductor material to form a gate;

Using the surface of the doped layer as a stop layer, a planarization process is performed.

Optionally, the doped layer is etched to form a plurality of trenches, an oxide layer is formed on the sidewalls of each of the trenches, and a semiconductor material is filled in each of the trenches, and the method for forming a gate is further include:

etching the doped layer to form the main body of the trench;

forming a first sub-oxide layer on the sidewall of the main body;

Etching from the bottom of the main body toward the substrate to form the protruding portion of the trench, and the main body portion and the protruding portion constitute the trench;

A second sub-oxide layer is formed on the sidewall of the trench, and the first sub-oxide layer and the second sub-oxide layer constitute the oxide layer;

The trench is filled with semiconductor material to form a gate.

Optionally, the trench is filled with semiconductor material, and the method for forming a gate further includes:

Filling the trench with a first semiconductor material, and removing the first semiconductor material above the protruding portion to form a first partial gate located in the protruding portion;

forming an interconnection structure on the surface of the first part of the gate electrode;

A second semiconductor material is filled on the surface of the interconnect structure to form a second portion of the gate located in the body portion.

The present application also provides an electronic device, comprising any of the above-mentioned semiconductor devices and a controller; the controller is used to control the on or off of the semiconductor device.

The above-mentioned semiconductor device and its forming method and electronic device of the present application use a source structure to access the source signal, which can realize the common source solution of the corresponding semiconductor device, block the backflow path of the body diode, prevent backflow, and improve the working efficiency of the semiconductor device. In addition, the source layer is arranged at the bottom of the gate structure, and the drain is arranged between two adjacent gates, which can reduce the size of the semiconductor device. , improve the area utilization rate of the chip where it is located, thereby improving the corresponding cell integration degree, so that the corresponding semiconductor device can obtain better on-resistance performance. In addition, the above-mentioned semiconductor device can also not be constrained by the packaging process rules, which further improves the area utilization rate of the corresponding chip.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the drawings that are used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained from these drawings without creative effort.

Fig. 1a, Fig. 1b and Fig. 1c are schematic diagrams of connection of related semiconductor devices in the conventional solution;

FIG. 2 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application;

3 is a schematic structural diagram of a semiconductor device according to another embodiment of the present application;

4 is a schematic structural diagram of a semiconductor device according to another embodiment of the present application;

5 is a schematic structural diagram of a semiconductor device according to another embodiment of the present application;

6 is a schematic structural diagram of a semiconductor device according to another embodiment of the present application;

FIG. 7 is a schematic diagram of a gate structure according to an embodiment of the present application;

8 is a schematic flowchart of a method for forming a semiconductor device according to an embodiment of the present application;

9a and 9b are schematic diagrams of structures obtained by each step in an embodiment of the present application;

10 is a schematic structural diagram of a semiconductor device according to another embodiment of the present application;

11a, 11b, 11c and 11d are schematic diagrams of semiconductor structures in another embodiment of the present application;

12 is a schematic structural diagram of a semiconductor device according to another embodiment of the present application;

13a and 13b are schematic diagrams of the structures obtained by each step in another embodiment of the present application;

14a, 14b and 14c are schematic diagrams of structures obtained by each step in another embodiment of the present application;

Figure 15a, Figure 15b, Figure 15c, Figure 15d and Figure 15e are schematic diagrams of structures obtained by each step in another embodiment of the present application;

16a, 16b and 16c are schematic diagrams of structures obtained by each step in another embodiment of the present application.

Detailed ways

In the fast charging circuit shown in Figure 1b, the inventors conducted research on the common-drain connection scheme, which affects the reliability of the system and has potential safety hazards, and found that if the common-source connection scheme shown in Figure 1c is used, the body diode can be blocked from backflow. access, prevent backflow, and ensure safety performance to a certain extent. However, the chips corresponding to the current common-source connection scheme often have a relatively large size, and there is a problem of low utilization rate of chip area.

In view of the above problems, the semiconductor device, its formation method, and the electronic device provided by the present application adopt a source layer to realize a common source solution, which can block the body diode inversion path, prevent inversion, and set the source layer at the bottom of the gate structure, The space occupied by the source structure can be reduced as much as possible, and the volume of the corresponding semiconductor device can be reduced, thereby improving the area utilization rate of the corresponding chip and improving the relevant performance of the fast charging circuit and/or electronic equipment using the semiconductor device.

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application. In the case of no conflict, the following various embodiments and their technical features can be combined with each other.

A first aspect of the present application provides a semiconductor device, as shown in FIG. 2 , the semiconductor device includes:

a substrate, in which the source layer 123 is formed;

a plurality of discrete gate structures 124 located in the substrate, and the bottom of the gate structures 124 is located on the surface of the source layer 123;

A plurality of drains 126 are located in the substrate on both sides of the top of the gate structure 124 , and each of the drains 126 is located between two adjacent gates 124 .

The above-mentioned semiconductor device adopts the source layer 123 to realize the common source scheme of the semiconductor device, which can block the body diode inversion path and prevent inversion. Occupy the space between and/or both sides of the gate structure 124 to achieve the purpose of space saving, thereby reducing the size of the semiconductor device; the source layer 123, the gate structure 124 and the drain 126 and other structures are arranged in the semiconductor device. In vivo, it can improve the utilization rate of the chip area and the integration of MOS cells, and can obtain better on-resistance performance.

In one embodiment, as shown in FIG. 3 and FIG. 4 , the semiconductor device further includes: a source connection structure 140 a electrically connected to the source layer 123 .

Specifically, the plurality of gate structures 124 include a plurality of first gate structures and a plurality of second gate structures, the drains located between adjacent first gate structures are first drains, and the drains located adjacent to the second gates The drain between the structures is the second drain;

The semiconductor device further includes: a first drain connection structure 140b interconnected with the first drain; and a second drain connection structure 140c interconnected with the second drain.

Optionally, the first drain connection structure 140b and the second drain connection structure 140c are located on two sides of the source connection structure 140a, respectively.

In one example, the semiconductor device further includes: a dielectric layer 130 on the surface of the substrate;

The source connection structure 140 a includes: a first conductive plug 131 located in the dielectric layer 130 and a source connection region 141 located on the surface of the dielectric layer 130 ;

The first drain connection structure 140b includes: a second conductive plug 132 located in the dielectric layer 130 and a first drain connection region 142 located on the surface of the dielectric layer 130, and the second conductive plug 132 is connected to the surface of the dielectric layer 130. Between the first drain connection region 142 and each corresponding first drain; the second drain connection structure 140c includes: a third conductive plug 133 located in the dielectric layer 130 and a third conductive plug located in the dielectric layer The second drain connection region 143 on the surface of 130, and the third conductive plug 133 is connected between the second drain connection region 143 and each corresponding second drain.

Correspondingly, there are dielectric regions 134 between the first conductive plugs 131 and the second conductive plugs 132 and the third conductive plugs 133 respectively, and there are dielectric regions 134 between two adjacent second conductive plugs 132 and two adjacent third conductive plugs 133 . Media area 134 .

Further, the semiconductor device further includes: a source connecting portion 127 located between the first gate structure and the second gate structure, and the first conductive plug 131 is connected to the source connecting portion 127 and the source connection region 141 to connect the required electrical signal to the source connection portion 127 .

In one example, as shown in FIG. 4 , the above-mentioned semiconductor device further includes a passivation layer 145 covering the dielectric layer 130 , the first drain connection region 141 , the second drain connection region 142 and The passivation layer of the source connection region 143, the passivation layer has a first opening, and the first opening exposes the first drain connection region, the second drain connection region and the The interconnection parts of the source connection region, so that the exposed interconnection parts can be connected to other circuits and/or related structures, and cover the gap and part of the surface between the source connection region 141 and the respective drain connection regions, so as to avoid The source connection region 141 and each of the drain connection regions are protected to reduce the loss of each connection region. Optionally, the source connection region 141 and/or each drain connection region respectively exposes at least one interconnection portion. For example, as shown in FIG. 4 , the source connection region 141 exposes only one interconnection portion, and the first drain connection region 142 and the second drain connection region 143 expose two interconnection sites, respectively.

In one embodiment, the above-mentioned source connecting structure can be disposed on the backside of the substrate, so as to omit the structure of the source connecting part between the first gate structure and the second gate structure, so that the source can be omitted The space occupied by the connection portion reduces the gap between the first gate structure and the second gate structure, and further reduces the size of the semiconductor device formed.

Specifically, as shown in FIG. 5 , the above-mentioned base further includes a substrate 111 , and the substrate 111 is located on the back surface 123 of the source layer to protect and support the source layer 123 and other structures.

Optionally, the source connection structure includes the first conductive plug 131 and the source connection region 141 . As shown in FIG. 6 , the source connection regions 141 are provided on the backside of the substrate 111 to provide source interconnections on the backside of the substrate 111 . As shown in FIG. 6 , the source connection region 141 may be disposed inside the substrate 111 , with a surface aligned with the bottom surface of the substrate 111 and exposed by the bottom surface of the substrate 111 . Correspondingly, the first conductive plug 131 may be disposed inside the substrate 111 to realize interconnection between the source electrode 123 and the source electrode connection region 141 .

In one embodiment, the gate structure 124 includes a gate and a gate dielectric layer between the gate and the substrate, so as to isolate the gate and the substrate by using the gate dielectric layer. Specifically, the gate is made of semiconductor materials, such as polysilicon and/or single crystal silicon, and the like.

Specifically, as shown in FIG. 7 , the gate includes a first partial gate 124b located at the top and a second partial gate 124a located at the bottom; the first partial gate 124b and the second partial gate 124a are mutually even.

In one embodiment, the substrate further includes a doping layer; the gate structure and the drain structure are formed in the doping layer. Correspondingly, as shown in FIG. 4 to FIG. 6 , there is a doped region 125 between the source electrode 123 and the drain electrode 126 , and two adjacent gate structures 124 also have a doped region 125 .

Specifically, the source electrode layer 123 and the drain electrode 126 are both doped with the first type of ions; the doped layer is doped with the second type of ions. Optionally, the doped regions 125 are lightly doped regions corresponding to the second type. Optionally, the source layer 123 is a heavily doped region corresponding to the first type ions, so as to reduce the resistivity. The drain 126 may be doped with the first type ions to multiple degrees. For example, the lower layer of the drain 126 is a lightly doped region corresponding to the first type ions, and the upper layer is a heavily doped region corresponding to the first type ions.

The first type is different from the second type to ensure the working effect of the formed semiconductor device. Specifically, when the first type is N-type (eg, arsenic, germanium, etc.), the first type is P-type (eg, boron, boron fluoride, phosphorus, etc.) ions; or, the first type is P In the case of type, the first type is N type.

In one embodiment, the material of the first conductive plug 131, the second conductive plug 132 and/or the third conductive plug 133 includes at least one of aluminum, copper and tungsten, so as to have good electrical conductivity performance.

For the above semiconductor device, the source connection structure 140a is used to connect the source signal to the corresponding semiconductor device, so that the common source solution of the semiconductor device can be realized, and the reliability of the semiconductor device during operation can be improved. In addition, the source layer 123 is arranged at the bottom of the gate structure 124, so that the source layer 123 occupies as little space between and/or both sides of the gate structure 124 as possible, so as to achieve the purpose of space saving, thereby reducing the size of the semiconductor device. The size of the chip increases the area utilization rate of the chip where it is located, thereby improving the corresponding cell integration degree and enabling the corresponding semiconductor device to obtain better on-resistance performance. In addition, the above-mentioned semiconductor device can also not be constrained by the packaging process rules, which further improves the area utilization rate of the corresponding chip.

In a second aspect, the present application provides a method for forming a semiconductor device. Referring to FIG. 8 , the forming method includes S210 and S220.

S210, providing a substrate, as shown in FIG. 9a, the substrate includes a source layer 323 and a doped layer 321 located on the surface of the source layer 323;

S210 , as shown in FIG. 9 b , a plurality of gate electrodes 324 are formed in the doped layer 321 , and a drain electrode 326 is formed between two adjacent gate electrodes 324 . Specifically, the drain 326 is located on the top side of the corresponding gate 324 , there is a doped region 325 between the drain 326 and the source layer 323 , and there is also a doped region 325 between two adjacent gates 324 .

In one embodiment, the plurality of gate structures include a plurality of first gate structures and a plurality of second gate structures, the drains located between adjacent first gate structures are first drains, and the drains located adjacent to the first gate structures are first drains. The drain between the two gate structures is the second drain.

Further, as shown in FIG. 10 , the forming method further includes:

In the doped layer 321, a source connection part 327 is formed to connect the source layer 323, and the source connection part 327 is located between the first gate structure and the second gate structure.

Specifically, the method for forming the source connection portion includes: digging a hole between the first gate structure and the second gate structure to form a first through hole exposing the source layer 323; The first through hole is filled with source material to obtain the source connection portion 327 .

In one example, the forming method further includes:

After the drains 326 are formed, a source connection structure connecting the source connection parts 327 is formed to connect electrical signals to the source, and a first drain connection structure of each first drain is formed and a first drain connection structure is formed to connect each of the first drains. A second drain connection structure of a drain is used to connect two parts of the drain with electrical signals.

Specifically, the method for forming the source connection structure, the first drain connection structure and the second drain connection structure includes:

As shown in FIG. 11a, a dielectric layer 330 is formed on the surface of the doped layer 321;

The dielectric layer 330 is etched to form second through holes corresponding to the source connection portion, each of the first drain electrodes and each of the second drain electrodes, and each second through hole is filled with a conductive material, such as As shown in FIG. 11b, a first conductive plug 331 corresponding to the source connection portion, a second conductive plug 332 corresponding to each of the first drains, and a third conductive plug corresponding to each of the second drains are formed. 333; there is a dielectric region 334 between each conductive plug;

As shown in FIG. 11c, a conductive layer 340 is formed on the surface of the dielectric layer 330, and the conductive layer 340 is patterned. As shown in FIG. 11d, a source connection region 341 connecting the first conductive plug 331 is formed, The first drain connection regions 342 of the respective second conductive plugs 332 are connected and the second drain connection regions 343 of the respective third conductive plugs 333 are connected.

In one embodiment, the forming method further includes: forming a passivation covering the dielectric layer 330 , the first drain connection region 342 , the second drain connection region 343 and the source connection region 341 . passivation layer 345; as shown in FIG. 12, the passivation layer 345 has a plurality of first openings, the first openings expose the first drain connection region 341, the second drain connection region 343 and the The interconnection portion of the source connection region 341 .

Specifically, in this embodiment, a passivation material layer covering the source connection region 341 , each of the drain connection regions and the dielectric region 333 can be formed by a process such as deposition, and then the passivation material layer can be etched to expose the source connection region A passivation layer 345 is formed between the interconnection parts 341 and the respective drain connection regions. Optionally, the source connection region 341 and/or each drain connection region respectively exposes at least one interconnection portion. For example, as shown in FIG. 10 , the source connection region 341 exposes only one interconnection portion, and the first drain connection region 342 and the second drain connection region 343 expose two interconnection sites, respectively.

In one embodiment, the method for forming the substrate includes:

providing a substrate, and doping the inside of the substrate to form the source layer 323 and the doping layer 321 on the surface of the source layer 323;

Alternatively, as shown in FIG. 13 a , a substrate 311 is provided, the surface of the substrate 311 is doped to form a source layer 323 located on the surface of the substrate 311 , and a doped layer 321 is epitaxially formed on the surface of the source layer 323 .

Optionally, the forming method further includes:

etching the backside of the substrate 131 to form a first opening exposing a portion of the backside of the source layer 323;

A source connection structure is formed in the first opening. As shown in FIG. 13b, the source connection structure includes a first conductive plug 331 and a source connection region 341. The source connection region 341 can be provided inside the substrate 311, The surface is aligned with the bottom surface of the substrate 311 and is exposed by the bottom surface of the substrate 311 . Correspondingly, the first conductive plug 331 may be disposed inside the substrate 311 to realize interconnection between the source electrode 323 and the source electrode connection region 341 .

In one embodiment, the source layer 323 and the drain 326 are both doped with the first type of ions; the doped layer 321 is doped with the second type of ions. Optionally, the source electrode 123 is a heavily doped region corresponding to the first type ions, so as to reduce the resistivity. The drain 326 can be doped with the first type ions to multiple degrees. For example, the lower layer of the drain 326 is a lightly doped region corresponding to the first type ions, and the upper layer is a heavily doped region corresponding to the first type ions, and so on.

The first type is different from the second type to ensure the working effect of the formed semiconductor device. Specifically, when the first type is N-type (eg, arsenic, germanium, etc.), the first type is P-type (eg, boron, boron fluoride, phosphorus, etc.) ions; or, the first type is P In the case of type, the first type is N type.

In one embodiment, the method of forming a plurality of gates 324 in the doped layer 321 further includes:

The doped layer 321 is etched to form a plurality of trenches 322. The trenches 322 can be as shown in FIG. 14a, as shown in FIG. 14b, and an oxide layer 328 is formed on the sidewalls of each of the trenches 322, as shown in FIG. 14b. As shown in 14c, each of the trenches 322 is filled with semiconductor material to form a gate electrode 324;

Using the surface of the doped layer 321 as a stop layer, a planarization process is performed.

Specifically, the doped layer 321 is etched to form a plurality of trenches 322, an oxide layer 328 is formed on the sidewalls of each of the trenches 322, and a semiconductor material is filled in each of the trenches 322 to form a gate The method of pole 324 further includes:

As shown in FIG. 15a, the doped layer 321 is etched to form the main body 322a of the trench 322;

As shown in FIG. 15b, a first sub-oxide layer 328a is formed on the sidewall of the main body portion 332a;

As shown in FIG. 15c, etching is performed from the bottom of the main body portion 322a toward the substrate 311 to form the protruding portion 322b of the trench 322. The main body portion 322a and the protruding portion 322b constitute a the groove 322;

As shown in FIG. 15d, a second sub-oxide layer 328b is formed on the sidewall of the trench 322, and the first sub-oxide layer 328a and the second sub-oxide layer 328b constitute the oxide layer 328;

As shown in FIG. 15e , the trench 322 is filled with semiconductor material to form the gate electrode 324 .

Optionally, filling the trench 322 with a semiconductor material, the method for forming the gate 324 further includes:

As shown in FIG. 16a, the trench 322 is filled with a first semiconductor material, and the first semiconductor material above the protruding portion 322b is removed to form a first portion of the gate electrode 324a located in the protruding portion 322b;

As shown in FIG. 16b, an interconnection structure 324c is formed on the surface of the first part of the gate electrode 324a;

As shown in FIG. 16c, the surface of the interconnect structure 324c is filled with a second semiconductor material to form a second portion of the gate electrode 324b located in the main body portion 322a.

For the method for forming a semiconductor device provided by the above embodiments, the semiconductor device provided by any of the above embodiments can be formed, which has all the beneficial effects of the above semiconductor device, and details are not described herein again.

A third aspect of the present application provides an electronic device, including the semiconductor device described in any of the foregoing embodiments and a controller; the controller is configured to control the on or off of the semiconductor device. The above-mentioned electronic devices may include terminal devices using batteries, such as mobile phones and/or tablet computers. Specifically, the above-mentioned semiconductor devices can be installed in electrical signal control circuits such as charge control, discharge control, overvoltage protection, and/or overcurrent protection in electronic equipment, so as to improve the reliability of the electrical signal control process and improve the reliability of the corresponding electronic equipment. the goal of.

A fourth aspect of the present application provides a fast charging circuit, including the semiconductor device and the controller described in any of the above embodiments, wherein the semiconductor device adopts a common source solution, which can block the diode inversion path in the body, prevent inversion, and has a high The reliability of the fast charging circuit can be improved.

While the application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular with respect to the various functions performed by the above-described components, the terms used to describe such components are intended to correspond to any component that performs the specified function of the component (eg, which is functionally equivalent) (eg, which is functionally equivalent) (unless otherwise indicated) , even if it is not structurally equivalent to the disclosed structure that performs the functions of the exemplary implementations of the specification shown herein.

That is, the above descriptions are only the embodiments of the present application, which are not intended to limit the scope of the patent of the present application. Any equivalent structure or equivalent process transformation made by using the contents of the description and drawings of the present application, such as the technical features between the embodiments Combining with each other, or directly or indirectly used in other related technical fields, are also included in the scope of patent protection of this application.

In addition, for structural elements with the same or similar characteristics, the present application may use the same or different reference numerals to identify them. In addition, the terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, features defined as "first", "second" may expressly or implicitly include one or more features. In the description of the present application, "plurality" means two or more, unless otherwise expressly and specifically defined.

The above description is presented in the present application to enable any person skilled in the art to make and use the present application. In the above description, various details are set forth for the purpose of explanation. It is to be understood that one of ordinary skill in the art can realize that the present application may be practiced without the use of these specific details. In other instances, well-known structures and procedures have not been described in detail so as not to obscure the description of the present application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown but is to be accorded the widest scope consistent with the principles and features disclosed herein.

Claims (23)

1. A semiconductor device, characterized in that the semiconductor device comprises: a substrate, in which a source layer is formed; a plurality of discrete gate structures located in the substrate, the bottom of the gate structure is located on the surface of the source layer; A plurality of drains are located in the substrate on both sides of the top of the gate structure, and each of the drains is located between two adjacent gates. 2 . The semiconductor device according to claim 1 , wherein the semiconductor device further comprises: a source connection structure electrically connected to the source layer. 3 . 3 . The semiconductor device according to claim 1 , wherein the plurality of gate structures comprises a plurality of first gate structures and a plurality of second gate structures, and the drains located between adjacent first gate structures are: 4 . the first drain, the drain located between the adjacent second gate structures is the second drain; The semiconductor device further includes: a first drain connection structure interconnected with the first drain; and a second drain connection structure interconnected with the second drain. 4. The semiconductor device according to claim 3, wherein the semiconductor device further comprises: a dielectric layer on the surface of the substrate; The source connection structure includes: a first conductive plug located in the dielectric layer and a source connection region located on the surface of the dielectric layer; The first drain connection structure includes: a second conductive plug located in the dielectric layer and a first drain connection region located on the surface of the dielectric layer, and the second conductive plug is connected to the first drain between the connection region and each corresponding first drain; the second drain connection structure includes: a third conductive plug located in the dielectric layer and a second drain connection region located on the surface of the dielectric layer, so The third conductive plugs are connected between the second drain connection regions and the corresponding second drains. 5 . The semiconductor device of claim 3 , wherein the semiconductor device further comprises: a source connection portion between the first gate structure and the second gate structure, the first gate structure A conductive plug connects the source connection portion and the source connection region. 6 . The semiconductor device according to claim 4 , wherein the semiconductor device further comprises: covering the dielectric layer, the first drain connection region, the second drain connection region and the a passivation layer of the source connection region, the passivation layer having a first opening exposing the first drain connection region, the second drain connection region and the source connection Interconnection of regions. 7 . The semiconductor device of claim 2 , wherein the source connection structure is disposed on the backside of the substrate. 8 . 8. The semiconductor device according to claim 1, wherein the gate structure comprises: a gate and a gate dielectric layer between the gate and the substrate. 9 . The semiconductor device of claim 8 , wherein the gate comprises a first portion of the gate at the top and a second portion of the gate at the bottom; the first portion of the gate and the second portion gate interconnect. 10 . The semiconductor device of claim 1 , wherein the substrate further comprises a doping layer; the gate structure and the drain structure are formed in the doping layer. 11 . 11. A method for forming a semiconductor device, wherein the forming method comprises: providing a substrate, the substrate including a source layer and a doped layer on the surface of the source layer; A plurality of gates are formed in the doped layer, and drains are formed between two adjacent gates. 12. The method for forming a semiconductor device according to claim 11, wherein the plurality of gate structures comprises a plurality of first gate structures and a plurality of second gate structures, located between adjacent first gate structures The drains between the adjacent second gate structures are the first drains, and the drains between the adjacent second gate structures are the second drains. 13. The method for forming a semiconductor device according to claim 12, wherein the forming method further comprises: Within the doped layer, a source connection portion connecting the source layer is formed, and the source connection portion is located between the first gate structure and the second gate structure. 14. The method for forming a semiconductor device according to claim 13, wherein the method for forming the source connection portion comprises: Digging a hole between the first gate structure and the second gate structure to form a first through hole exposing the source layer; Filling the first through hole with source material to obtain the source connection portion. 15. The method for forming a semiconductor device according to claim 14, wherein the forming method further comprises: After forming the drains, a source connection structure is formed to connect the source connection parts, and a first drain connection structure of each of the first drains and a second drain connection structure of each of the first drains are formed . 16. The method for forming a semiconductor device according to claim 14, wherein the method for forming the source connection structure, the first drain connection structure and the second drain connection structure comprises: forming a dielectric layer on the surface of the doped layer; The dielectric layer is etched to form second through holes corresponding to the source connection portion, each of the first drains and each of the second drains, and conductive material is filled into each of the second through holes to form all the second through holes. a first conductive plug corresponding to the source connection portion, a second conductive plug corresponding to each of the first drains, and a third conductive plug corresponding to each of the second drains; A conductive layer is formed on the surface of the dielectric layer, and the conductive layer is patterned to form a source connection region connected to the first conductive plug, a first drain connection region connected to each second conductive plug, and a first drain connection region connected to each of the first conductive plugs. The second drain connection region of the three conductive plugs. 17. The method of forming a semiconductor device according to claim 16, further comprising: forming a passivation layer covering the dielectric layer, the first drain connection region, the second drain connection region and the source connection region; the passivation layer has a first opening, the first Openings expose interconnection portions of the first drain connection region, the second drain connection region, and the source connection region. 18. The method for forming a semiconductor device according to claim 13, wherein the method for forming the substrate comprises: providing a substrate, and doping the inside of the substrate to form the source layer and the doping layer on the surface of the source layer; Alternatively, a substrate is provided, a surface of the substrate is doped to form a source layer on the surface of the substrate, and a doped layer is epitaxially formed on the surface of the source layer. 19. The method for forming a semiconductor device according to claim 18, wherein the forming method further comprises: etching the back side of the substrate to form a first opening exposing the back side of the source layer part; A source connection structure is formed in the first opening. 20. The method for forming a semiconductor device according to claim 11, wherein the method for forming a plurality of gates in the doped layer further comprises: etching the doped layer to form a plurality of trenches, forming an oxide layer on the sidewalls of each of the trenches, and filling each of the trenches with a semiconductor material to form a gate; Using the surface of the doped layer as a stop layer, a planarization process is performed. 21. The method for forming a semiconductor device according to claim 20, wherein the doped layer is etched to form a plurality of trenches, an oxide layer is formed on the sidewalls of each of the trenches, and an oxide layer is formed on the sidewalls of each of the trenches. The trench is filled with semiconductor material, and the method for forming a gate further includes: etching the doped layer to form the main body of the trench; forming a first sub-oxide layer on the sidewall of the main body; Etching from the bottom of the main body toward the substrate to form the protruding portion of the trench, and the main body portion and the protruding portion constitute the trench; A second sub-oxide layer is formed on the sidewall of the trench, and the first sub-oxide layer and the second sub-oxide layer constitute the oxide layer; The trench is filled with semiconductor material to form a gate. 22. The method for forming a semiconductor device according to claim 21, wherein the method for filling the trench with a semiconductor material and forming a gate further comprises: Filling the trench with a first semiconductor material, and removing the first semiconductor material above the protruding portion to form a first partial gate located in the protruding portion; forming an interconnection structure on the surface of the first part of the gate electrode; A second semiconductor material is filled on the surface of the interconnect structure to form a second portion of the gate located in the body portion. 23. An electronic device, comprising the semiconductor device according to any one of claims 1 to 10 and a controller; the controller is used to control the on or off of the semiconductor device.

Images