CN115020259B - Semiconductor structure and packaging method thereof - Google Patents
Semiconductor structure and packaging method thereof Download PDFInfo
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- CN115020259B CN115020259B CN202210739444.1A CN202210739444A CN115020259B CN 115020259 B CN115020259 B CN 115020259B CN 202210739444 A CN202210739444 A CN 202210739444A CN 115020259 B CN115020259 B CN 115020259B
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 15
- 229910000679 solder Inorganic materials 0.000 claims abstract description 146
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 68
- 239000002184 metal Substances 0.000 claims abstract description 44
- 229910052751 metal Inorganic materials 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 238000003466 welding Methods 0.000 claims abstract description 12
- 238000003825 pressing Methods 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 230000008642 heat stress Effects 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000010309 melting process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/1605—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/1605—Shape
- H01L2224/1607—Shape of bonding interfaces, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
The invention discloses a semiconductor structure and a packaging method thereof, comprising the steps of providing a substrate with a first surface and a second surface which are oppositely arranged, wherein the first surface is provided with a solder bump, and the second surface is provided with a metal convex layer; forming a photoresist layer I on the second surface, wherein the photoresist layer I is provided with a first groove exposing the top of the metal convex layer; providing a chip with a first upper surface and a second lower surface which are opposite to each other, wherein the first upper surface is provided with a bonding pad, and the upper surface of each bonding pad is correspondingly provided with a conductive connecting layer; forming a photoresist layer II on the first upper surface and the conductive connecting layer, wherein the photoresist layer II is provided with a second groove exposing the top of the conductive connecting layer; a conductive sheet is arranged in the second groove, and one side of the conductive sheet opposite to the conductive connecting layer is provided with a notch for accommodating the solder bump; and bonding and connecting the conductive sheet of the chip and the metal convex layer of the substrate. The invention uses the shape of the conductive sheet to clamp and position the chip during flip-chip welding, thereby improving the production yield.
Description
Technical Field
The invention belongs to the technical field of semiconductor manufacturing, and particularly relates to a semiconductor structure and a packaging method thereof.
Background
The flip chip technology has been widely used due to the development of integration and high performance miniaturization of semiconductors. In chinese patent (application number 2005101038187, publication date 2008.07.02) a semiconductor device and a method of manufacturing the same are disclosed, as shown in fig. 1, the semiconductor device 10 has a flip chip bonding structure including a microchip 11 and a substrate 13, a first electrode pad 12 on the microchip 11 is electrically connected to a second electrode pad 14 on the substrate 13 through a first low-melting spot welding layer 16, a solder bump 15 and a second low-melting solder layer 17, and a gap portion between the microchip 11 and the substrate 13 is filled with a sealing resin 18. When the technology is adopted to flip-chip bond the chip, the adjacent solder bumps 15 are easy to have the short circuit problem, and meanwhile, when the substrate or the chip is warped due to the effect of heat stress, the virtual joint problem is easy to occur between the solder bumps and the corresponding second electrode pads, and in addition, the problem of shift, offset or inclination in the chip bonding process is easy to occur due to uneven pressing force of the solder bumps or the chip.
In chinese patent (application number 2019104776156, publication date: 2019.10.01), a semiconductor bonding packaging method is disclosed, as shown in fig. 2, a bonding pad 31 of a chip 30 is connected with a metal bump 11 of a substrate 10 through a functional bump 33 and a solder 34 by a thermocompression bonding method, which solves the problem of shorting between adjacent solder balls, but there is also a problem that when the substrate or the chip is warped, the solder ball is in virtual connection with a corresponding bonding pad, and meanwhile, the manufacturing process also requires a special jig for lamination, so that the cost is high.
Disclosure of Invention
The invention provides a semiconductor structure and a packaging method thereof aiming at the technical problems. In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a method of packaging a semiconductor structure, comprising the steps of:
s1, providing a substrate, wherein the substrate is provided with a first surface and a second surface which are oppositely arranged, a plurality of solder bumps are arranged on the first surface, and a plurality of metal convex layers are arranged on the second surface;
s2, forming a photoresist layer I on the second surface, wherein the photoresist layer I is provided with a first groove exposing the top of the metal convex layer;
s3, providing a chip, wherein the chip is provided with a first upper surface and a second lower surface which are opposite to each other, a plurality of bonding pads are arranged on the first upper surface, and a conductive connecting layer is correspondingly arranged on the upper surface of each bonding pad;
s4, forming a photoresist layer II on the first upper surface and the conductive connecting layer, wherein the photoresist layer II is provided with a second groove exposing the top of the conductive connecting layer;
s5, arranging a conductive sheet in the second groove, wherein a notch for accommodating a solder bump is formed on one side of the conductive sheet opposite to the conductive connection layer;
s6, bonding and connecting the conductive sheet of the chip and the metal convex layer of the substrate by a hot-press bonding method.
The step S5 includes the steps of:
s5.1, providing solder pads, and respectively placing the solder pads on the second grooves so that at least two opposite sides of the solder pads are lapped on a photoresist layer II at the periphery of the second grooves;
s5.2, placing the conductive sheet on the solder pad, wherein the conductive sheet is positioned right above the second groove, and pressing the conductive sheet downwards to bend the solder pad so as to position and clamp the conductive sheet;
and S5.3, heating the solder pad to enable the solder pad to be melted into solder and reflow to the bottom of the second groove, and further welding and fixing the conductive sheet and the conductive connecting layer.
Preferably, the step S5 may also include the following steps:
s5.1a, etching a pad placement groove which is consistent with the size of the solder pad on the photoresist layer II, wherein the size of the pad placement groove in the length direction is larger than the length of the second groove, or the size of the pad placement groove in the width direction is larger than the width of the second groove;
s5.1b, providing a solder pad, and placing the solder pad in a pad placing groove so that at least two opposite sides of the solder pad are lapped on a photoresist layer II where the pad placing groove is located;
s5.2, placing the conductive sheet on the solder pad, wherein the conductive sheet is positioned right above the second groove, and pressing the conductive sheet downwards to bend the solder pad so as to position and clamp the conductive sheet;
and S5.3, heating the solder pad to enable the solder pad to be melted into solder and reflow to the bottom of the second groove, and further welding and fixing the conductive sheet and the conductive connecting layer.
In order to facilitate positioning of the conductive sheet, the length of the solder pad is smaller than the length of the second groove and the width of the solder pad is larger than the width of the second groove, or the length of the solder pad is larger than the length of the second groove and the width of the solder pad is smaller than the width of the second groove.
To avoid solder overflow, the thickness of the solder pad is not more than 1/3 of the depth of the second recess.
The length of the conductive sheet is smaller than or equal to the length of the second groove, and the width of the conductive sheet is smaller than or equal to the width of the second groove, so that the conductive sheet can be placed conveniently.
The total thickness of the metal convex layer, the solder bump and the conductive sheet does not exceed the total thickness of the photoresist layer I and the photoresist layer II, and the thickness of the photoresist layer II is higher than the height of the conductive sheet and lower than the total height of the conductive sheet and the solder bump.
A semiconductor structure comprises at least one semiconductor module, and a plurality of semiconductor modules are connected through a substrate in each module; each semiconductor module includes:
the substrate is provided with a first surface and a second surface which are oppositely arranged, a plurality of metal convex layers are arranged on the second surface, a photoresist layer I is arranged between the adjacent metal convex layers, and a first groove surrounded by the photoresist layer I and the metal convex layers is arranged at the upper part of the metal convex layers;
the chip is provided with a first upper surface and a second lower surface which are oppositely arranged, a plurality of bonding pads are arranged on the first upper surface, a conductive connecting layer is correspondingly arranged on the upper surface of each bonding pad, a photoresist layer II is arranged between adjacent conductive connecting layers, and a second groove formed by the photoresist layer II and the conductive connecting layers in a surrounding manner is arranged at the upper part of each conductive connecting layer;
the conductive sheet is arranged in the second groove, one side of the conductive sheet opposite to the conductive connecting layer is provided with a notch matched with the solder bump in shape, and the conductive connecting layer is connected with the metal convex layer through the conductive sheet and the solder bump.
The total thickness of the metal convex layer, the solder bump and the conductive sheet does not exceed the total thickness of the photoresist layer I and the photoresist layer II, and the thickness of the photoresist layer II is higher than the height of the conductive sheet and lower than the total height of the conductive sheet and the solder bump.
The invention has the beneficial effects that:
by arranging the conductive sheet with the shape matched with the solder bump, the other side of the conductive sheet is welded with the conductive connecting layer through the solder pad, so that the clamping and positioning of the flip chip welding of the chip are realized through the shape of the conductive sheet, the problems of shifting, shifting or tilting in the chip welding process are avoided, the manufacturing yield of a semiconductor is improved, and the phenomena of shifting and off-welding are reduced; the pad placing groove can play a role in positioning the solder pad, and further, the conductive sheet is better positioned and clamped through the solder pad, after the conductive sheet and the solder pad are subjected to high-temperature reflow, the electric connection cohesiveness between the solder bump and the substrate can be improved, the problems of virtual connection and virtual soldering are effectively solved, the technological process of a semiconductor is further improved, and the production yield is improved.
Meanwhile, when the chip is bonded with the substrate, the arch-like structure of the conducting strip can decompose mechanical force in the hot pressing process, so that pressure in the direction perpendicular to the substrate and the chip is reduced, warpage in the direction of the substrate and the chip is further reduced, poor disconnection caused by back warpage is further reduced, and packaging quality is improved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a semiconductor device in the prior art.
Fig. 2 is a schematic structural diagram of another semiconductor device in the prior art.
Fig. 3 is a cross-sectional view of a substrate.
Fig. 4 is a cross-sectional view of a first recess formed in a substrate.
Fig. 5 is a cross-sectional view of a chip.
Fig. 6-8 are schematic cross-sectional views of a process of forming a second groove.
Fig. 9 is a top view and corresponding cross-sectional view of the gasket groove after formation.
Fig. 10 is a top view and corresponding cross-sectional view of the placement of solder pads directly on photoresist layer II.
Fig. 11 is a top view and corresponding cross-sectional view of placement of solder pads on the pad placement groove.
Fig. 12 is a top view and corresponding cross-sectional view of a conductive sheet placed over the solder pad of fig. 10.
Fig. 13 is a top view and corresponding cross-sectional view of a conductive sheet placed over the solder pad of fig. 11.
Fig. 14 is a schematic cross-sectional view of the conductive sheet after being formed in the second recess.
Fig. 15 is a schematic cross-sectional view of a conductive sheet after solder bumps have been added.
Fig. 16 is a schematic cross-sectional view of the chip after connection with the substrate.
Is a schematic cross-sectional view illustrating the process of manufacturing a semiconductor of the present invention.
In the figure, 1 is a substrate, 1-1 is a solder bump, 2 is a photoresist layer I,3 is a metal convex layer, 4 is a solder bump, 5 is a photoresist layer II,6 is a conductive sheet, 7 is a conductive connecting layer, 8 is a bonding pad, 9 is a chip, 101 is a first mask layer, 111 is a first groove, 112 is a second groove, 113 is a pad placement groove, and 93 is a solder pad.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without any inventive effort, are intended to be within the scope of the invention.
Example 1: a method of packaging a semiconductor, comprising the steps of:
s1, providing a substrate, as shown in FIG. 3, wherein the substrate 1 is provided with a first surface and a second surface which are oppositely arranged, a plurality of solder bumps 1-1 are arranged on the first surface, and a plurality of metal convex layers 3 are arranged on the second surface;
in step S1, the substrate 1 may be a PCB board or other substrate.
S2, forming a photoresist layer I2 on the second surface, wherein the photoresist layer I2 is provided with a first groove 111 exposing the top of the metal convex layer;
as shown in fig. 4, a photoresist layer is first coated on the second surface of the substrate 1, the photoresist layer is covered on the second surface of the substrate, and the upper surface of the photoresist layer is higher than the upper surface of the metal convex layer. The patterned photoresist layer I is formed by using an exposing and developing method, the top of the metal convex layer is exposed, and the side wall of the photoresist layer I and the upper surface of the metal convex layer form a first groove 111, so that the subsequent flip-chip bonding with the chip is facilitated.
S3, providing a chip, wherein the chip 9 is provided with a first upper surface and a second lower surface which are opposite to each other, a plurality of bonding pads 8 are arranged on the first upper surface, and a conductive connecting layer 7 is correspondingly arranged on the upper surface of each bonding pad;
specifically, a chip 9 is provided, the chip 9 has a first upper surface and a second lower surface which are opposite, a plurality of bonding pads 8 are arranged on the first upper surface, a metal layer is covered on the first upper surface and all bonding pads, a photoresist layer is coated on the metal layer, then the metal layer between two adjacent bonding pads is exposed through illumination and development, then the metal layer between the two bonding pads is etched to form a conductive connecting layer 7 which is positioned right above the bonding pads, the photoresist on the conductive connecting layer is removed, and the size of the conductive connecting layer is smaller than that of the bonding pads.
S4, forming a photoresist layer II5 on the first upper surface and the conductive connecting layer 7, wherein the photoresist layer II5 is provided with a second groove 112 exposing the top of the conductive connecting layer;
as shown in fig. 6-8, a photoresist layer II is covered on the first upper surfaces of the conductive connection layer 7 and the chip 9, a patterned first mask layer 101 is formed on the photoresist layer II, the photoresist layer II is etched by taking the first mask layer as a mask and the top of the conductive connection layer 7 is exposed, and a second groove 112 is formed on the sidewall of the photoresist layer II and the upper surface of the conductive connection layer, so as to facilitate flip-chip electrical connection with the substrate. The photoresist layer II between the two conductive connection layers achieves electrical isolation between adjacent pads.
S5, as shown in FIG. 14, placing a conductive sheet 6 in the second groove 112, wherein a side of the conductive sheet 6 opposite to the conductive connection layer is provided with a notch for accommodating the solder bump 4;
as shown in fig. 9 to 13, the step S5 includes the steps of:
s5.1, as shown in fig. 10, providing solder pads 93, and placing each solder pad 93 on the second groove 112, respectively, such that at least two opposite sides of the solder pad 93 overlap the photoresist layer II5 at the periphery of the second groove 112;
preferably, the step S5.1 may also include the following steps:
a. as shown in fig. 9, a pad placement groove 113 corresponding to the size of the solder pad 93 is etched on the photoresist layer II5, the size in the length direction or the size in the width direction of the pad placement groove 113 being larger than the corresponding size of the second groove 112;
b. as shown in fig. 11, a solder pad 93 is provided, and the solder pad 93 is placed in the pad placement groove 113 such that at least two opposite sides of the solder pad 93 overlap the photoresist layer II5 in which the pad placement groove 113 is located;
the solder pad is cuboid, and the size setting conditions of the solder pad are as follows: (1) the length of the solder pad is smaller than the length of the second groove, the width of the solder pad is larger than the width of the second groove, or the length of the solder pad is larger than the length of the second groove, and the width of the solder pad is smaller than the width of the second groove; (2) the thickness of the solder pad is not greater than 1/3 of the depth of the second groove, so that the solder pad can be correspondingly carried on the photoresist layer II around the second groove when being tiled above the second groove, and the conductive sheet is prevented from exposing the second groove when the solder pad is melted, thereby being convenient for placing solder bumps. In this embodiment, the length L1 of the solder pad is smaller than the length L2 of the second groove, and the width W1 of the solder pad is larger than the width W2 of the second groove.
In this embodiment, the pad placement groove is a square groove, and the center of the square groove coincides with the center of the second groove, so that both sides of the solder pad can uniformly and stably clamp the conductive sheet. The adjacent pad placement grooves are not connected, so that the error connection between the adjacent pads in the melting process is avoided, and the pad placement grooves can play a role in positioning the solder pads. The solder bump is made of tin, and the conductive sheet is made of copper or alloy thereof.
S5.2, as shown in fig. 12 or 13, placing the conductive sheet 6 on the solder pad 93 with the conductive sheet 6 directly above the second recess 112, pressing down the conductive sheet 6 so that the solder pad 93 is bent to position and temporarily clamp the conductive sheet;
preferably, the length L3 of the conductive sheet is smaller than or equal to the length L2 of the second groove, and the width W3 of the conductive sheet is smaller than or equal to the width W2 of the second groove, so that the conductive sheet can be placed in the second groove, and the height of the conductive sheet is smaller than or equal to half of the depth of the second groove, so as to ensure the stability of the solder ball when the solder ball is placed later. In this embodiment, the length L3 of the conductive sheet is slightly smaller than the length L2 of the second groove, and the width W3 of the conductive sheet is slightly smaller than the width W2 of the second groove (not shown in fig. 10). Each conducting strip is correspondingly placed on each solder pad, adjacent solder pads are not connected, the bottoms of the conducting strips are planar, the conducting strips can be well attached to the bottoms of the second grooves, notches are formed in the tops of the conducting strips, the bottoms of the notches are located in the middle of the conducting strips, the shapes of the notches are identical to those of solder bumps, namely solder balls, so that the notches can well bear and contain the solder balls, the clamping and positioning of the chips in the flip-chip placement and welding processes are facilitated, the problem that the chips are shifted, offset or inclined in the welding process due to uneven pressure of the solder balls or the chips is solved, and meanwhile, the problem that the cost is high is solved because special jigs are not needed for the conducting strips. The solder pad can play a role in positioning the conductive sheet, the conductive sheet is prevented from shifting in the welding process, the conductive sheet is pressed down, the solder pad is deformed under pressure and is bent towards the direction of the second groove until the conductive sheet is clamped. The solder pad may be bent in a V-shape, or a U-shape.
Preferably, the shape of the solder pad may be any shape and material, so long as the conductive sheet can be positioned and temporarily clamped after being deformed by compression, and the solder is melted into solder after being heated and reflowed to the bottom of the second groove, so that the conductive sheet and the conductive connection layer are welded, and the electrical connection between the conductive sheet and the conductive connection layer is not affected.
S5.3, as shown in fig. 14 and 15, the solder pad 93 is heated, so that the solder pad is melted into solder and reflowed to the bottom of the second groove 112, and the conductive sheet 6 and the conductive connection layer 7 are soldered and fixed.
The chip on which the solder pad and the conductive sheet are placed is heated and subjected to high-temperature reflow treatment, the solder pad is melted into fluid at high temperature to become solder, and the solder is reflowed to the bottom of the second groove, namely the surface of the conductive connecting layer opposite to the second groove and solidified due to the material characteristics of the solder, such as small intermolecular distance, large intermolecular attraction and large surface tension, so that the conductive sheet can be welded and fixed with the conductive connecting layer, and the conductive sheet is formed on the surface of the conductive connecting layer and part of the side wall of the second groove due to the surface tension of the conductive sheet after becoming semi-cured conductive material, therefore, the semi-cured layer formed by the high-temperature reflow of the conductive sheet is equivalent to a metal layer under the UBM (UBM) bump, the electric connection adhesion between the solder ball and the chip is improved, and the problems of virtual connection and virtual soldering are further improved. The conductive sheet is provided with solder bumps 4, so as to avoid bridging between adjacent conductive sheets caused by overflow of solder of the solder bumps, the total thickness of the metal convex layer, the solder bumps and the conductive sheet does not exceed the total thickness of the photoresist layer I and the photoresist layer II, and the thickness of the photoresist layer II is higher than the height of the conductive sheet 6 and lower than the total height of the conductive sheet 6 and the solder bumps.
S6, as shown in fig. 16, the conductive sheet 6 of the chip and the metal bump layer 3 of the substrate are bonded and connected by thermocompression bonding.
The conductive sheet of the chip is connected with the metal convex layer of the substrate through the solder bump, under the hot-press bonding process, the solder bump is melted to connect the conductive sheet with the metal convex layer, and then the melted solder bump is subjected to cold-setting molding, so that stable electric connection among the bonding pad of the chip, the conductive connecting layer, the conductive sheet and the metal convex layer of the substrate is realized. The substrate has more metal convex layers, one or more identical or different chips can be connected with the substrate, the wafer integration process is realized, the packaging efficiency is improved, and the element size is reduced.
In this embodiment, the lengths and widths of the first groove and the second groove are consistent, so as to facilitate positioning and fixing the chip.
Example 2: a semiconductor structure comprises at least one semiconductor module, and a plurality of semiconductor modules are connected through a substrate in each module; each semiconductor module includes:
the substrate is provided with a first surface and a second surface which are oppositely arranged, a plurality of metal convex layers are arranged on the second surface, a photoresist layer I is arranged between the adjacent metal convex layers, and a first groove surrounded by the photoresist layer I and the metal convex layers is arranged at the upper part of the metal convex layers;
the chip is provided with a first upper surface and a second lower surface which are oppositely arranged, a plurality of bonding pads are arranged on the first upper surface, a conductive connecting layer is correspondingly arranged on the upper surface of each bonding pad, a photoresist layer II is arranged between adjacent conductive connecting layers, and a second groove formed by the photoresist layer II and the conductive connecting layers in a surrounding manner is arranged at the upper part of each conductive connecting layer;
the conductive sheet is arranged in the second groove, one side of the conductive sheet opposite to the conductive connecting layer is provided with a notch matched with the solder bump in shape, and the conductive connecting layer is connected with the metal convex layer through the conductive sheet and the solder bump.
The total thickness of the metal convex layer, the solder bump and the conductive sheet does not exceed the total thickness of the photoresist layer I and the photoresist layer II, and the thickness of the photoresist layer II is higher than the height of the conductive sheet and lower than the total height of the conductive sheet and the solder bump.
In this embodiment, the manufacturing method and the structural requirement of each structure are as shown in embodiment 1, and a solder pad is further disposed between the conductive sheet and the conductive connection layer, and the structure and the setting method are as shown in embodiment 1.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the invention.
Claims (8)
1. A method of packaging a semiconductor structure, comprising the steps of:
s1, providing a substrate, wherein the substrate is provided with a first surface and a second surface which are oppositely arranged, a plurality of solder bumps are arranged on the first surface, and a plurality of metal convex layers are arranged on the second surface;
s2, forming a photoresist layer I on the second surface, wherein the photoresist layer I is provided with a first groove exposing the top of the metal convex layer;
s3, providing a chip, wherein the chip is provided with a first upper surface and a second lower surface which are opposite to each other, a plurality of bonding pads are arranged on the first upper surface, and a conductive connecting layer is correspondingly arranged on the upper surface of each bonding pad;
s4, forming a photoresist layer II on the first upper surface and the conductive connecting layer, wherein the photoresist layer II is provided with a second groove exposing the top of the conductive connecting layer;
s5, arranging a conductive sheet in the second groove, wherein a notch for accommodating a solder bump is formed on one side of the conductive sheet opposite to the conductive connection layer;
s6, bonding and connecting the conductive sheet of the chip and the metal convex layer of the substrate by a hot-press bonding method;
the step S5 includes the steps of:
s5.1, providing solder pads, and respectively placing the solder pads on the second grooves so that at least two opposite sides of the solder pads are lapped on a photoresist layer II at the periphery of the second grooves;
s5.2, placing the conductive sheet on the solder pad, wherein the conductive sheet is positioned right above the second groove, and pressing the conductive sheet downwards to bend the solder pad so as to position and clamp the conductive sheet;
and S5.3, heating the solder pad to enable the solder pad to be melted into solder and reflow to the bottom of the second groove, and further welding and fixing the conductive sheet and the conductive connecting layer.
2. The method of packaging a semiconductor structure of claim 1, wherein the solder pad has a length less than a length of the second recess and a width greater than a width of the second recess, or wherein the solder pad has a length greater than a length of the second recess and a width less than a width of the second recess.
3. The method of packaging a semiconductor structure of claim 1, wherein a thickness of the solder pad is no greater than 1/3 of a depth of the second recess.
4. The method of claim 1, wherein the conductive sheet has a length less than or equal to a length of the second recess and a width less than or equal to a width of the second recess.
5. The method of claim 4, wherein the total thickness of the metal bump layer, the solder bump, and the conductive pad does not exceed the total thickness of the photoresist layer I and the photoresist layer II, and the thickness of the photoresist layer II is higher than the height of the conductive pad and lower than the total height of the conductive pad and the solder bump.
6. A method of packaging a semiconductor structure, comprising the steps of:
s1, providing a substrate, wherein the substrate is provided with a first surface and a second surface which are oppositely arranged, a plurality of solder bumps are arranged on the first surface, and a plurality of metal convex layers are arranged on the second surface;
s2, forming a photoresist layer I on the second surface, wherein the photoresist layer I is provided with a first groove exposing the top of the metal convex layer;
s3, providing a chip, wherein the chip is provided with a first upper surface and a second lower surface which are opposite to each other, a plurality of bonding pads are arranged on the first upper surface, and a conductive connecting layer is correspondingly arranged on the upper surface of each bonding pad;
s4, forming a photoresist layer II on the first upper surface and the conductive connecting layer, wherein the photoresist layer II is provided with a second groove exposing the top of the conductive connecting layer;
s5, arranging a conductive sheet in the second groove, wherein a notch for accommodating a solder bump is formed on one side of the conductive sheet opposite to the conductive connection layer;
s6, bonding and connecting the conductive sheet of the chip and the metal convex layer of the substrate by a hot-press bonding method;
the step S5 includes the steps of:
s5.1a, etching a pad placement groove which is consistent with the size of the solder pad on the photoresist layer II, wherein the size of the pad placement groove in the length direction is larger than the length of the second groove, or the size of the pad placement groove in the width direction is larger than the width of the second groove;
s5.1b, providing a solder pad, and placing the solder pad in a pad placing groove so that at least two opposite sides of the solder pad are lapped on a photoresist layer II where the pad placing groove is located;
s5.2, placing the conductive sheet on the solder pad, wherein the conductive sheet is positioned right above the second groove, and pressing the conductive sheet downwards to bend the solder pad so as to position and clamp the conductive sheet;
and S5.3, heating the solder pad to enable the solder pad to be melted into solder and reflow to the bottom of the second groove, and further welding and fixing the conductive sheet and the conductive connecting layer.
7. The method of claim 6, wherein the solder pad has a length less than a length of the second recess and a width greater than a width of the second recess, or wherein the solder pad has a length greater than a length of the second recess and a width less than a width of the second recess.
8. The method of packaging a semiconductor structure of claim 6, wherein a thickness of the solder pad is no greater than 1/3 of a depth of the second recess.
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| CN104576547A (en) * | 2013-10-25 | 2015-04-29 | Lg伊诺特有限公司 | Printed circuit board and manufacturing method thereof and semiconductor package using the same |
| CN110299295A (en) * | 2019-06-03 | 2019-10-01 | 苏州通富超威半导体有限公司 | Bonding semiconductor packaging method |
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| US7417305B2 (en) * | 2004-08-26 | 2008-08-26 | Micron Technology, Inc. | Electronic devices at the wafer level having front side and edge protection material and systems including the devices |
| IT201700071775A1 (en) * | 2017-06-27 | 2018-12-27 | St Microelectronics Srl | PROCESS OF MANUFACTURING OF A FLIP CHIP INTEGRATED AND CORRESPONDENT FLIP CHIP PACKAGE INTEGRATED CIRCUIT FLIP CHIP |
| US11094658B2 (en) * | 2019-05-22 | 2021-08-17 | Lenovo (Singapore) Pte. Ltd. | Substrate, electronic substrate, and method for producing electronic substrate |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104576547A (en) * | 2013-10-25 | 2015-04-29 | Lg伊诺特有限公司 | Printed circuit board and manufacturing method thereof and semiconductor package using the same |
| CN110299295A (en) * | 2019-06-03 | 2019-10-01 | 苏州通富超威半导体有限公司 | Bonding semiconductor packaging method |
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