CN115020428A - Array substrate, display panel and display device - Google Patents

Abstract

The invention discloses an array substrate, a display panel and a display device. The array substrate comprises a substrate; the first metal layer, the second metal layer, the third metal layer and the fourth metal layer are sequentially stacked on one side of the substrate in the direction away from the substrate; an insulating layer is arranged between every two adjacent metal layers; the first routing comprises a trunk line positioned on the third metal layer and a jumper wire positioned on the fourth metal layer; the jumper wire is used for connecting the trunk line; the second routing is positioned on the second metal layer; the third routing is positioned on the first metal layer; the orthographic projection of the main line of the first wire on the substrate is staggered with the orthographic projection of the second wire on the substrate and/or the orthographic projection of the third wire on the substrate. The technical scheme provided by the embodiment of the invention reduces the short circuit risk of the array substrate and improves the yield of the display panel.

Description

Array substrate, display panel and display device

technical field

The present invention relates to the field of display technology, and in particular, to an array substrate, a display panel and a display device.

Background technique

With the development of display technology, display devices are widely used, and people have higher and higher requirements for display effects. The metal traces on the array substrate of the display panel are prone to short circuit risk, which affects the yield of the display panel.

SUMMARY OF THE INVENTION

The present invention provides an array substrate, a display panel and a display device to solve the problem that the metal wires on the array substrate of the display panel are prone to short-circuit risk and affect the yield of the display panel.

According to an aspect of the present invention, an array substrate is provided, comprising:

substrate;

In the direction away from the substrate, stack the first metal layer, the second metal layer, the third metal layer and the fourth metal layer arranged on one side of the substrate in sequence;

An insulating layer is arranged between every two adjacent metal layers;

a first wiring, the first wiring includes a main line located in the third metal layer and a jumper line located in the fourth metal layer; the jumper line is used to connect the main line;

the second wiring, the second wiring is located in the second metal layer;

The third wiring, the third wiring is located in the first metal layer;

The orthographic projection of the main line of the first wiring on the substrate is staggered from the orthographic projection of the second wiring on the substrate and/or the orthographic projection of the third wiring on the substrate.

Optionally, the orthographic projection of the jumper of the first trace on the substrate at least partially overlaps with the orthographic projection of the second trace on the substrate and/or the orthographic projection of the third trace on the substrate. This arrangement further reduces the risk of short circuit between the first wiring and the second wiring or the third wiring, and further improves the yield of the display panel.

Optionally, the first trace further includes:

A branch line, the branch line is connected between the main line and the jumper line; the branch line is used to conduct the connection between the main line and the jumper line. In this way, the main line located in the third metal layer and the jumper line located in the fourth metal layer are electrically connected through the branch lines, and then the first wiring lines are connected.

Optionally, the extension direction of the jumper wire is the same as the extension direction of the trunk wire to which the jumper wire is connected. This arrangement facilitates the connection of the jumper wire with the main line, saves the length of the branch line connected between the jumper wire and the main line, makes the impedance of the first line smaller, and makes the voltage drop of the voltage signal transmitted on the first line smaller than that of the first line. Small, saves wiring space on the array substrate.

Optionally, along the extension direction of the jumper wire, the jumper wire includes a first end and a second end;

along the extension direction of the trunk line, the trunk line includes a plurality of trunk line segments arranged at intervals, and the trunk line segment includes a third end and a fourth end;

The branch line includes a first branch line and a second branch line;

The first branch line is connected between the fourth end of the main line segment and the first end of the jumper line; the second branch line is connected between the third end of the adjacent main line segment and the second end of the jumper line. This arrangement makes the technological process simple, and is convenient to save the manufacturing cost.

Optionally, the insulating layer includes:

a first insulating layer, the first insulating layer is disposed between the fourth metal layer and the third metal layer;

a second insulating layer, the second insulating layer is disposed between the second metal layer and the third metal layer;

The thickness of the first insulating layer is greater than the thickness of the second insulating layer;

Preferably, the first insulating layer includes an organic adhesive layer.

In this way, since the insulating effect of the organic adhesive layer is good, cracks are not easy to occur, and the risk of short circuit between the jumper wire of the first wiring and the second wiring or the third wiring is further reduced. In addition, the first insulating layer includes an organic adhesive layer, which can be better compatible with the existing process and reduce the manufacturing cost.

Optionally, the array substrate further includes:

at least two through holes; the through holes penetrate the first insulating layer;

The branch lines are arranged in the through holes. In this way, the jumper line and the main line can be reliably connected, the yield of the branch line can be improved, and the risk of disconnection between the branch line and the main line can be avoided.

Preferably, the branch lines are perpendicular to the main line and/or the jumper lines.

In this way, the length of the branch line is short, the resistance of the branch line can be reduced, the material of the branch line can be saved, the manufacturing process is simple, and the manufacturing cost is reduced.

Optionally, the first wiring includes multiple power lines and multiple data lines;

The second line includes a plurality of initialization lines;

The third wiring includes a plurality of light-emitting control lines and scan lines. This arrangement can better avoid the short circuit phenomenon caused by the existence of foreign objects or residual problems between the data lines, the light emitting control lines, the scan lines and the initialization lines.

In a second aspect, an embodiment of the present invention provides a display panel, including: the array substrate set forth in any item of the first aspect.

In a third aspect, an embodiment of the present invention provides a display device, including: the display panel proposed in the second aspect.

In the technical solution of the embodiment of the present invention, the first wiring includes a main line located in the third metal layer and a jumper line located in the fourth metal layer, the main line is connected through the jumper line, and the main line located in the third metal layer is located in the substrate The orthographic projection on the substrate is staggered from the orthographic projection of the second trace located on the second metal layer on the substrate and/or the orthographic projection of the third trace located on the first metal layer on the substrate, so that the orthographic projection on the substrate is located on the third metal layer The position where the orthographic projection of the main line on the substrate does not overlap with the orthographic projection of the second line located in the second metal layer and/or the third line located in the first metal layer on the substrate can be better. It avoids short circuits caused by foreign objects or residual problems between the first traces and the second traces and/or the third traces, reduces the short circuit risk of the array substrate, and improves the yield of the display panel.

It should be understood that the content described in this section is not intended to identify key or critical features of the embodiments of the invention, nor is it intended to limit the scope of the invention. Other features of the present invention will become readily understood from the following description.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort.

1 is a schematic structural diagram of a display panel provided in the prior art;

2 is a schematic structural diagram of a pixel circuit provided in the prior art;

3 is a schematic cross-sectional structure diagram of an array substrate provided by an embodiment of the present invention;

4 is a schematic diagram of a layout structure of an array substrate according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of the layout structure of the first metal layer of the array substrate in FIG. 4 according to an embodiment of the present invention;

FIG. 6 is a schematic layout structure diagram of the second metal layer of the array substrate in FIG. 4 according to an embodiment of the present invention;

7 is a schematic diagram of a layout structure of a third metal layer of the array substrate in FIG. 4 according to an embodiment of the present invention;

FIG. 8 is a schematic layout structure diagram of the fourth metal layer of the array substrate in FIG. 4 according to an embodiment of the present invention;

9 is a schematic diagram of a layout structure of a branch line of the array substrate in FIG. 4 according to an embodiment of the present invention;

10 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention;

11 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

FIG. 12 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed ways

In order to make those skilled in the art better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only Embodiments are part of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

It should be noted that the terms "first", "second" and the like in the description and claims of the present invention and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific sequence or sequence. It is to be understood that the data so used may be interchanged under appropriate circumstances such that the embodiments of the invention described herein can be practiced in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "having" and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those expressly listed Rather, those steps or units may include other steps or units not expressly listed or inherent to these processes, methods, products or devices.

As mentioned in the background art, the metal wires on the array substrate of the display panel are prone to short-circuit risk, which affects the yield of the display panel. After long-term research, the inventor found that due to the foreign matter or residual problem on the array substrate of the display panel, the metal wiring on the same layer on the array substrate is short-circuited, or the upper metal wiring and the lower metal wiring on the array substrate are short-circuited. Short circuits are prone to occur between them, resulting in yield loss problems such as poor metal wiring or burns in the display area of the display panel, affecting the yield rate of the display panel.

FIG. 1 is a schematic structural diagram of a display panel provided in the prior art. FIG. 1 exemplarily shows a situation in which the array substrate 100 is disposed in the display panel 200 . FIG. 2 is a schematic structural diagram of a pixel circuit provided in the prior art. 1 and 2 , the display panel 200 includes an array substrate 100 and a plurality of light-emitting units, and the light-emitting units include a light-emitting device D1 and its corresponding pixel circuit 1 . The array substrate 100 includes a first power supply line VDD, a second power supply line VSS and an initialization line Vref. Each pixel circuit 1 is connected to the first power supply line VDD, the second power supply line VSS and the initialization line Vref, respectively. In each light-emitting unit, the pixel circuit 1 includes a plurality of thin film transistors and storage capacitors. The thin film transistors may include a driving transistor T1 and a switching transistor. The driving transistor T1 and the light-emitting device D1 are sequentially connected to the first power supply line VDD and the second power supply line between VSS. The driving transistor T1 can generate a driving current to drive the light-emitting device D1 connected to the pixel circuit 1 to emit light, and the switching transistor mainly plays a switching role.

Referring to FIG. 1 , the array substrate 100 may further include a plurality of scan signal lines Scan 1-Scan n, a plurality of data signal lines Data 1-Data n, a plurality of light emission control signal lines EM 1-EM n, and a driving chip 300, a pixel circuit 1 is arranged in the area defined by the intersection of the scan signal line Scan and the data line Data, and the scan signal is input to the corresponding pixel circuit 1 through the scan signal line Scan, and the pixel circuit 1 is electrically connected to the scan signal line Scan. Next, the data line Data electrically connected to it is connected, and the driving chip 300 inputs a data signal to the corresponding pixel circuit 1 through the data line Data, and the voltage of the data signal corresponds to the driving voltage, which determines the light-emitting brightness of the light-emitting device D1, that is, determines the light-emitting device D1 display grayscale. It should be noted that the driving transistor, the switching transistor and the storage capacitor may have various connection relationships to form the pixel circuit 1 in various forms. The pixel circuit 1 shown in FIG. 2 is just an example, and other forms of pixel circuits, such as a 3T1C pixel circuit, a 7T1C pixel circuit, and an 8T2C pixel circuit, etc., are used, where T represents a transistor and C represents a capacitor. FIG. 2 exemplarily shows the case of a 7T1C pixel circuit, and is not a limitation to the pixel circuit 1 .

Referring to FIG. 1 and FIG. 2 , the first power line VDD may be used to transmit the first power signal, and the second power line ELVSS may be used to transmit the second power signal. The voltage on the first power supply line VDD is generally a high-level voltage, and the voltage on the second power supply line VSS is generally a low-level voltage. In the light-emitting stage, the first power supply signal on the first power supply line VDD is applied to the first pole of the driving transistor T1, and the second power supply signal on the second power supply line VSS is applied to the second pole of the light-emitting device D1, for example, the second pole The cathode, the first power supply signal and the second power supply signal serve as a power supply for the driving transistor T1 to generate a driving current, so that the driving transistor T1 generates a driving current to drive the light-emitting device D1 to emit light. The first power supply line VDD may be a signal line directly connected to one pole (eg, drain or source) of the driving transistor T1 in the pixel circuit 1 , or indirectly connected to the pixel circuit 1 through a switching transistor (eg, a light-emitting control transistor) The signal line of one pole of the driving transistor T1 in the second power supply line VSS may be a signal line connected to the cathode of the light emitting device D1. The initialization line Vref can be used to transmit an initialization signal to the pixel circuit 1. For example, the initialization line Vref can be connected to the gate of the driving transistor T1 and the storage capacitor through a switching transistor, and the initialization signal can be written into the driver through the initialization line Vref and its connected switching transistor. The gate of the transistor T1 and the storage capacitor Cst initialize the gate of the driving transistor T1 and the storage capacitor Cst to clear the residual charge of the previous frame of display and avoid affecting the next frame of display. The initialization line Vref can also be connected to the anode of the light-emitting device D1 through the switching transistor, and the initialization signal is written into the anode of the light-emitting device D1 through the initialization line Vref and the connected switching transistor, and the potential of the anode of the light-emitting device D1 is initialized to clear the The residual charge of the previous frame of display screen, to avoid affecting the next frame of display screen.

FIG. 3 is a schematic cross-sectional structure diagram of an array substrate according to an embodiment of the present invention. Referring to FIG. 3 , an array substrate 100 provided by an embodiment of the present invention includes a substrate 101 ; in a direction away from the substrate 101 , a first metal layer 10 , a second metal layer 20 , a first metal layer 10 , a second metal layer 20 , a first metal layer 10 , a second metal layer 20 , a Three metal layers 30 and a fourth metal layer 40; an insulating layer is provided between every two adjacent metal layers; the first wiring 2, the first wiring 2 includes the main line 21 located in the third metal layer 30 and the main line 21 located in the third metal layer 30. The jumper line 22 of the four metal layers 40; the jumper line 22 is used to connect the main line 21; the second line 3, the second line 3 is located in the second metal layer 20; the third line 4, the third line 4 is located in the A metal layer 10; the orthographic projection of the main line 21 of the first trace 2 on the substrate 101 and the orthographic projection of the second trace 3 on the substrate 101 and/or the orthographic projection of the third trace 4 on the substrate 101 The orthographic projection is staggered.

Specifically, the electrode of the driving transistor in the pixel circuit, such as the gate, can be arranged on the first metal layer 10, the first electrode plate of the storage capacitor can be arranged on the first metal layer 10, and the second electrode plate of the storage capacitor can be arranged on the first metal layer 10. The second metal layer 20 . The second traces 3 are disposed on the second metal layer 20 , and the second traces 3 may include power lines such as initialization lines. The third wiring 4 is disposed on the first metal layer 10 , and the third wiring 4 may include signal lines such as scan lines or light-emitting control lines. The first wiring 2 may include a data line or a power line or the like.

Since the fourth metal layer 40 is disposed on the side of the third metal layer 30 away from the substrate 101 , an insulating layer is disposed between the third metal layer 30 and the fourth metal layer 40 . By arranging that the first trace 2 includes the main line 21 located in the third metal layer 30 and the jumper 22 located in the fourth metal layer 40 , the first trace 2 can be connected to the main line 22 through the jumper 22 located in the fourth metal layer 40 . Trunk 21. In this way, on the one hand, the main lines 21 of the first wiring 2 are connected through the jumper wire 22, and on the other hand, the jumper wire 22 is connected with the third wiring 4 located in the first metal layer 10 and the second metal layer 20. The insulation distance between the second traces 3 is relatively large, so as to avoid a short circuit between the jumper wire 22 and the second trace 3 or the third trace 4 .

The orthographic projection of the main line 21 of the first trace 2 located in the third metal layer 30 on the substrate 101 is staggered from the orthographic projection of the second trace 3 on the substrate 101, so that the main line of the first trace 2 The position where the orthographic projection of 21 on the substrate 101 and the orthographic projection of the second trace 3 on the substrate 101 do not overlap, which can better avoid foreign objects or foreign objects between the first trace 2 and the second trace 3. Short circuit caused by residual problems.

The orthographic projection of the main line 21 of the first trace 2 on the substrate 101 is set to be staggered from the orthographic projection of the third trace 4 on the substrate 101, so that the main line 21 of the first trace 2 is on the substrate 101. The position where the orthographic projection and the orthographic projection of the third trace 4 on the substrate 101 do not overlap can better avoid a short circuit phenomenon caused by foreign objects or residual problems between the first trace 2 and the third trace 4 .

The orthographic projection of the main line 21 of the first trace 2 on the substrate 101 is set to be staggered from the orthographic projection of the second trace 3 on the substrate 101 and the orthographic projection of the third trace 4 on the substrate 101, so that the The orthographic projection of the main line 21 of a trace 2 on the substrate 101 does not overlap with the orthographic projection of the second trace 3 or the third trace 4 on the substrate 101, which can better avoid the first trace. A short circuit caused by foreign matter or residual problems between the wire 2 and the second wire 3 or the third wire 4.

This embodiment provides a technical solution by arranging that the first wiring 2 includes a main line 21 located in the third metal layer 30 and a jumper line 22 located in the fourth metal layer 40, and the main line 21 is connected through the jumper line 22, which is located in the third metal layer. The orthographic projection of the main line 21 of 30 on the substrate 101 is the same as the orthographic projection of the second trace 3 located in the second metal layer 20 on the substrate 101 and/or the third trace 4 located in the first metal layer 10. The orthographic projection on the substrate 101 is staggered, so that the orthographic projection of the main line 21 on the third metal layer 30 on the substrate 101 is different from that of the second trace 3 on the second metal layer 20 and/or on the first metal layer 10 The orthographic projection of the third trace 4 on the substrate 101 does not overlap, which can better avoid foreign objects or residues between the first trace 2 and the second trace 3 and/or the third trace 4 The short circuit phenomenon caused by the problem reduces the short circuit risk of the array substrate 100 and improves the yield of the display panel.

Optionally, on the basis of the above embodiment, continue to refer to FIG. 3 , the orthographic projection of the jumper wire 22 of the first trace 2 on the substrate 101 and the orthographic projection of the second trace 3 on the substrate 101 and/or Or the orthographic projections of the third traces 4 on the substrate 101 at least partially overlap.

Specifically, the main lines 21 of the first wiring 2 can be set to be connected through the jumper wire 22 located in the fourth metal layer 40 at the position where two adjacent main lines 21 are disconnected. When the orthographic projection of the first trace 2 on the substrate 101 overlaps with the orthographic projection of the second trace 3 or the third trace 4 on the substrate 101, since the jumper 22 is disposed on the fourth metal layer 40, Two insulating layers are arranged between the jumper wire 22 and the second wire 3, and three layers of insulating layers are arranged between the jumper wire 22 and the third wire 4. The orthographic projection of the second wire 3 on the substrate 101 is the same as that of the first wire. The orthographic projection of a trace 2 on the substrate 101 overlaps the position of the orthographic projection of the jumper 22 of the first trace 2 on the substrate 101 . Alternatively, the orthographic projection of the third trace 4 on the substrate 101 and the orthographic projection of the first trace 2 on the substrate 101 overlap with the orthographic projection of the jumper 22 of the first trace 2 on the substrate 101 Location. This arrangement further reduces the risk of short circuit between the first wiring 2 and the second wiring 3 or the third wiring 4, and further improves the yield of the display panel.

It should be noted that FIG. 3 exemplarily shows the orthographic projection of the jumper 22 of the first trace 2 on the substrate 101 and the orthographic projection of the second trace 3 on the substrate 101 and/or the third trace The case where the orthographic projections on the substrate 101 partially overlap is not limited here.

Optionally, on the basis of the above embodiment, referring to FIG. 3, the first wiring 2 may further include: a branch line 23, the branch line 23 is connected between the main line 21 and the jumper line 22; the branch line 23 is used for The main line 21 and the jumper line 22 are electrically connected.

Specifically, the branch wire 23 may be a metal wire of the same material as the jumper wire 22 . The branch line 23 can conduct the connection between the main line 21 located in the third metal layer 30 and the jumper line 22 located in the fourth metal layer 40 , thereby connecting the first trace 2 .

Optionally, FIG. 4 is a schematic diagram of a layout structure of an array substrate provided by an embodiment of the present invention. FIG. 5 is a schematic diagram of the layout structure of the first metal layer of the array substrate in FIG. 4 according to an embodiment of the present invention. FIG. 6 is a schematic diagram of a layout structure of a second metal layer of the array substrate in FIG. 4 according to an embodiment of the present invention. 7 is a schematic diagram of a layout structure of a third metal layer of the array substrate in FIG. 4 according to an embodiment of the present invention. FIG. 8 is a schematic diagram of a layout structure of a fourth metal layer of the array substrate in FIG. 4 according to an embodiment of the present invention. FIG. 9 is a schematic layout structure diagram of a branch line of the array substrate in FIG. 4 according to an embodiment of the present invention. On the basis of the above-mentioned embodiment, with reference to FIGS. 4 to 9 , the extension direction M of the jumper wire 22 can be set to be the same as the extension direction of the trunk line 21 to which the jumper wire 22 is connected.

Specifically, this arrangement is convenient for connecting the jumper line 22 to the main line 21, saving the length of the branch line 23 connected between the jumper line 22 and the main line 21, so that the impedance of the first wiring 2 is small, so that the first wiring The voltage drop of the voltage signal transmitted on 2 is small, which saves the wiring space on the array substrate 100 .

Optionally, on the basis of the above-mentioned embodiment, with reference to FIG. 3 to FIG. 10 , the first wiring 2 may include multiple power supply lines VDD and multiple data lines Data; the second wiring 3 may include multiple initialization lines Vref ; The third wiring 4 may include a plurality of light-emitting control lines EM and scan lines Scan.

Specifically, the first trace 2 may include a power line VDD and a plurality of data lines Data located on the third metal layer 30 . The second trace 3 may include a plurality of initialization lines Vref on the second metal layer 20 . The third trace 4 may include a plurality of light-emitting control lines EM and a scan line Scan located on the first metal layer 10 . FIG. 4 exemplarily shows the case where the scan line Scan includes the first scan line Scan1 and the second scan line Scan2 .

3 to 9 , the first trace 2 may include a data line Data, and the main line 21 of the data line Data is connected by a jumper 22, so that the orthographic projection of the main line 21 of the data line Data on the substrate 101 and the light emission control The orthographic projections of the line EM, the first scan line Scan1, the second scan line Scan2 and the initialization line Vref on the substrate 101 are staggered, so that the orthographic projection of the main line 21 of the data line Data on the substrate 101 is the same as the light emission control lines EM, The position where the orthographic projections of the first scan line Scan1, the second scan line Scan2 and the initialization line Vref on the substrate 101 do not overlap can better avoid the data line Data and the light emission control line EM, the first scan line Scan1, the first scan line There is a short circuit phenomenon caused by foreign matter or residual problem between the two scan lines Scan2 and the initialization line Vref.

3 to 9, the first trace 2 may further include a power line VDD, and the main line 21 of the power line VDD is connected by a jumper wire 22, so that the orthographic projection and light emission of the main line 21 of the power line VDD on the substrate 101 The orthographic projections of the control line EM, the first scan line Scan1, the second scan line Scan2 and the initialization line Vref on the substrate 101 are staggered, so that the orthographic projection of the main line 21 of the power supply line VDD on the substrate 101 is different from the light emission control line EM , the position where the orthographic projections of the first scan line Scan1, the second scan line Scan2 and the initialization line Vref on the substrate 101 do not overlap, which can better avoid the power supply line VDD and the light-emitting control line EM, the first scan line Scan1, There is a short circuit phenomenon caused by foreign matter or residual problem between the second scan line Scan2 and the initialization line Vref.

It should be noted that FIG. 3 exemplarily shows the case where the main line 21 included in the first wiring 2 is routed in a single layer of the third metal layer 30 , and FIG. 4 exemplarily shows the main line 21 included in the data line Data. In the case of single-layer wiring of the third metal layer 30 , the main line 21 included in the power supply line VDD is in the case of double-layer wiring of the third metal layer 30 and the fourth metal layer 40 . FIG. 4 exemplarily shows a situation where the first wiring 2 and the second wiring 3 are perpendicular to each other, and the first wiring 2 and the third wiring 4 are perpendicular to each other. No limitation is made here.

Optionally, FIG. 10 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention. 3 and 10, along the extension direction M of the jumper wire 22, the jumper wire 22 may include a first end a1 and a second end a2; along the extension direction M of the main line 21, the main line 21 may include a plurality of trunk line segments 210 arranged at intervals, the trunk line segment 210 includes a third end b1 and a fourth end b2; the branch line 23 includes a first branch line 231 and a second branch line 232; the first branch line 231 is connected to the trunk Between the fourth end b2 of the line segment 210 and the first end a1 of the jumper line 22 ; the second branch line 232 is connected between the third end b1 of the adjacent trunk line segment 210 and the second end a2 of the jumper line 22 .

Specifically, the first end a1 of the jumper line 22 is connected to the fourth end b2 of the main line segment 210 through the first branch line 231 , and the second end a2 of the jumper line 22 is connected to the adjacent main line segment 21 through the second branch line 232 . The third end b1 is connected. The third end b1 of the Nth trunk line segment 210 and the fourth end b2 of the N-1th trunk line 21 are respectively connected by the first branch line 231 , the jumper line 22 and the second branch line 232 . The fourth end b2 of the Nth trunk line segment 210 and the third end b1 of the N+1th trunk line segment 210 are respectively connected by the first branch line 231 , the jumper line 22 and the second branch line 232 . In this way, each jumper wire 22 is connected to the main wire 21 through two branch wires 23 , the process is simple, and it is convenient to save the manufacturing cost.

Optionally, on the basis of the above-mentioned embodiment, referring to FIG. 10 , the insulating layer provided in this embodiment may include a first insulating layer 6 , and the first insulating layer 6 is disposed on the fourth metal layer 40 and the third metal layer 30 . The second insulating layer 7 is arranged between the second metal layer 20 and the third metal layer 30 ; the thickness of the first insulating layer 6 is greater than the thickness of the second insulating layer 7 .

Specifically, the thickness of the first insulating layer 6 located between the third metal layer 30 and the fourth metal layer 40 is greater than that of the second insulating layer 7 located between the second metal layer 20 and the third metal layer 30, and the thickness increases In order to avoid the orthographic projection of the jumper wire 22 of the first wire 2 on the substrate 101, the insulation distance between the jumper wire 22 located in the fourth metal layer 40 and the second wire 3 and the third wire 4 is preferably avoided. The risk of short circuit occurring at the position overlapping the orthographic projection of the second trace 3 and the third trace 4 on the substrate 101 further improves the yield of the display panel.

Preferably, the first insulating layer 6 may include an organic adhesive layer. The insulating effect of the organic adhesive layer is good, and cracks are not easy to occur, which further reduces the risk of short circuit between the jumper wire 22 of the first wire 2 and the second wire 3 or the third wire 4 . On the other hand, the first insulating layer 6 includes an organic adhesive layer, which can be better compatible with the existing process and reduce the manufacturing cost.

Optionally, on the basis of the foregoing embodiment, referring to FIG. 10 , the array substrate 100 provided in this embodiment may further include: at least two through holes 5 ; the through holes 5 penetrate the first insulating layer 6 ; the branch lines 23 are provided in the through hole 5 .

Specifically, through holes 5 may be formed by drilling holes in the first insulating layer 6 , and branch lines 23 may be formed in the through holes 5 . This arrangement can reliably connect the jumper line 22 to the main line 21 , improve the yield of the branch line 23 , and avoid the risk of disconnection between the branch line 23 and the main line 21 .

Preferably, on the basis of the above-mentioned embodiment, and continuing to refer to FIG. 10 , the branch line 23 is perpendicular to the main line 21 and/or the jumper line 22 .

Specifically, this arrangement makes the length of the branch line 23 short, which is convenient to reduce the resistance of the branch line 23, and can also save the material of the branch line 23, the manufacturing process is simple, and the manufacturing cost is reduced.

Optionally, FIG. 11 is a schematic structural diagram of a display panel provided by an embodiment of the present invention. On the basis of the above embodiments, referring to FIG. 11 , the display panel 200 provided by the embodiments of the present invention includes the array substrate 100 proposed in any of the above embodiments, and has the beneficial effects of the array substrate 100 proposed in any of the above embodiments, which is not repeated here. Repeat.

Optionally, FIG. 12 is a schematic structural diagram of a display device provided by an embodiment of the present invention. On the basis of the above-mentioned embodiment, referring to FIG. 12 , the display device 400 provided by the embodiment of the present invention includes the array substrate 100 proposed in any of the above-mentioned embodiments, or includes the display panel 200 proposed in any of the above-mentioned embodiments. The beneficial effects of the array substrate 100 are not repeated here. The display device 400 includes terminals such as mobile phones, tablet computers, and wearable devices.

It should be noted that, FIG. 12 only exemplarily shows the case where the display device 400 includes the display panel 200 proposed in any of the above embodiments, which is not limited herein.

It should be understood that steps may be reordered, added or deleted using the various forms of flow shown above. For example, the steps described in the present invention can be performed in parallel, sequentially or in different orders, and as long as the desired results of the technical solutions of the present invention can be achieved, no limitation is imposed herein.

The above-mentioned specific embodiments do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may occur depending on design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (10)

1. An array substrate, characterized in that, comprising: substrate; In the direction away from the substrate, stack the first metal layer, the second metal layer, the third metal layer and the fourth metal layer arranged on one side of the substrate in sequence; An insulating layer is arranged between every two adjacent metal layers; a first wiring, the first wiring includes a main line located in the third metal layer and a jumper line located in the fourth metal layer; the jumper line is used to connect the main line; a second wiring, the second wiring is located in the second metal layer; a third wiring, the third wiring is located in the first metal layer; The orthographic projection of the trunk line of the first trace on the substrate and the orthographic projection of the second trace on the substrate and/or the third trace on the substrate The orthographic projection on is staggered. 2. The array substrate according to claim 1, wherein, The orthographic projection of the jumper wire of the first trace on the substrate and the orthographic projection of the second trace on the substrate and/or the third trace on the substrate The orthographic projections on at least partially overlap. 3. The array substrate according to claim 1, wherein the first wiring further comprises: A branch line, the branch line is connected between the main line and the jumper line; the branch line is used for conducting connection between the main line and the jumper line. 4. The array substrate according to claim 3, wherein, The extension direction of the jumper line is the same as the extension direction of the trunk line to which the jumper line is connected. 5. The array substrate according to claim 4, wherein, along the extending direction of the jumper wire, the jumper wire includes a first end and a second end; along the extension direction of the trunk line, the trunk line includes a plurality of trunk line segments arranged at intervals, and the trunk line segment includes a third end and a fourth end; the branch line includes a first branch line and a second branch line; The first branch line is connected between the fourth end of the main line segment and the first end of the jumper line; the second branch line is connected between the third end of the adjacent main line segment and all between the second ends of the jumper wires. 6. The array substrate according to claim 3, wherein the insulating layer comprises: a first insulating layer, the first insulating layer is disposed between the fourth metal layer and the third metal layer; a second insulating layer, the second insulating layer is disposed between the second metal layer and the third metal layer; The thickness of the first insulating layer is greater than the thickness of the second insulating layer; Preferably, the first insulating layer includes an organic adhesive layer. 7. The array substrate according to claim 6, wherein the array substrate further comprises: at least two through holes; the through holes penetrate the first insulating layer; the branch line is arranged in the through hole; Preferably, the branch line is perpendicular to the trunk line and/or the jumper line. 8. The array substrate according to claim 1, wherein, The first wiring includes a plurality of power lines and a plurality of data lines; the second wiring includes a plurality of initialization lines; The third wiring includes a plurality of light-emitting control lines and scan lines. 9. A display panel, comprising: the array substrate according to any one of claims 1-8. 10. A display device, comprising: the display panel of claim 9.

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