CN115021756A - Analog-to-digital conversion circuit, chip, analog-to-digital conversion method and electronic device - Google Patents

Abstract

Embodiments of the present application provide an analog-to-digital conversion circuit, a chip, an analog-to-digital conversion method, and an electronic device. The analog-to-digital conversion circuit includes: a fully parallel analog-to-digital conversion module, including: a K-bit resistor string; an N-bit successive approximation analog-to-digital The conversion module includes: an M-bit capacitance digital-to-analog conversion array, which is used to perform N-bit analog-to-digital conversion on the analog input signal and obtain an N-bit digital signal. The N-bit digital signal includes a high K-bit digital signal and a low M-bit digital signal, wherein , N=K+M, and K, M, and N are positive integers; among them: the fully parallel analog-to-digital conversion module is configured to sample and convert the analog input signal to obtain a high K-bit digital signal; N-bit successive approximation modulus The digital conversion module is configured to obtain the low M-bit digital signal through the K-bit resistor string and the M-bit capacitance digital-to-analog conversion array, and the low M-bit digital signal is obtained from the N-bit analog-to-digital conversion according to the high K-bit digital signal. With the embodiments of the present application, the area or power consumption of the analog-to-digital conversion circuit can be reduced.

Description

Analog-to-digital conversion circuit, chip, analog-to-digital conversion method and electronic device

technical field

The present application relates to the technical field of signal processing, and in particular, to an analog-to-digital conversion circuit, a chip, an analog-to-digital conversion method, and an electronic device.

Background technique

A fully parallel (Flash) analog-to-digital converter (ADC) combined with a successive approximation register (SAR) ADC is a hybrid analog-to-digital converter, also known as a Flash-SAR ADC.

The Flash-SAR ADC in the related art has technical problems of large circuit area and high power consumption.

SUMMARY OF THE INVENTION

In view of this, the embodiments of the present application provide an analog-to-digital conversion circuit, a chip, an analog-to-digital conversion method, and an electronic device, so as to reduce the circuit area and power consumption of the analog-to-digital conversion circuit.

According to an aspect of the present application, an analog-to-digital conversion circuit is provided, comprising:

Full parallel analog-to-digital conversion module, including: K-bit resistor string;

N-bit successive approximation analog-to-digital conversion module, including: M-bit capacitance digital-to-analog conversion array, used to perform N-bit analog-to-digital conversion on the analog input signal and obtain N-bit digital signal, the N-bit digital signal includes high K-bit digital signal and low M-bit digital signal, wherein, N=K+M, and K, M and N are positive integers;

in:

The fully parallel analog-to-digital conversion module is configured to sample and convert the analog input signal to obtain a high-K-bit digital signal;

The N-bit successive approximation analog-to-digital conversion module is configured to obtain the low M-bit digital signal through the K-bit resistor string and the M-bit capacitor digital-to-analog conversion array, and the low M-bit digital signal is based on the high K-bit digital signal. obtained in conversion.

According to another aspect of the present application, an analog-to-digital conversion method for an analog-to-digital conversion circuit is provided. The analog-to-digital conversion circuit includes: a fully parallel analog-to-digital conversion module, including: a K-bit resistor string; an N-bit successive approximation analog-to-digital conversion module , including: M-bit capacitance digital-to-analog conversion array, N-bit successive approximation analog-to-digital conversion module, which is used to perform N-bit analog-to-digital conversion on the analog input signal and obtain N-bit digital signal. The N-bit digital signal includes high K-bit digital signal and Low M-bit digital signal; wherein, N=K+M, and K, M and N are positive integers;

Analog-to-digital conversion methods include:

The fully parallel analog-to-digital conversion module samples and converts the analog input signal to obtain a high K-bit digital signal;

The N-bit successive approximation analog-to-digital conversion module obtains the low M-bit digital signal through the K-bit resistor string and the M-bit capacitor digital-to-analog conversion array, and the low M-bit digital signal is obtained from the N-bit analog-to-digital conversion according to the high K-bit digital signal.

According to another aspect of the present application, a chip is provided, including the analog-to-digital conversion circuit of the embodiment of the present application.

According to another aspect of the present application, an electronic device is provided, including: the analog-to-digital conversion circuit of the embodiment of the present application.

One or more technical solutions provided in the embodiments of the present application reduce the number of capacitors in the capacitor digital-to-analog conversion array in the successive approximation analog-to-digital conversion module by multiplexing the K-bit resistor strings in the fully parallel analog-to-digital conversion module, which can reduce circuit area and reduced power consumption.

Description of drawings

Further details, features and advantages of the present application are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

1 shows a schematic block diagram of an analog-to-digital conversion circuit according to an exemplary embodiment of the present application;

FIG. 2 shows another schematic block diagram of an analog-to-digital conversion circuit according to an exemplary embodiment of the present application;

FIG. 3 shows another schematic block diagram of an analog-to-digital conversion circuit according to an exemplary embodiment of the present application;

Fig. 4 shows another schematic block diagram of the analog-to-digital conversion circuit of the exemplary embodiment of the present application;

Fig. 5 shows another schematic block diagram of the analog-to-digital conversion circuit of an exemplary embodiment of the present application;

Fig. 6 shows another schematic block diagram of the analog-to-digital conversion circuit of an exemplary embodiment of the present application;

FIG. 7 shows a schematic structural diagram of an example of an analog-to-digital conversion circuit according to an exemplary embodiment of the present application;

FIG. 8 shows a schematic structural diagram of another example of an analog-to-digital conversion circuit according to an exemplary embodiment of the present application;

FIG. 9 shows a flowchart of an analog-to-digital conversion method according to an exemplary embodiment of the present application.

Detailed ways

Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present application are shown in the drawings, it is to be understood that the present application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for the purpose of A more thorough and complete understanding of this application. It should be understood that the drawings and embodiments of the present application are only used for exemplary purposes, and are not used to limit the protection scope of the present application.

It should be understood that the various steps described in the method embodiments of the present application may be performed in different orders and/or in parallel. Furthermore, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of this application is not limited in this regard.

As used herein, the term "including" and variations thereof are open-ended inclusions, ie, "including but not limited to". The term "based on" is "based at least in part on." The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions of other terms will be given in the description below. It should be noted that concepts such as "first" and "second" mentioned in this application are only used to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or interdependence.

It should be noted that the modifications of "a" and "a plurality" mentioned in this application are illustrative rather than restrictive, and those skilled in the art should understand that unless the context clearly indicates otherwise, they should be understood as "one or a plurality of". multiple".

The embodiments of the present application provide an analog-to-digital conversion circuit.

FIG. 1 shows a schematic block diagram of an analog-to-digital conversion circuit according to an exemplary embodiment of the present application. As shown in FIG. 1 , the analog-to-digital conversion circuit 100 includes: a fully parallel analog-to-digital conversion module 110 and an N-bit successive approximation analog-to-digital conversion module 120. The fully parallel analog-to-digital conversion module 110 includes a K-bit resistor string 111 . The N-bit successive approximation analog-to-digital conversion module 120 includes an M-bit capacitance digital-to-analog conversion array 121 . The N-bit successive approximation analog-to-digital conversion module 120 is configured to perform N-bit analog-to-digital conversion on the analog input signal and obtain an N-bit digital signal, wherein the N-bit digital signal includes a high K-bit digital signal and a low M-bit digital signal. N=K+M, and K, M and N are positive integers.

The fully parallel analog-to-digital conversion module 110 is configured to sample and convert the analog input signal to obtain the high-K-bit digital signal in the N-bit digital signal. The N-bit successive approximation analog-to-digital conversion module 120 is configured to obtain the low M-bit digital signal in the N-bit digital signal through the K-bit resistor string 111 and the M-bit capacitance digital-to-analog conversion array 121, and the low M-bit digital signal is based on The high K-bit digital signal is obtained in N-bit analog-to-digital conversion.

Through the analog-to-digital conversion circuit 100 of this embodiment, the K-bit resistor string 111 of the fully parallel analog-to-digital conversion module 110 and the M-bit capacitance digital-to-analog conversion array 121 of the N-bit successive approximation analog-to-digital conversion module 120 are used to form a resistor-capacitor hybrid structure, Realize N bit-to-analog conversion. By multiplexing the K-bit resistor strings in the fully parallel analog-to-digital conversion module, the number of capacitors in the capacitor-to-digital-to-analog conversion array in the successive approximation analog-to-digital conversion module can be reduced, which can reduce circuit area and power consumption.

It should be understood that although the components included in the analog-to-digital conversion circuit 100 and the positional relationship between the components are shown in FIG. 1 , this embodiment is not limited thereto.

In this embodiment, the M-bit capacitor digital-to-analog conversion array 121 may be a binary weighted capacitor array or a segmented capacitor array (also referred to as a bridge capacitor array), which is not limited in this embodiment. An example of a segmented capacitor array is the separation of two independent binary weighted capacitor arrays by segmented capacitors (called Cs) to at least reduce the overall capacitance value.

In this embodiment, the K-bit resistor string 111 can be first used by the fully parallel analog-to-digital conversion module 110 to generate the high-order K-bit digital signal among the N-bit digital signals, and then used by the N-bit successive approximation analog-to-digital conversion module 120 to generate the digital signal. The low-order M-bit digital signal in the N-bit digital signal. A possible implementation of the multiplexed K-bit resistor string 111 is described below.

method one

The N-bit successive approximation analog-to-digital conversion module 120 is configured to: perform digital-to-analog conversion on the high K-bit digital signal through the K-bit resistor string 111 , and obtain the low M in the N-bit digital signal through the M-bit capacitance digital-to-analog conversion array 121 bit digital signal.

FIG. 2 shows a schematic block diagram of an analog-to-digital conversion circuit according to an exemplary embodiment of the present application. As shown in FIG. 2, the analog-to-digital conversion circuit 100 further includes: a switch module 130 configured to The temperature code corresponding to the signal (including 2 ^k -1 bits) controls the K-bit resistor string 111 to output the reference voltage signal (V _REF ). The reference signal terminals corresponding to each capacitor in the M-bit capacitor digital-to-analog conversion array 121 are configured to receive the above-mentioned reference voltage signal (V _REF ).

As shown in FIG. 2 , the fully parallel analog-to-digital conversion module 110 includes: a comparison module 112 connected to the K-bit resistor string 111 , and the comparison module 112 is configured to generate a temperature code corresponding to the high K-bit digital signal. Further, the corresponding high K-bit digital signal can be obtained based on the temperature encoding.

As an example, the switch module 130 includes switches corresponding to the encoded bits of the temperature encoding, and each bit in the temperature encoding controls one switch respectively. As an example, the K-bit resistor string 111 may include ^2K -1 equal-value resistors, the comparison module 112 includes ^2K -1 comparators, and each comparator receives a segmented reference voltage corresponding to a resistor. Correspondingly, The switch module 130 may include 2 ^K −1 switches, and each switch corresponds to a segmented reference voltage corresponding to one resistance.

Take one sample and convert as an example. Exemplarily, during the sampling period, the analog input signal is simultaneously sampled by the fully parallel analog-to-digital conversion module 110 and the N-bit successive approximation analog-to-digital conversion module 120 . During the conversion period of the fully parallel analog-to-digital conversion module 110, the comparison module 112 generates the temperature code of the high-K-bit digital signal corresponding to the analog input signal, and further encodes the temperature code to obtain the high-K-bit digital signal corresponding to the analog input signal. The comparison module 112 feeds back the temperature code to the switch module 130 . The switch module 130 controls the K-bit resistor string 111 to output a reference voltage signal (V _REF ) according to the temperature code, and the reference signal terminal corresponding to each capacitor in the M-bit capacitor digital-to-analog conversion array 121 receives the reference voltage signal (V _REF ). At this time, the K-bit resistor string 111 in the multiplexed full-parallel analog-to-digital conversion module is used as the high-K digital-to-analog conversion module of the N-bit successive approximation analog-to-digital conversion module 120, and the M-bit capacitance digital-to-analog conversion array 121 is used as the N-bit successive approximation. The low-M digital-to-analog conversion module of the analog-to-digital conversion module 120, the N-bit successive approximation analog-to-digital conversion module 120 directly starts the comparison from the M-1th bit through the M-bit capacitance digital-to-analog conversion array, and the rest only needs to be compared M times until the generation The low M-bit digital signal corresponding to the analog input signal.

FIG. 3 shows a schematic block diagram of another analog-to-digital conversion circuit according to an exemplary embodiment of the present application. As shown in FIG. 3 , the analog-to-digital conversion circuit 100 further includes: a switch module 130 configured to The digital signal controls the K-bit resistor string 111 to output a reference voltage signal (V _REF ). The reference signal terminals corresponding to each capacitor in the M-bit capacitor digital-to-analog conversion array 121 are configured to receive the above-mentioned reference voltage signal (V _REF ).

As shown in FIG. 3 , the fully parallel analog-to-digital conversion module 110 includes: a comparison module 112, which is connected to the K-bit resistor string 111, and the comparison module 112 is configured to generate the temperature encoding of the high K-bit digital signal corresponding to the analog input signal; the encoding module 113, connected to the comparison module 112, and configured to generate a high K-bit digital signal corresponding to the analog input signal for the temperature encoding.

As an example, the switch module 130 may include K channels of control signal terminals, and each channel of control signal terminals corresponds to one bit of digital signal in the high K-bit digital signal. As an example, the switch module 130 may be a switch tree having K channels corresponding to control signal terminals.

Take one sample and convert as an example. Exemplarily, during the sampling period, the analog input signal is simultaneously sampled by the fully parallel analog-to-digital conversion module 110 and the N-bit successive approximation analog-to-digital conversion module 120 . During the conversion of the fully parallel analog-to-digital conversion module 110, the comparison module 112 generates the temperature code of the high K-bit digital signal corresponding to the analog input signal, and the encoding module 113 further encodes the temperature code to obtain the high K-bit digital signal corresponding to the analog input signal. The encoding module 113 feeds back the high K-bit digital signal to the switch module 130 . The switch module 130 controls the K-bit resistor string 111 according to the high K-bit digital signal to output a reference voltage signal (V _REF ), and the reference signal terminal corresponding to each capacitor in the M-bit capacitor digital-to-analog conversion array 121 receives the reference voltage signal (V _REF ) . At this time, the K-bit resistor string 111 in the multiplexed full-parallel analog-to-digital conversion module is used as the high-K digital-to-analog conversion module of the N-bit successive approximation analog-to-digital conversion module 120, and the M-bit capacitance digital-to-analog conversion array 121 is used as the N-bit successive approximation. The low-M digital-to-analog conversion module of the analog-to-digital conversion module 120, the N-bit successive approximation analog-to-digital conversion module 120 directly starts the comparison from the M-1th bit through the M-bit capacitance digital-to-analog conversion array, and the rest only needs to be compared M times until the generation The low M-bit digital signal corresponding to the analog input signal.

FIG. 4 shows a schematic block diagram of another analog-to-digital conversion circuit according to an exemplary embodiment of the present application. As shown in FIG. 4 , the analog-to-digital conversion circuit 100 further includes: a switch module 130 .

As shown in FIG. 4 , the fully parallel analog-to-digital conversion module 110 includes: a comparison module 112, which is connected to the K-bit resistor string 111, and the comparison module 112 is configured to generate the temperature encoding of the high K-bit digital signal corresponding to the analog input signal; the encoding module 113, connected to the comparison module 112, and configured to generate a high K-bit digital signal corresponding to the analog input signal for the temperature encoding.

As shown in FIG. 4 , the N-bit successive approximation analog-to-digital conversion module 120 further includes: an M-bit successive comparison logic 122 and a comparison unit 124 . The M-bit successive comparison logic 122 is configured to control the M-bit capacitance digital-to-analog conversion array 121 to perform low-M digital-to-analog conversion in the N-bit digital-to-analog conversion, thereby obtaining a low-M-bit digital signal corresponding to the analog input signal.

As shown in FIG. 4 , the analog-to-digital conversion circuit 100 further includes: a comparison unit 124 . One input terminal of the comparison unit 124 is connected to the analog voltage output terminal of the M-bit capacitance digital-to-analog conversion array 121 . The M-bit successive comparison logic 122 listens to the comparison output of the comparison unit 124 .

It should be noted that, in FIG. 4 , a dotted line is used to connect the encoding circuit 113 and the switch module 130 , and another dotted line is used to connect the comparison module 112 and the switch module 130 , the purpose of which is to illustrate one of the encoding circuit 113 or the comparison module 112 The signal is used to control the switch module 130 and is not a limitation of the connection relationship.

Method 2

The N-bit successive approximation analog-to-digital conversion module 120 is configured to: control the M-bit capacitance digital-to-analog conversion array to perform digital-to-analog conversion according to the high-K-bit digital signal or the temperature code corresponding to the high-K-bit digital signal, and use the M-bit capacitance digital signal to perform digital-to-analog conversion. The analog conversion array and the K-bit resistor string obtain the low-order M-bit digital signal in the N-bit digital signal.

FIG. 5 shows a schematic block diagram of an analog-to-digital conversion circuit according to an exemplary embodiment of the present application. As shown in FIG. 5 , a switch module 130 is further included.

As shown in FIG. 5 , the N-bit successive approximation analog-to-digital conversion module 120 further includes: an M-bit successive approximation logic 122 configured to output an M-bit control signal. The M-bit capacitance digital-to-analog conversion array 121 includes: a high-K-bit capacitance digital-to-analog conversion array, a low M-K-bit capacitance digital-to-analog conversion array, and a compensation capacitor.

The M-bit control signal is used to control the low-M-K-bit capacitance digital-to-analog conversion array and the K-bit resistor string to obtain a low-M-bit digital signal. Specifically, the M-bit control signal includes a first control signal and a second control signal.

The switch module 130, connected to the M-bit successive approximation logic 122, is configured to control the K-bit resistor string to output the reference voltage signal (V _REF ) according to the first control signal. A compensation capacitor is configured to receive the reference voltage signal (V _REF ). The low MK bit capacitance digital-to-analog conversion array is configured to receive the second control signal for digital-to-analog conversion.

As shown in FIG. 5 , the fully parallel analog-to-digital conversion module 110 includes: a comparison module 112, which is connected to the K-bit resistor string 111, and the comparison module 112 is configured to generate the temperature encoding of the high K-bit digital signal corresponding to the analog input signal; the encoding module 113, connected to the comparison module 112, and configured to generate a high K-bit digital signal corresponding to the analog input signal for the temperature encoding. The high-K-bit capacitance digital-to-analog conversion array is configured to receive the temperature code corresponding to the analog input signal.

As an example, the switch module 130 includes K channels of control signal terminals, and each channel of control signal terminals corresponds to a one-bit switch control signal in the first control signal. As an example, the switch module 130 may be a switch tree with K channels of control signals.

Take one sample and convert as an example. Exemplarily, during the sampling period, the analog input signal is simultaneously sampled by the fully parallel analog-to-digital conversion module 110 and the N-bit successive approximation analog-to-digital conversion module 120 . During the conversion period of the fully parallel analog-to-digital conversion module 110, the comparison module 112 generates the bit temperature code of the high-K digital signal corresponding to the analog input signal, and the encoding module 113 further encodes the temperature code to obtain the high-K bit digital signal corresponding to the analog input signal. The encoding module 113 feeds back the high-k-bit digital signal to the high-k-bit capacitance digital-to-analog conversion array of the M-bit capacitance digital-to-analog conversion array 121, so that the high-k-bit capacitance digital-to-analog conversion array is flipped according to the high-k-bit digital signal, and the N bits The successive approximation analog-to-digital conversion module 120 only needs to perform conversion from the remaining low M-K bit capacitance digital-to-analog conversion arrays in the M-bit capacitor digital-to-analog conversion array until the low M-bit digital signal corresponding to the analog input signal is generated.

Specifically, in the process of converting the low M-bit digital signal, the second control signal in the M-bit control signal output by the M-bit successive approximation logic 122 controls the low-MK-bit capacitance digital-to-analog conversion array to perform conversion, and the M-bit control signal The first control signal in the switch module 130 controls the switch module 130 to control the K-bit resistor string 111 to output a reference voltage signal (V _REF ); the reference signal terminal of the compensation capacitor in the M-bit capacitor digital-to-analog conversion array 121 receives the reference voltage signal (V _REF ). That is, in this process, the conversion of the low M-bit digital signal is completed by the low MK-bit capacitance digital-to-analog conversion array in the M-bit capacitance digital-to-analog conversion array and the K-bit resistor string 111 in the fully parallel analog-to-digital conversion array.

FIG. 6 shows a schematic block diagram of another analog-to-digital conversion circuit according to an exemplary embodiment of the present application. As shown in FIG. 6 , it further includes a switch module 130 .

As shown in FIG. 6 , the N-bit successive approximation analog-to-digital conversion module 120 further includes: an M-bit successive approximation logic 122 configured to output an M-bit control signal. The M-bit capacitance digital-to-analog conversion array 121 includes: a high-K-bit capacitance digital-to-analog conversion array, a low M-K-bit capacitance digital-to-analog conversion array, and a compensation capacitor.

The M-bit control signal is used to control the low-M-K-bit capacitance digital-to-analog conversion array and the K-bit resistor string to obtain a low-M-bit digital signal. Specifically, the M-bit control signal includes a first control signal and a second control signal.

The N-bit successive approximation analog-to-digital conversion module 120 further includes an encoding module 123 configured to generate a temperature encoding corresponding to the first control signal.

The switch module 130, connected to the encoding module 123, is configured to control the K-bit resistor string according to the temperature encoding corresponding to the first control signal to output a reference voltage signal (V _REF ). A compensation capacitor is configured to receive the reference voltage signal (V _REF ). The low MK bit capacitance digital-to-analog conversion array is configured to receive the second control signal for digital-to-analog conversion.

As an example, the switch module 130 includes switches corresponding to a corresponding number of encoded bits of temperature encoding, and each switch corresponds to a segmented reference voltage corresponding to the resistance of the K-bit resistor string 111 .

As shown in FIG. 6 , the fully parallel analog-to-digital conversion module 110 includes: a comparison module 112, which is connected to the K-bit resistor string 111, and the comparison module 112 is configured to generate the temperature encoding of the high K-bit digital signal corresponding to the analog input signal; the encoding module 113, connected to the comparison module 112, and configured to generate a high K-bit digital signal corresponding to the analog input signal for the temperature encoding. The high-K-bit capacitance digital-to-analog conversion array is configured to receive high-K-bit digital signals corresponding to the analog input signals.

Take one sample and convert as an example. Exemplarily, during the sampling period, the analog input signal is simultaneously sampled by the fully parallel analog-to-digital conversion module 110 and the N-bit successive approximation analog-to-digital conversion module 120 . During the conversion of the fully parallel analog-to-digital conversion module 110, the comparison module 112 generates the temperature code of the high K-bit digital signal corresponding to the analog input signal, and the encoding module 113 further encodes the temperature code to obtain the high K-bit digital signal corresponding to the analog input signal. The encoding module 113 feeds back the high-k-bit digital signal to the high-k-bit capacitance digital-to-analog conversion array of the M-bit capacitance digital-to-analog conversion array 121, so that the high-k-bit capacitance digital-to-analog conversion array is flipped according to the high-k-bit digital signal, and the N bits The successive approximation analog-to-digital conversion module 120 only needs to perform conversion from the remaining low M-K bit capacitance digital-to-analog conversion arrays in the M-bit capacitor digital-to-analog conversion array until the low M-bit digital signal corresponding to the analog input signal is generated.

Specifically, in the process of converting the low M-bit digital signal, the second control signal in the M-bit control signal output by the M-bit successive approximation logic 122 controls the low-M-K-bit capacitance digital-to-analog conversion array to perform conversion, and the M-bit control signal The first control signal in the switch module 130 controls the switch module 130 to control the K-bit resistor string 111 to output a reference voltage signal (VREF); the reference signal terminal of the compensation capacitor in the M-bit capacitor digital-to-analog conversion array 121 receives the reference voltage signal (VREF). That is, in this process, the conversion of the low M-bit digital signal is completed by the low M-K-bit capacitance digital-to-analog conversion array in the M-bit capacitance digital-to-analog conversion array and the K-bit resistor string 111 in the fully parallel analog-to-digital conversion array.

As shown in FIGS. 5 and 6 , the analog-to-digital conversion circuit 100 further includes: a comparison unit 124 . One input terminal of the comparison unit 124 is connected to the analog voltage output terminal of the M-bit capacitance digital-to-analog conversion array 121 . The M-bit successive comparison logic 122 listens to the comparison output of the comparison unit 124 .

Some examples of this embodiment are described below.

FIG. 7 shows a schematic structural diagram of an example of an analog-to-digital conversion circuit according to an exemplary embodiment of the present application. The analog-to-digital conversion circuit is an N-bit Flash SAR hybrid ADC, as shown in FIG. 7 , which includes K-bit Flash ADC, M-bit DAC differential capacitor array, comparator COMP, M-bit SAR logic, encoding circuit 1 and encoding circuit 2.

The K-bit Flash ADC includes sampling capacitors CS1 and CS2, a K-bit resistor string, and 2*(2 ^K -1) comparators. During the ADC sampling stage, the Flash ADC and the SAR ADC sample simultaneously. After the sampling is completed, the temperature code results TP[2 ^K -1:0] and TP[2 ^K -1:0] corresponding to the differential signal can be obtained in one clock cycle, and then the K-bit binary code result T[K is obtained through the encoding circuit 1 -1:0]. And the comparison result of the K-bit Flash ADC is fed back to the K-bit resistor string (as the high K-bit resistor array in the SAR ADC) through the encoding circuit 1.

The N-bit SAR ADC includes a K-bit resistor string, an M-bit DAC differential capacitor array, a comparator COMP, an M-bit SAR logic, etc. The M-bit DAC differential capacitor array includes an M-bit capacitor array, wherein the DAC differential capacitor array includes but Not limited to binary weight DAC differential capacitor arrays and bridge DAC differential capacitor arrays. After the coding circuit 1 feeds back the comparison result of the K-bit Flash ADC to the high K bits in the SAR ADC, the SAR ADC starts the comparison of the M-1th bit, and the remaining comparisons are made M times. The high K bits of the SAR ADC directly multiplex the K-bit resistor string in the Flash ADC, and are controlled by two sets of switches SW1 and SW2. The DAC differential capacitor array includes an M-bit capacitor array, and the M-bit capacitor array is controlled by M bit SAR logic. The number of reusable resistor strings of the SAR ADC is less than or equal to K bits, and the DAC array includes an M-bit capacitor array. The total number of capacitors is 2*2 ^M , which reduces 2*(2 ^N -2 ^M ) capacitors compared to the traditional method. . For example, for a SAR ADC with N=12, K=4, and M=8, the number of capacitors that can be saved is 2*(2 ¹² -2 ⁸ )=7680, and the saved capacitor part accounts for about 94% of the capacitance of the traditional structure.

The encoding circuit 2 accumulates the K-bit binary code result T[K-1:0] of the Flash ADC and the M-bit binary code result D[M-1:0] of the SAR ADC to obtain the N-bit binary code result D[N-1 :0].

FIG. 8 shows a schematic structural diagram of another example of an analog-to-digital conversion circuit according to an exemplary embodiment of the present application. The analog-to-digital conversion circuit is an N-bit Flash SAR hybrid ADC, and the circuit includes K-bit Flash ADC, M-bit DAC differential capacitor array, comparator COMP, M-bit SAR logic, encoding circuit 1 and encoding circuit 2.

The K-bit Flash ADC includes sampling capacitors CS1 and CS2, a K-bit resistor string, and 2*(2 ^K -1) comparators. In the ADC sampling stage, the Flash ADC and SAR ADC are sampled at the same time. After the sampling is completed, the temperature code results TP[2 ^K -1:0] and TP[2 ^K -1:0] corresponding to the differential signal can be obtained in one clock cycle, and then Through the encoding circuit 1, the K-bit binary code result T[K-1:0] can be obtained. And through the coding circuit 1, the comparison result of the K-bit Flash ADC is fed back to the high-k-bit capacitor array in the SAR ADC.

The N-bit SAR ADC includes a K-bit resistor string, an M-bit DAC differential capacitor array, a comparator COMP, an M-bit SAR logic, etc. The M-bit DAC differential capacitor array includes a high-K-bit capacitor array and a low-MK-bit capacitor array. The DAC differential capacitor array is not limited to the binary weight DAC differential capacitor array and the bridge-connected DAC differential capacitor array. After the coding circuit 1 feeds back the comparison result of the K-bit FlashADC to the high-K-bit capacitor array in the SAR ADC, the SAR ADC starts the comparison of the M-1th bit, and the remaining comparisons are made M times. The lowest-order capacitance CPT(0) in the high-K bits of the DAC differential capacitance array is twice the highest-order capacitance CP(MK-1) in the low-MK bits. The low M bits of the SAR ADC include an MK-bit capacitor array and a K-bit resistor string. The K-bit resistor string multiplexes the resistor string in the Flash ADC through two sets of switches SW1 and SW2. The MK-bit capacitor array and the K-bit resistor string are controlled by M-bit SAR logic. The number of resistor strings that can be reused by SARADC is less than or equal to K bits, and the DAC array only needs an M-bit capacitor array. The total number of capacitors is 2*2 ^M , which reduces 2*(2 ^N -2 ^M ) capacitors compared to the traditional method. . For example, for a SAR ADC with N=12, K=4, and M=8, the number of capacitors that can be saved is 2*(21 ² -2 ⁸ )=7680, and the saved capacitor portion accounts for about 94% of the capacitance of the traditional structure.

The encoding circuit 2 accumulates the K-bit binary code result T[K-1:0] of the Flash ADC and the M-bit binary code result D[M-1:0] of the SAR ADC to obtain the N-bit binary code result D[N-1 :0].

This embodiment also provides an analog-to-digital conversion method for an analog-to-digital conversion circuit, which is applied to the analog-to-digital conversion circuit of the embodiment of the present application.

Fig. 9 shows a flowchart of an analog-to-digital conversion method according to an exemplary embodiment of the present application. As shown in Fig. 9 , the method includes steps S901 to S902.

Step S901 , the fully parallel analog-to-digital conversion module samples and converts the analog input signal to obtain a high K-bit digital signal corresponding to the analog input signal.

The fully parallel analog-to-digital conversion module includes: a K-bit resistor string; an N-bit successive approximation analog-to-digital conversion module includes: an M-bit capacitance digital-to-analog conversion array, where N=K+M, and K, M and N are positive integer.

Step S902, the N-bit successive approximation analog-to-digital conversion module obtains the low M-bit digital signal through the K-bit resistor string and the M-bit capacitor digital-to-analog conversion array, and the low M-bit digital signal is converted according to the high K-bit digital signal in the N-bit analog-to-digital conversion. obtained in.

Through the analog-to-digital conversion method of this embodiment, a resistor-capacitor hybrid structure is formed by using the K-bit resistor string of the fully parallel analog-to-digital conversion module and the M-bit capacitance digital-to-analog conversion array of the N-bit successive approximation analog-to-digital conversion module to realize N-bit analog-to-digital conversion. convert. By multiplexing the K-bit resistor strings in the fully parallel analog-to-digital conversion module, the number of capacitors in the capacitor-to-digital-to-analog conversion array in the successive approximation analog-to-digital conversion module can be reduced, which can reduce circuit area and power consumption.

As an implementation manner, the above step S902 includes:

The digital-to-analog conversion is performed on the high-K-bit digital signal through the K-bit resistor string, and the low-M-bit digital signal is obtained through the M-bit capacitance digital-to-analog conversion array.

As an example, digital-to-analog conversion is performed on high-k-bit digital signals through K-bit resistor strings, and low-M-bit digital signals are obtained through an M-bit capacitor digital-to-analog conversion array, including:

According to the high-K-bit digital signal or the temperature code corresponding to the high-K-bit digital signal, the K-bit resistor string is controlled to output the first reference voltage signal, wherein the reference signal terminal corresponding to each capacitor in the M-bit capacitor digital-to-analog conversion array receives the first reference signal. a reference voltage signal.

As another implementation manner, the N-bit successive approximation analog-to-digital conversion module obtains a low-M-bit digital signal through a K-bit resistor string and an M-bit capacitor digital-to-analog conversion array, including:

According to the temperature code corresponding to the high-K-bit digital signal or the high-K-bit digital signal, the M-bit capacitor digital-to-analog conversion array is controlled to perform digital-to-analog conversion, and the low-M-bit digital signal is obtained through the M-bit capacitor digital-to-analog conversion array and the K-bit resistor string. .

As an example, the M-bit capacitance digital-to-analog conversion array includes: a high-K-bit capacitance digital-to-analog conversion array, a low M-K-bit capacitance digital-to-analog conversion array, and a compensation capacitor;

Among them, the low M-bit digital signal is obtained through the M-bit capacitor digital-to-analog conversion array and the K-bit resistor string, including:

Output an M-bit control signal, wherein the M-bit control signal is used to control the low-M-K-bit capacitance digital-to-analog conversion array and the K-bit resistor string to obtain a low-M-bit digital signal; and the M-bit control signal includes a first control signal and a second control signal Signal;

The K-bit resistor string is controlled according to the first control signal to output the second reference voltage signal, wherein the reference signal terminal corresponding to the compensation capacitor is configured to receive the second reference voltage signal;

The low M-K bit capacitance digital-to-analog conversion array is controlled to perform digital-to-analog conversion according to the second control signal.

An embodiment of the present application further provides a chip, where the chip includes the above-mentioned analog-to-digital conversion circuit. A chip (Integrated Circuit, IC) is also called a chip, and the chip may be, but is not limited to, a SOC (System on Chip, system-on-chip) chip or a SIP (system in package, system-in-package) chip. The chip uses the K-bit resistor string of the full-parallel analog-to-digital conversion module and the M-bit capacitance digital-to-analog conversion array of the N-bit successive approximation analog-to-digital conversion module to form a resistor-capacitor hybrid structure to realize N digital-to-analog conversion. By multiplexing the K-bit resistor strings in the fully parallel analog-to-digital conversion module, the number of capacitors in the capacitor-to-digital-to-analog conversion array in the successive approximation analog-to-digital conversion module is reduced, which can reduce circuit area and power consumption.

An embodiment of the present application further provides an electronic device, the electronic device includes a device body and the above-mentioned chip provided in the device subject. Electronic devices can be but are not limited to weight scales, body fat scales, nutrition scales, infrared electronic thermometers, pulse oximeters, body composition analyzers, power banks, wireless chargers, fast chargers, car chargers, adapters, monitors , USB (Universal Serial Bus, Universal Serial Bus) docking station, stylus, true wireless headset, car center console, automobile, smart wearable device, mobile terminal, smart home equipment. Smart wearable devices include but are not limited to smart watches, smart bracelets, and cervical spine massagers. Mobile terminals include but are not limited to smart phones, notebook computers, tablet computers, and POS (point of sales terminal, point of sale terminal) machines. Smart home devices include but are not limited to smart sockets, smart rice cookers, smart sweepers, and smart lights. The electronic device forms a resistor-capacitor hybrid structure by using the K-bit resistor string of the fully parallel analog-to-digital conversion module and the M-bit capacitance digital-to-analog conversion array of the N-bit successive approximation analog-to-digital conversion module to realize N-bit digital-to-analog conversion. By multiplexing the K-bit resistor strings in the fully parallel analog-to-digital conversion module, the number of capacitors in the capacitor-to-digital-to-analog conversion array in the successive approximation analog-to-digital conversion module is reduced, which can reduce circuit area and power consumption.

The above are only preferred embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed above with preferred embodiments, it is not intended to limit the present application. Without departing from the scope of the technical solution of the present application, when the technical content disclosed above can be used to make some changes or modifications to equivalent examples of equivalent changes, provided that it does not depart from the content of the technical solution of the present application, according to the technical essence of the present application. Any brief modifications, equivalent changes and modifications made in the above embodiments still fall within the scope of the technical solutions of the present application.

Claims (13)

1. an analog-to-digital conversion circuit, is characterized in that, comprises: Full parallel analog-to-digital conversion module, including: K-bit resistor string; The N-bit successive approximation analog-to-digital conversion module includes: an M-bit capacitance digital-to-analog conversion array for performing N-bit analog-to-digital conversion on an analog input signal to obtain an N-bit digital signal, where the N-bit digital signal includes high K-bit digital signals and low M-bit digital signals, where N=K+M, and K, M and N are positive integers; in: The fully parallel analog-to-digital conversion module is configured to sample and convert the analog input signal to obtain the high K-bit digital signal; The N-bit successive approximation analog-to-digital conversion module is configured to obtain the low M-bit digital signal through the K-bit resistor string and the M-bit capacitance digital-to-analog conversion array, and the low M-bit digital signal is based on The high K-bit digital signal is obtained in N-bit analog-to-digital conversion. 2 . The analog-to-digital conversion circuit according to claim 1 , wherein the N-bit successive approximation analog-to-digital conversion module is configured to: digitize the high K-bit digital signal through the K-bit resistor string. 3 . analog-to-analog conversion, and obtain the low M-bit digital signal through the M-bit capacitance digital-to-analog conversion array. 3. analog-to-digital conversion circuit according to claim 2, is characterized in that, also comprises: a first switch module, configured to control the K-bit resistor string to output a first reference voltage signal according to the high-K-bit digital signal or the temperature code corresponding to the high-K-bit digital signal; The reference signal terminals corresponding to each capacitor in the M-bit capacitor digital-to-analog conversion array are configured to receive the first reference voltage signal. 4 . The analog-to-digital conversion circuit according to claim 1 , wherein the N-bit successive approximation analog-to-digital conversion module is configured to: according to the high-k-bit digital signal or the corresponding high-k-bit digital signal. 5 . The temperature encoding of the M-bit capacitance digital-to-analog conversion array is controlled to perform digital-to-analog conversion, and the low M-bit digital signal is obtained through the M-bit capacitance digital-to-analog conversion array and the K-bit resistor string. 5. The analog-to-digital conversion circuit according to claim 4, wherein the M-bit capacitance digital-to-analog conversion array comprises: a high-K-bit capacitance digital-to-analog conversion array, a low M-K-bit capacitance digital-to-analog conversion array, and a compensation capacitor; The fully parallel analog-to-digital conversion module is configured to control the high-k-bit capacitance digital-to-analog conversion array according to the high-k-bit digital signal or the temperature code corresponding to the high-k-bit digital signal; The N-bit successive approximation analog-to-digital conversion module includes: an M-bit successive approximation logic unit, the M-bit successive approximation logic unit is configured to output an M-bit control signal, and the M-bit control signal is used to control the low M-K bits A capacitor digital-to-analog conversion array and the K-bit resistor string are used to obtain the low M-bit digital signal. 6. The analog-to-digital conversion circuit according to claim 5, wherein the M-bit control signal comprises a first control signal and a second control signal; the analog-to-digital conversion circuit further comprises: The second switch module is configured to control the K-bit resistor string to output a second reference voltage signal according to the first control signal, wherein the reference signal terminal corresponding to the compensation capacitor is configured to receive the second reference voltage signal reference voltage signal; The low M-K bit capacitance digital-to-analog conversion array is configured to receive the second control signal for digital-to-analog conversion. 7. An analog-to-digital conversion method for an analog-to-digital conversion circuit, wherein the analog-to-digital conversion circuit comprises: a fully parallel analog-to-digital conversion module, comprising: a K-bit resistor string; an N-bit successive approximation analog-to-digital conversion module, including : M-bit capacitance digital-to-analog conversion array, the N-bit successive approximation analog-to-digital conversion module is used to perform N-bit analog-to-digital conversion on the analog input signal and obtain an N-bit digital signal, and the N-bit digital signal includes high K-bit digital signals Signal and low M-bit digital signal; wherein, N=K+M, and K, M and N are positive integers; The analog-to-digital conversion method includes: The fully parallel analog-to-digital conversion module samples and converts the analog input signal to obtain the high K-bit digital signal; The N-bit successive approximation analog-to-digital conversion module obtains the low M-bit digital signal through the K-bit resistor string and the M-bit capacitance digital-to-analog conversion array, and the low M-bit digital signal is based on the high K-bit digital signal. The bit digital signal is obtained in N-bit analog-to-digital conversion. 8 . The analog-to-digital conversion method according to claim 7 , wherein the N-bit successive approximation analog-to-digital conversion module obtains the low M by the K-bit resistor string and the M-bit capacitance digital-to-analog conversion array. 9 . Bit digital signal, including: Digital-to-analog conversion is performed on the high-k-bit digital signal through the K-bit resistor string, and the low-M-bit digital signal is obtained through the M-bit capacitance digital-to-analog conversion array. 9 . The analog-to-digital conversion method according to claim 8 , wherein the digital-to-analog conversion is performed on the high K-bit digital signal by the K-bit resistor string, and the digital-to-analog conversion is performed by the M-bit capacitor. 10 . The array obtains the low M-bit digital signal, including: The K-bit resistor string is controlled to output a first reference voltage signal according to the high-K-bit digital signal or the temperature code corresponding to the high-K-bit digital signal, wherein each of the M-bit capacitance digital-to-analog conversion arrays The reference signal terminal corresponding to the capacitor receives the first reference voltage signal. 10 . The analog-to-digital conversion method according to claim 7 , wherein the N-bit successive approximation analog-to-digital conversion module obtains the low M value through the K-bit resistor string and the M-bit capacitor digital-to-analog conversion array. 11 . Bit digital signal, including: According to the high-K-bit digital signal or the temperature code corresponding to the high-K-bit digital signal, the M-bit capacitance digital-to-analog conversion array is controlled to perform digital-to-analog conversion, and the M-bit capacitance digital-to-analog conversion array and the The K-bit resistor string obtains the low M-bit digital signal. 11. The analog-to-digital conversion method according to claim 10, wherein the M-bit capacitance digital-to-analog conversion array comprises: a high-K-bit capacitance digital-to-analog conversion array, a low M-K-bit capacitance digital-to-analog conversion array, and a compensation capacitor; Wherein, obtaining the low M-bit digital signal through the M-bit capacitance digital-to-analog conversion array and the K-bit resistor string includes: outputting an M-bit control signal, wherein the M-bit control signal is used to control the low-M-K-bit capacitance digital-to-analog conversion array and the K-bit resistor string to obtain the low-M-bit digital signal; and the M-bit control signal the signal includes a first control signal and a second control signal; The K-bit resistor string is controlled to output a second reference voltage signal according to the first control signal, wherein the reference signal terminal corresponding to the compensation capacitor is configured to receive the second reference voltage signal; The low M-K bit capacitance digital-to-analog conversion array is controlled according to the second control signal to perform digital-to-analog conversion. 12. A chip, characterized by comprising the analog-to-digital conversion circuit according to any one of claims 1 to 6. 13. An electronic device, comprising: the analog-to-digital conversion circuit according to any one of claims 1 to 6.

Images