CN115037984A - High-efficiency reversing control system and method based on video decoding chip - Google Patents

Abstract

The invention discloses a high-efficiency reversing control system based on a video decoding chip, which comprises a reversing system, a decoding chip, a microcontroller MCU, a flash memory unit, a liquid crystal display screen and a system level chip SOC, wherein the decoding chip is connected with the microcontroller MCU; a high-efficiency reversing control method based on a video decoding chip is characterized in that a microcontroller MCU inputs a channel switching instruction to the decoding chip through an IIC integrated circuit bus, and performs switching control on a normal interface data flow channel corresponding to a low-voltage differential signal LVDS input by a system-on-chip SOC and a reversing interface data flow channel corresponding to a composite synchronous video broadcast signal input by a reversing system; the decoding chip can output the input image data stream to the liquid crystal display screen for display after carrying out corresponding image quality adjustment and synthesis processing on the input image data stream so as to achieve the realization of the reversing function. The invention releases the system resources occupied by the backing function of the original SOC terminal, solves the bad phenomena of unstable part of the system, blocked picture, delayed backing image output, slower quick backing response and the like, and improves the user experience.

Description

An efficient reversing control system and method based on video decoding chip

technical field

The invention relates to the field of vehicle electronics, in particular to an efficient reversing control system and method based on a video decoding chip.

Background technique

In the current vehicle reversing scheme, the Kernel (kernel) in most SOCs (system-on-chips) integrated with operating systems such as Linux or Android controls a single camera to output a reversing image NTSC (abbreviation of National Television Standards Committee, meaning "(US) National Television Standards) Committee", this document only represents "composite synchronous video broadcast signal", which is the same as CVBS) screen, its scheme occupies more OS (operating system) resources, and the reversing response speed is generally low. Especially during the host startup process, because the system needs to start many threads, there may be undesired phenomena such as system instability, screen stuck, delayed reversing image output, and slow response to fast reversing. Degrade user experience.

Generally, the safety guarantee function of "warning classical Chinese" cannot be directly prompted in the NTSC picture of the composite synchronous video broadcast signal of the reversing image. In order to complete such "warning classical language" prompt function requirements, the OS (operating system) needs to synthesize the "warning classical Chinese" picture with the original camera composite synchronized video broadcast signal NTSC after obtaining the NTSC picture of the composite synchronous video broadcast signal of the camera. Output to screen display. This solution will increase the resources related to the operating system OS again, causing more obvious screen freezes and delays, and further reducing the user experience.

The on-board reversing system in the mass-produced host project in the early stage, because the operating system OS occupies a lot of system resources in the process of reversing, resulting in a slow start time (about 3.0s) for fast reversing, which cannot meet the current fast reversing startup time specification for new development projects (less than 1.2s). At the same time, the operating system OS occupies a lot of system resources, which will also lead to undesired phenomena such as system instability, screen stuck, delayed display of the reversing screen, and slow response to fast reversing, resulting in low user experience.

SUMMARY OF THE INVENTION

The purpose of the present invention is to overcome the defects of the prior art, to provide a high-efficiency reversing control system and method based on a video decoding chip, to release the system resources originally occupied by the SOC end due to the reversing function, and to solve some system instability, picture stuck, reversing Undesirable phenomena such as image output delay and slow response to fast reversing improve user experience.

On the one hand, the purpose of the present invention is achieved in this way: An efficient reversing control method based on a video decoding chip, comprising the following steps:

1) The microcontroller MCU inputs the channel switching command to the decoding chip through the IIC integrated circuit bus, and corresponds to the normal interface data stream channel corresponding to the low-voltage differential signal LVDS input by the system-on-chip SOC and the composite synchronous video broadcast signal input by the reversing system. The data flow channel of the reversing interface is switched and controlled;

2) When switching to the normal interface data stream channel, the decoding chip processes the video signal output by the system-on-chip SOC and outputs it to the liquid crystal display;

3) When switching to the data stream channel of the reversing interface, the decoding chip synthesizes the "warning classical Chinese" picture stored in the peripheral flash memory unit into the composite synchronous video broadcast signal picture of the reversing image, and then converts it into a dual-channel low-voltage differential signal LVDS signal and output to the LCD screen.

Further, the step 2) specifically includes:

2-1) The microcontroller MCU inputs the normal interface data stream channel switching command corresponding to the low-voltage differential signal LVDS input by the system-on-chip SOC to the decoding chip through the IIC integrated circuit bus;

2-2) The system-on-chip SOC outputs the normal interface data stream corresponding to the low-voltage differential signal LVDS to the decoding chip;

2-3) The decoding chip outputs the processed low-voltage differential signal LVDS to the liquid crystal display for display.

Further, the step 3) specifically includes:

3-1) The microcontroller MCU inputs the data stream channel switching instruction of the reversing interface corresponding to the composite synchronous video broadcast signal input by the reversing system to the decoding chip through the IIC integrated circuit bus;

3-2) The reversing system outputs the data stream of the reversing interface corresponding to the composite synchronous video broadcast signal to the decoding chip;

3-3) The decoding chip performs image synthesis between the “warning classical Chinese” picture obtained from the flash memory unit through the SPI serial peripheral interface and the reversing interface corresponding to the composite synchronous video broadcast signal input by the reversing system; the synthesized reversing image is then processed by the decoding chip. Internally converted to dual-channel low-voltage differential signal LVDS for output;

3-4) The decoding chip outputs the synthesized dual-channel low-voltage differential signal LVDS to the liquid crystal display for display.

Another aspect of the present invention is achieved in this way: an efficient reversing control system based on a video decoding chip, including a reversing system, a decoding chip, a microcontroller MCU, a flash memory unit, a liquid crystal display, and a system-level chip SOC;

The decoding chip is used to decode the composite synchronous video broadcast signal of the reversing system obtained through the CVBS input port, and output the video signal to the liquid crystal display screen through the dual-channel low-voltage differential signal LVDS output port;

The microcontroller MCU is connected with the decoding chip through the IIC integrated circuit bus, and is used for normal data transmission and reception, and realizes the switching between the normal picture and the reversing picture channel of the host through the operation of the register of the decoding chip;

The flash memory unit is connected with the decoding chip through a serial peripheral interface, and is used to store the picture of "warning classical Chinese";

The system-on-chip SOC is used to output the video signal to the decoding chip through the low-voltage differential signal LVDS;

The reversing system is used to output the data stream of the reversing interface corresponding to the composite synchronous video broadcast signal to the decoding chip;

The liquid crystal display screen is used to display the normal picture and the reversing picture after the synthesis processing of the decoding chip.

Further, the decoding chip is provided with a digital video input end, an analog signal input end, a display output end, an SPI serial peripheral interface and an IIC integrated circuit bus.

Further, the digital video input terminal is connected to the system-on-chip SOC, and is used for receiving the low-voltage differential signal LVDS signal output by the system-on-chip SOC;

The analog signal input end is connected with the reversing system, and is used for receiving the composite synchronous video broadcast signal video signal of the reversing system;

The display output terminal is connected to the liquid crystal display screen for image display;

The SPI serial peripheral interface is connected to the flash memory unit, and is used to obtain the picture information of "warning classical Chinese" accessed in the flash memory unit;

The IIC integrated circuit bus is connected to the microcontroller MCU for controlling the display chip.

Compared with the prior art, the present invention adopts the above technical scheme, and compared with the prior art, the beneficial effects are as follows: the video decoding chip is used to control the reversing picture, the system resources originally occupied by the SOC end of the system-level chip due to the reversing function are released, and the instability of part of the system is solved. Picture stuck, reversing image output delay and fast reversing response are slow and other undesirable phenomena, improve the user experience, among which the fast reversing start time can be reduced from the original 3.0s to less than 1.2s; the video decoding chip can also use OSD (On-Screen -Display) technology, the "warning classical Chinese" pictures stored in the peripheral flash memory unit FLASH are synthesized into the NTSC picture of the composite synchronous video broadcast signal of the reversing image, and then converted into a dual-channel signal low-voltage differential LVDS signal by the decoding chip, which is output to The screen display improves the efficiency and safety of the reversing function; the control method of the video decoding chip uses the microcontroller MCU to switch and control the normal interface output by the display chip and the channel of the reversing interface through the IIC integrated circuit bus command, so as to achieve the reversing function. Realization, the decoding function and the picture synthesis function are all completed by the display chip, which occupies less MCU system resources and can improve the fast reversing response time.

Description of drawings

Fig. 1 is a schematic diagram of the system structure of the present invention.

Fig. 2 The internal structure and part of the external interface of the decoding chip of the present invention.

Figure 3 is a block diagram of the normal mode of the present invention.

FIG. 4 is a schematic diagram of the internal data flow in the normal interface of the present invention.

Figure 5 is a block diagram of the reverse mode of the present invention.

6 is a schematic diagram of the internal data flow of the reversing interface of the present invention.

FIG. 7 is a connection diagram of the decoding chip of the present invention and the microcontroller MCU circuit.

FIG. 8 is a schematic diagram of the connection between the decoding chip of the present invention and the SOC circuit of the system-on-chip.

FIG. 9 is a schematic diagram of the circuit connection between the decoding chip of the present invention and the liquid crystal display screen.

FIG. 10 is a schematic diagram of the circuit connection between the decoding chip and the flash memory unit of the present invention.

FIG. 11 is a circuit schematic diagram of the flash memory cell of the present invention.

Fig. 12 is a circuit schematic diagram of the microcontroller MCU of the present invention.

FIG. 13 is a circuit schematic diagram of the system-on-chip SOC of the present invention.

Detailed ways

As shown in Figure 1, an efficient reversing control system based on a video decoding chip includes a reversing system, a decoding chip, a microcontroller MCU, a flash memory unit, a liquid crystal display screen and a system-on-chip SOC;

The decoding chip is used to decode the composite synchronous video broadcast signal of the reversing system obtained through the CVBS input port, and output the video signal to the LCD screen through the dual-channel low-voltage differential signal LVDS output port;

The microcontroller MCU is connected with the decoding chip through the IIC integrated circuit bus, which is used for normal data transmission and reception, and through the operation of the decoding chip register, the switching between the normal picture and the reversing picture channel of the host is realized;

The flash memory unit is connected with the decoding chip through the serial peripheral interface, which is used to store the pictures of "Warning Classical Language";

The system-on-chip SOC is used to output the video signal to the decoding chip through the low-voltage differential signal LVDS;

The reversing system is used to output the data stream of the reversing interface corresponding to the composite synchronous video broadcast signal to the decoding chip;

The LCD screen is used to display the normal picture and the reversing picture after the synthesis processing of the decoding chip.

As shown in Figure 2, the decoding chip is provided with a digital video input end, an analog signal input end, a display output end, an SPI serial peripheral interface and an IIC integrated circuit bus.

The digital video input terminal (Digital Video input) is connected to the system-on-chip SOC, and is used to receive the low-voltage differential LVDS signal output by the system-on-chip SOC;

The analog signal input (Analog video input) VIN1 is connected to the reversing system, and is used to receive the composite synchronous video broadcast signal NTSC video signal of the reversing system;

Display output (Display output, LVDS Dual or VLDS Single low-voltage differential signal, dual or single) is connected to the LCD screen for image display;

The SPI serial peripheral interface is connected to the flash memory unit, and is used to obtain the picture information of "Warning Classical Language" accessed in the flash memory unit;

The IIC integrated circuit bus is connected to the microcontroller MCU for controlling the display chip.

Decoding chip internal image processing unit:

The low-voltage differential LVDS signal output by the system-on-chip SOC enters the digital video input terminal (Digital Videoinput) and passes through: LVDS Rx (LVDS input), Digital I/F (digital interface), RGB/YC conversion (RGB/YC conversion) ;

After the composite synchronous video broadcast signal NTSC video signal of the reversing system enters the analog video input (Analog video input), it goes through: ADC (Analog-to-Digital Converter), VideoDecoder (video decoding), I/P conversion (Intra-field interpolation), Reduction scaling, Expansion scaling;

Then select the video input source channel through the multiplexer MUX (Multiplexer), and the signal passes through YC offset, gain (bright color compensation, gain), Y contrast (Y contrast), Hue adjustment (color adjustment), YC/RGB conversion (YC/RGB conversion), Area selection (domain selection), RGB contrast (RGB contrast), RGB offset (RGB compensation), Gamma correction (gamma correction), ROM-OSD (ROM, OSD image synthesis), Dither/FRC (error diffusion (error diffusion) / Frame Rate Control (frame rate control)), LCD I/F (LCD interface), and finally output to the LCD screen through LVDS Tx (LVDS output).

An efficient reversing control method based on a video decoding chip, comprising the following steps:

1) The microcontroller MCU inputs the channel switching command to the decoding chip through the IIC integrated circuit bus, and corresponds to the normal interface data stream channel corresponding to the low-voltage differential signal LVDS input by the system-on-chip SOC and the composite synchronous video broadcast signal input by the reversing system. The data flow channel of the reversing interface is switched and controlled;

2) When switching to the normal interface data stream channel, the decoding chip processes the video signal output by the system-on-chip SOC and outputs it to the liquid crystal display;

As shown in Figure 3-4, step 2 specifically includes:

2-1) The microcontroller MCU inputs the normal interface data stream channel switching command corresponding to the low-voltage differential signal LVDS input by the system-on-chip SOC to the decoding chip through the IIC integrated circuit bus;

2-2) The system-on-chip SOC outputs the normal interface data stream corresponding to the low-voltage differential signal LVDS to the decoding chip;

2-3) The decoding chip outputs the processed low-voltage differential signal LVDS to the liquid crystal display TFT-LCD for display.

3) When switching to the data stream channel of the reversing interface, the decoding chip synthesizes the "warning classical Chinese" picture stored in the peripheral flash memory unit into the composite synchronous video broadcast signal picture of the reversing image, and then converts it into a dual-channel low-voltage differential signal LVDS signal and output to the LCD screen.

As shown in Figure 5-6, step 3 specifically includes:

3-1) The microcontroller MCU inputs the data stream channel switching command of the reversing interface corresponding to the composite synchronous video broadcast signal NTSC input by the reversing system to the decoding chip through the IIC integrated circuit bus;

3-2) The reversing system outputs the data stream of the reversing interface corresponding to the composite synchronous video broadcast signal NTSC to the decoding chip;

3-3) The “warning classical Chinese” picture obtained by the decoding chip from the flash memory unit FLASH through the SPI serial peripheral interface and the reversing interface corresponding to the composite synchronous video broadcast signal NTSC input by the reversing system are combined for image synthesis; the synthesized reversing image is then processed by The decoding chip is internally converted into a dual-channel low-voltage differential signal LVDS for output;

3-4) The decoding chip outputs the synthesized dual-channel low-voltage differential signal LVDS to the liquid crystal display TFT-LCD for display.

As shown in Figure 7, the decoding chip is connected to the microcontroller MCU through the IIC integrated circuit bus interface (Figure 12), and obtains the composite synchronous video broadcast signal NTSC video signal of the reversing system (CAMERA SYSTEM) through the CVBS input port;

The composite synchronous video broadcast signal output by the external reversing system (CAMERA SYSTEM) (NTSC is connected to the decoding chip VIN1 (72pin) through the hard wire CAMERA_CVBS;

The pin SCL (25pin) and pin SDA (26pin) of the decoding chip are connected to the hard MCU_I2CL0_3V3_SCL and MCU_I2CL0_3V3_SDA in the microcontroller MCU (Figure 12) through the hard wires 86304_IIC_SCL and 86304_IIC_SDA, and are connected to the pin RIIC0SDL (27pin) of the microcontroller MCU ) and RIIC0SDA (26pin).

As shown in Figure 8, the decoding chip obtains the video signal of the system-on-chip SOC (Figure 13) through the low-voltage differential signal LVDS input port; the LVDS input pins of the decoding chip RD0AN (102pin),

RD0AP (103pin), RD1AN (104pin), RD1AP (105pin), RD2AN (106pin), RD2AP (107pin), RCKAN (108pin), RCKAP (109pin), RD3AN (110pin), RD3AP (111pin) via hard wire, LVDS0_DATA0_N, LVDS0_DATA0_P、LVDS0_DATA1_N、LVDS0_DATA1_P、LVDS0_DATA2_N、LVDS0_DATA2_P、LVDS0_CLK_N、LVDS0_CLK_P、LVDS0_DATA3_N、LVDS0_DATA3_P连接至系统级芯片SOC（图13）的MIPI_DSI1_DATA0_N(AN15pin)、MIPI_DSI1_DATA0_P(AR15pin)、MIPI_DSI1_DATA1_N(AN17pin)、MIPI_DSI1_DATA1_P(AR17pin)、MIPI_DSI1_DATA2_N( AM14pin), MIPI_DSI1_DATA2_P(AP14pin), MIPI_DSI1_CLK_N(AM16pin), MIPI_DSI1_CLK_P(AP16 pin), MIPI_DSI1_DATA3_N(AN18 pin), MIPI_DSI1_DATA3_P(AP18 pin).

As shown in Figure 9, the decoding chip outputs the video signal to the TFT-LCD (liquid crystal display) through the dual-channel low-voltage differential signal LVDS output port;

LVDS output pins of decoding chip TD3AP(49pin), TD3AN(50pin), TCKAP(51pin), TCKAN(52pin), TD2AP(53pin), TD2AN(54pin), TD1AP(55pin), TD1AN(56pin), TD0AP(57pin) ), TD0AN(58pin), TD3BP(37pin), TD3BN(38pin), TCKBP(39pin), TCKBN(40pin), TD2BP(41pin), TD2BN(42pin), TD1BP(43pin), TD1BN(44pin), TD0BP(45pin) ), TD0BN (46pin) through hard wire ODD_LVDS_DATA3_P, ODD_LVDS_DATA3_P

ODD_LVDS_CLK_P、ODD_LVDS_CLK_P、ODD_LVDS_DATA2_P、ODD_LVDS_DATA2_P、ODD_LVDS_DATA1_P、ODD_LVDS_DATA1_P、ODD_LVDS_DATA0_P、ODD_LVDS_DATA0_P、EVEN_LVDS_DATA3_P、EVEN_LVDS_DATA3_P、EVEN_LVDS_CLK_P、EVEN_LVDS_CLK_P、EVEN_LVDS_DATA2_P、EVEN_LVDS_DATA2_P、EVEN_LVDS_DATA1_P、EVEN_LVDS_DATA1_P、EVEN_LVDS_DATA0_P、EVEN_LVDS_DATA0_P连接至液晶显示屏TFT-LCD。

As shown in Figure 10, the decoding chip obtains the picture of "Warning Classical Language" in the flash memory unit (Figure 11) through the SPI serial peripheral interface;

The SPI pins QSD3(14pin), QSD2(15pin), QSD1(16pin), QSD0(17pin), QSCK(18pin), QSCS(19pin) of the decoding chip are connected by hard wire To the pins HOLD#/IO3(7pin), WP#/IO2(3pin), SO/IO1(2pin), SI/IO0(5pin), SCLK(6pin), CS#(1pin) of the flash unit FLASH (Figure 11) ).

When the invention works, the microcontroller MCU is connected to the decoding chip through the IIC integrated circuit bus interface, and the baud rate is 400bps, which can meet the normal data transmission and reception, and the microcontroller MCU can realize the DA (host) by operating the decoding chip register. Switch between normal screen and reversing screen channels, and meet the time specification for fast reversing start (less than 1.2s).

The flash memory unit FLASH can store the pictures of "warning classical Chinese", which is connected with the decoding chip through the SPI serial peripheral interface. Set the interface command to obtain the warning classical Chinese picture in the flash memory unit FLASH, and synthesize it with the composite synchronous video broadcast signal NTSC video signal output by the reversing system, and finally achieve the output of dual-channel LVDS (low voltage differential signal with "warning classical Chinese" safety prompt information. ) reversing video screen.

The invention is based on the microcontroller MCU controlling the decoding chip through the IIC integrated circuit bus, and realizes the short start time (less than 1.2s) of fast reversing.

The present invention is not limited to the above-mentioned embodiments. On the basis of the technical solutions disclosed in the present invention, those skilled in the art can make some substitutions and modifications to some of the technical features according to the disclosed technical contents without creative work. Modifications, replacements and modifications are all within the protection scope of the present invention.

Claims (6)

1. A high-efficiency reverse control method based on a video decoding chip is characterized by comprising the following steps:

1) the microcontroller MCU inputs a channel switching instruction to the decoding chip through the IIC integrated circuit bus, and performs switching control on a normal interface data flow channel corresponding to the low-voltage differential signal LVDS input by the system-level chip SOC and a data flow channel of the backing interface corresponding to the composite synchronous video broadcast signal input by the backing system;

2) when the data flow channel of the normal interface is switched, the decoding chip processes the video signal output by the SOC and outputs the video signal to the liquid crystal display screen;

3) when the data flow channel of the reversing interface is switched, the warning words stored in the peripheral flash memory unit are synthesized into a reversing image composite synchronous video broadcast signal picture by the decoding chip, then the warning words are converted into a double-path low-voltage differential signal LVDS signal, and the double-path low-voltage differential signal LVDS signal is output to the liquid crystal display screen.

2. The efficient reversing method based on the video decoding chip according to claim 1, wherein the step 2) specifically comprises:

2-1) the microcontroller MCU inputs a normal interface data flow channel switching instruction corresponding to the low voltage differential signal LVDS input by the system level chip SOC to the decoding chip through the IIC integrated circuit bus;

2-2) the system on chip SOC outputs the normal interface data stream corresponding to the low voltage differential signal LVDS to the decoding chip;

2-3) the decoding chip outputs the processed low-voltage differential signal LVDS to a liquid crystal display screen for displaying.

3. The efficient reversing method based on the video decoding chip according to claim 1, wherein the step 3) specifically comprises:

3-1) the microcontroller MCU inputs a data stream channel switching instruction of a backing interface corresponding to the composite synchronous video broadcast signal input by the backing system to a decoding chip through an IIC integrated circuit bus;

3-2) the reversing system outputs the data stream of the reversing interface corresponding to the composite synchronous video broadcast signal to a decoding chip;

3-3) the decoding chip carries out image synthesis on the warning language picture acquired from the flash memory unit through the SPI serial peripheral interface and the backing interface corresponding to the composite synchronous video broadcast signal input by the backing system; the synthesized reversing image is converted into a double-path low-voltage differential signal LVDS for output through the interior of a decoding chip;

and 3-4) the decoding chip outputs the synthesized two-way low voltage differential signal LVDS to a liquid crystal display screen for displaying.

4. A high-efficiency reversing control system based on a video decoding chip comprises a reversing system, and is characterized by further comprising a decoding chip, a microcontroller MCU, a flash memory unit, a liquid crystal display screen and a system on chip SOC;

the decoding chip is used for decoding the composite synchronous video broadcast signal of the reversing system acquired through the CVBS input port and outputting the video signal to the liquid crystal display screen through the dual-path low-voltage differential signal LVDS output port;

the microcontroller MCU is connected with the decoding chip through an IIC integrated circuit bus, is used for receiving and transmitting normal data, and realizes the switching of a normal picture and a reversing picture channel of the host machine through the operation of a register of the decoding chip;

the flash memory unit is connected with the decoding chip through a serial peripheral interface and is used for storing an alarm language picture;

the system-on-chip SOC is used for outputting a video signal to a decoding chip through a low-voltage differential signal LVDS;

the reversing system is used for outputting the data stream of the reversing interface corresponding to the composite synchronous video broadcast signal to the decoding chip;

and the liquid crystal display screen is used for displaying the normal picture and the reversing picture after the synthesis processing of the decoding chip.

5. The efficient reversing control system based on the video decoding chip as claimed in claim 4, wherein the decoding chip is provided with a digital video input terminal, an analog signal input terminal, a display output terminal, an SPI serial peripheral interface and an IIC integrated circuit bus.

6. The efficient reversing control system based on the video decoding chip according to claim 5, wherein the digital video input terminal is connected to the system-on-chip SOC and is configured to receive a low-voltage differential signal LVDS output by the system-on-chip SOC;

the analog signal input end is connected with the reversing system and used for receiving a composite synchronous video broadcast signal video signal of the reversing system;

the display output end is connected to the liquid crystal display screen and used for displaying images;

the SPI serial peripheral interface is connected to the flash memory unit and used for acquiring warning language picture information accessed in the flash memory unit;

the IIC integrated circuit bus is connected to the microcontroller MCU and used for controlling the display chip.

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