CN115064194A - Memory and decoupling method thereof - Google Patents

Abstract

The present invention provides a memory capable of removing noise generated by coupling during a write operation. By activating the decoupling enable signal at the same time when the write operation enable signal is activated, for the first falling edge of the third data clock signal and the fourth data clock signal without the corresponding rising edge to eliminate the coupling influence, use the decoupling enable The signal pulls down the reference voltage signal to eliminate the effects of the coupling described above on the reference voltage signal. Therefore, the adverse effect on the reference voltage caused by the coupling noise can be eliminated, the comparison accuracy of the comparator can be improved, and the performance of the memory can be improved.

Description

Memory and method of decoupling the same

technical field

The present invention relates to a memory, in particular to a memory capable of removing noise generated by coupling during a write operation.

Background technique

Regarding memory, it can be divided into read-only memory (ROM) and random access memory (RAM) according to the read-write function. The content stored in the read-only memory is fixed and can only be read but not written. Random access memory is a memory that can be both read and written. In addition, random access memory can be divided into SRAM (static random access memory) and DRAM (dynamic random access memory).

DRAM uses capacitors to store charge to store data, and requires a regular refresh circuit to overcome the problem of capacitor leakage. It is often used in large-capacity main memory, such as computers, smartphones, and server memory. DRAM can be divided into SDRAM, DDRSDRAM, RDRAM and so on.

Among them, SDRAM (Synchronous DRAM) is a clock-synchronized memory that operates based on a clock signal sent by a processor. Command signals for defining actions and address signals for specifying memory cells are sent in parallel and synchronized with the rising edge of the clock signal. DDR SDRAM (double data rate SDRAM: double data rate synchronous dynamic random access memory) is a memory with double data transfer rate, which can perform data transfer on both the rising and falling edges of the clock signal, that is, its data transfer speed is Twice the frequency of the clock signal, its transfer performance is better than that of conventional SDRAM due to the increased speed.

DDR SDRAM (hereinafter referred to as DDR) uses the DQ Strobe (DQS) signal as a source synchronous clock to gate the data signal DQ and transmit data through the DQ bus. Command signals and address signals are only synchronized to the rising edge of the clock signal DQS, while data signals are synchronized to the rising and falling edges of DQS. The clock signal, command signal, and address signal are unidirectionally input to the DDR from the processor, while DQS and DQ are bidirectional, input to the DDR when writing, and output from the DDR when reading.

A DDR receiver circuit usually has multiple (for example, four) parallel-connected comparators, and each comparator determines whether to select the data signal by comparing the input data signal with the reference voltage signal. For example, in the comparator COMP_A of the DDR receiver circuit of FIG. 1 described later, by comparing the voltage of the data signal DQ with the reference voltage VREFDQ, an output signal of 0 or 1 output from the output terminal OUT can be obtained OUTA.

When the comparator COMP_A is triggered by a certain signal edge of the clock signal DQSAb, if the input data signal DQ is near the reference voltage VREFDQ, due to the noise of the signal itself and the mismatch of circuit elements, it will be further coupled and Noise is generated, which reduces the accuracy of the comparator. In order to save power consumption, the reference voltage VREFDQ generally uses a weaker voltage (lower voltage value) during the normal writing operation, so the above-mentioned coupling noise will have a greater impact on the reference voltage VREFDQ, which in turn affects the comparator and even DDR overall performance.

SUMMARY OF THE INVENTION

For the above coupling noise, consider controlling the phase of the clock signal of each comparator, for example, the phases of the respective clock signals DQSAb, DQSBb, DQSCb, DQSDb of the four comparators in FIG. 1 are 90 degrees different from each other, that is, 0° , 90°, 180°, 270°. In this way, whenever a comparator begins to calibrate according to the falling edge of the clock signal applied to the comparator, there is an inverted rising edge of the data clock signal of another comparator to eliminate the falling edge caused by Coupling noise is decoupling.

However, according to the above phase settings, the clock signals DQSAb, DQSBb start the first falling edge at the same time or after the comparator is triggered in normal operation, and the first falling edge of DQSCb and DQSDb are before the comparator is triggered. Appear. For the first falling edges of the two clock signals DQSCb and DQSDb, there is no corresponding rising edge like the first falling edges of DQSAb and DQSBb to eliminate the influence of coupling noise. Therefore, the first falling edges of the clock signals DQSCb and DQSDb The coupling effect caused by each falling edge to the reference voltage VREFDQ is not eliminated, therefore, the coupling noise will affect the accuracy of the comparator, thereby affecting the overall performance of the memory.

The present invention has been made to solve the above-mentioned problems, and an object thereof is to provide a memory capable of removing noise generated by coupling during a write operation. By activating the decoupling enable signal at the same time when the write operation enable signal is activated, for the first falling edge of the third data clock signal and the fourth data clock signal without the corresponding rising edge to eliminate the coupling influence, use the decoupling enable The signal pulls down the reference voltage signal to eliminate the effects of the coupling described above on the reference voltage signal. Therefore, the adverse effect on the reference voltage caused by the coupling noise can be eliminated, the comparison accuracy of the comparator can be improved, and the performance of the memory can be improved.

The memory involved in the first aspect of the present invention can remove noise generated by coupling during a write operation, including:

an input receiving unit, the input receiving unit is provided with an interface for converting serial input into parallel output, and a first comparator, a second comparator, a third comparator, and a fourth comparator connected in parallel to the interface, The clock signal input terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator respectively input the divided first data clock signal, the second data clock signal, and the third Three data clock signals and a fourth data clock signal, respectively input reference voltage signals to the reference voltage input terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator, A data signal is input to the data signal input terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator, respectively, and the reference voltage signal and the data signal are processed. Compare and output the comparison result;

a control unit that generates a control signal based on the respective comparison results of the first comparator, the second comparator, the third comparator, and the fourth comparator; and

a storage unit that stores at least a data signal compared and gated by the first comparator, the second comparator, the third comparator, and the fourth comparator, and the first comparison the comparison results of the comparator, the second comparator, the third comparator, and the fourth comparator,

The phases of the first data clock signal, the second data clock signal, the third data clock signal, and the fourth data clock signal differ by 90° respectively, and the first data clock signal falls The edge corresponds to the first rising edge of the third data clock signal, the first falling edge of the second data clock signal corresponds to the first rising edge of the fourth data clock signal,

Decoupling capacitors are respectively connected to the reference voltage input terminals of the third comparator and the fourth comparator, and the third data clock signal or the fourth data is respectively applied to the decoupling capacitors The decoupling enable signal corresponding to the clock signal.

Preferably, in the second aspect of the present invention, in the memory according to the first aspect of the present invention,

The decoupling enable signal applied to the decoupling capacitor of the third comparator is triggered at the first falling edge of the third data clock signal, thereby eliminating the first falling edge of the third data clock signal. A falling edge generates coupled noise on the reference voltage signal,

The decoupling enable signal applied to the decoupling capacitor of the fourth comparator is triggered at the first falling edge of the fourth data clock signal, thereby eliminating the first falling edge of the fourth data clock signal. A falling edge generates coupled noise on the reference voltage signal.

Preferably, in the third aspect of the present invention, in the memory related to the second aspect of the present invention,

The decoupling enable signal of the third comparator becomes a low level at the moment of the first falling edge of the third data clock signal,

The decoupling enable signal of the fourth comparator changes to a low level at the moment of the first falling edge of the fourth data clock signal.

Preferably, in the fourth aspect of the present invention, in the memory related to the third aspect of the present invention,

The decoupling enable signal of the third comparator and the decoupling enable signal of the fourth comparator are reset to a high level when a write operation of the memory is completed.

Preferably, in the fifth aspect of the present invention, in the memory related to the first aspect of the present invention,

The decoupling enable signal of the third comparator and the decoupling enable signal of the fourth comparator are generated according to a global reset signal and a write operation enable signal of the memory.

Preferably, in the sixth aspect of the present invention, in the memory related to the first aspect of the present invention,

After the first falling edge of the first data clock signal, each signal edge of the first data clock signal is inverted with each signal edge of the third data clock signal,

After the first falling edge of the second data clock signal, each signal edge of the second data clock signal is inverted with each signal edge of the fourth data clock signal.

Preferably, in the seventh aspect of the present invention, in the memory according to any one of the first to sixth aspects of the present invention,

The memory is DDR (Double Rate Synchronous Dynamic Random Access Memory).

The decoupling method involved in the eighth aspect of the present invention can remove the noise generated by the coupling when the memory performs the write operation,

The memory includes:

an input receiving unit, the input receiving unit is provided with an interface for converting serial input into parallel output, and a first comparator, a second comparator, a third comparator, and a fourth comparator connected in parallel to the interface, The clock signal input terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator respectively input the divided first data clock signal, the second data clock signal, and the third Three data clock signals and a fourth data clock signal, respectively input reference voltage signals to the reference voltage input terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator, A data signal is input to the data signal input terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator, respectively, and the reference voltage signal and the data signal are processed. Compare and output the comparison result;

a control unit that generates a control signal based on the respective comparison results of the first comparator, the second comparator, the third comparator, and the fourth comparator; and

a storage unit that stores at least a data signal compared and gated by the first comparator, the second comparator, the third comparator, and the fourth comparator, and the first comparison the comparison results of the comparator, the second comparator, the third comparator, and the fourth comparator,

The phases of the first data clock signal, the second data clock signal, the third data clock signal, and the fourth data clock signal differ by 90° respectively, and the first data clock signal falls The edge corresponds to the first rising edge of the third data clock signal, the first falling edge of the second data clock signal corresponds to the first rising edge of the fourth data clock signal,

Decoupling capacitors are respectively connected to the reference voltage input terminals of the third comparator and the fourth comparator, and the third data clock signal or the fourth data is respectively applied to the decoupling capacitors The decoupling enable signal corresponding to the clock signal.

Invention effect

According to the memory of the present invention, it is possible to remove noise due to coupling when a write operation is performed. By activating the decoupling enable signal at the same time when the write operation enable signal is activated, for the first falling edge of the third data clock signal and the fourth data clock signal without the corresponding rising edge to eliminate the coupling influence, use the decoupling enable The signal pulls down the reference voltage signal to eliminate the effects of the coupling described above on the reference voltage signal. Therefore, the adverse effect on the reference voltage caused by the coupling noise can be eliminated, the comparison accuracy of the comparator can be improved, and the performance of the memory can be improved.

Description of drawings

1 is a schematic circuit diagram showing a basic configuration of an input receiving unit of a memory and a specific configuration of a comparator according to Embodiment 1 of the present invention.

2 is a timing chart showing signals in the memory according to Embodiment 1 of the present invention.

3 is a schematic diagram showing a circuit for eliminating coupling noise in the memory according to Embodiment 1 of the present invention.

4 is a timing chart showing signals during a write operation in the memory according to Embodiment 1 of the present invention.

5 is a schematic diagram showing a configuration for eliminating coupling noise in the memory according to Embodiment 1 of the present invention.

6 is a logic circuit and a signal timing diagram showing the enable decoupling signal DECOUPLE_EN in the memory according to Embodiment 1 of the present invention.

Detailed ways

The present invention is described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. However, the present invention may be embodied in various forms and should not be limited to the embodiments set forth herein. The size and relative sizes of layers and regions may be exaggerated in the drawings for clarity.

For convenience of description, spatially relative terms, such as "below," "below," "under," "over," "over," etc. may be used herein to describe one element or feature as shown in the figures relative to another The relationship of an element or characteristic. It should be understood that spatially relative terms are intended to encompass different orientations of the device used or operated in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features.

Unless otherwise defined, terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms should be understood to have meanings that are consistent with their meanings in the context of the related art, and should not be understood as idealized or overly formalized, unless explicitly so defined herein.

<Embodiment 1>

The memory of the present invention includes an input receiving unit, a control unit and a storage unit. Hereinafter, an example in which the memory of the present invention is a DDR will be described, but the type thereof is not particularly limited, as long as it has the calibration function described in this application.

1 is a schematic circuit diagram showing the basic configuration of the input receiving unit 10 of the DDR memory according to Embodiment 1 of the present invention and the specific configuration of the comparator COMP_A.

As shown in FIG. 1 , the input receiving unit 10 of the DDR memory 100 includes an interface (not shown) for converting serial input into parallel output, and a first comparator COMP_A and a second comparator COMP_B connected in parallel to the interface. , the third comparator COMP_C, and the fourth comparator COMP_D (the structures of these comparators are basically the same, so they are also denoted as D_COMPATOR if they are not distinguished). The reference voltage input terminals of the first comparator COMP_A, the second comparator COMP_B, the third comparator COMP_C, and the fourth comparator COMP_D are connected to each other, and are respectively applied with the reference voltage signal VREFDQ. The data signal input terminals DQ_IN of the comparators COMP_A, COMP_B, COMP_C, and COMP_D receive the input (DQ_IN) of the data signal DQ to be stored.

In the input receiving unit 10, a serial data clock signal DQS is divided into four parallel data clock signals through its interface, namely the first data clock signal DQSAb, the second data clock signal DQSBb, the third data clock signal DQSCb, The fourth data clock signal DQSDb is respectively input to the clock signal input terminals CKb of the four comparators. Specifically, the first data clock signal DQSAb is input to the clock signal input terminal CKb of the first comparator COMP_A, the second data clock signal DQSBb is input to the clock signal input terminal CKb of the second comparator COMP_B, and the third data clock signal DQSBb is input to the clock signal input terminal CKb of the second comparator COMP_B. The clock signal DQSCb is input to the clock signal input terminal CKb of the third comparator COMP_C, and the fourth data clock signal DQSDb is input to the clock signal input terminal CKb of the fourth comparator COMP_D.

In each of the comparators COMP_A, COMP_B, COMP_C, and COMP_D, the reference voltage signal VREFDQ and the data signal DQ are compared respectively, and digital output signals OUTA, OUTB, OUTC, OUTD of 0 or 1 are output from the respective output terminals OUT according to the comparison results. .

The digital output signals OUTA, OUTB, OUTC, and OUTD are input to a calibration unit or a control unit (not shown) of the subsequent stage. For example, a calibration control unit composed of a driver, a pulse generator, a lock unit, etc. is connected to the rear stage of each comparator, and the calibration control unit generates a control signal based on the comparison result of the connected comparator and applies it to the comparison The control terminal of the comparator is used to control the comparator to perform calibration for eliminating the offset caused by the mismatch of circuit elements, and the detailed description thereof is omitted here.

The DDR memory also has a control unit and a storage unit (not shown), wherein the control unit generates a control signal to perform, for example, mismatch calibration based on the comparison results of the four comparators. The gated data signal DQ, and the above-mentioned output signals OUTA, OUTB, OUTC, OUTD and other signals.

The right side of FIG. 1 shows a schematic circuit diagram of the specific structure of the comparator D_COMPARATOR in the memory according to Embodiment 1 of the present invention. Here, the first comparator CMP_A is taken as an example to describe the basic structure of the comparator D_COMPARATOR.

As shown in the figure, the basic structure of the comparator COMP_A includes nine transistors P1-P9. In this embodiment, the transistors P1-P5 are PMOS, and the transistors P6-P9 are NMOS. The gates of the transistors P1, P6 and P7 are connected to the clock signal input terminal CKb of the comparator D_COMPATOR, the gate of the transistor P2 is connected to the reference voltage input terminal VREFDQ, and the gate of the transistor P3 is connected to the data signal input terminal DQ_IN. In addition, VSS and OUT in the figure represent the source voltage and the output terminal of the comparator D_COMPATOR, respectively. The comparator COMP_A compares the reference voltage signal VREFDQ and the data signal DQ (DQ_IN) under the trigger of the clock signal DQSAb with the structure shown in the figure, and outputs a digital output signal OUTA of 0 or 1 from the output terminal OUT according to the comparison result.

2 is a timing chart showing signals in the memory according to Embodiment 1 of the present invention. In the figure, the data signal DQ is 0, 1, ..., 9, a, b, ..., f, a total of 16 bits of data. The clock signals DQS_t and DQS_c are mutually inverse signals, and are divided into clock signals DQSAb, DQSBb, DQSCb and DQSDb which are respectively input to the four comparators CMP_A, CMP_B, CMP_C and CMP_D. Each comparator is triggered on the signal edge (falling edge in this embodiment) of each clock signal, compares the reference voltage signal VREFDQ and the data signal DQ, and outputs respective output signals OUTA, OUT, OUTC, and OUTD according to the comparison results.

As mentioned above, the circuit elements in the comparator are mismatched, and the input signal is inevitably distorted. Therefore, when the data signal DQ is close to the reference voltage signal VREFDQ or within a certain range near the reference voltage signal VREFDQ When , the offset of the comparator is caused by the mismatch of the circuit components, and when calibrating, the noise generated by the coupling will affect the reference voltage signal VREFDQ with a small value, resulting in a decrease in the performance and accuracy of the comparator.

In contrast, in Embodiment 1 of the present invention, the phases of the first data clock signal DQSAb, the second data clock signal DQSBb, the third data clock signal DQSCb, and the fourth data clock signal DQSDb input to the four comparators are respectively Set to 0°, 90°, 180°, 270°. As shown in FIG. 2 , for the data of the first bit “0” of the data signal DQ, the timing of triggering corresponds to the falling edge of the first data clock signal DQSAb, so the output terminal OUTA of the first comparator CMP_A outputs information about this data. Comparison result of data "0". It should be noted that, at the trigger timing of the data "0", in addition to the falling edge of the first data clock signal DQSAb, the rising edge of the third data clock signal DQSCb is also set. That is, the trigger edge of the data of the first bit "0" corresponds to the falling edge of the first data clock signal DQSAb and the rising edge of the third data clock signal DQSCb at the same time. Likewise, the trigger edge of the data of the second bit "1" corresponds to the falling edge of the second data clock signal DQSBb and the rising edge of the fourth data clock signal DQSDb at the same time. The trigger edge of the data of the third bit "2" corresponds to the falling edge of the third data clock signal DQSCb and the rising edge of the first data clock signal DQSAb at the same time. The trigger edge of the data of the fourth bit "3" corresponds to the falling edge of the fourth data clock signal DQSDb and the rising edge of the second data clock signal DQSBb at the same time. The trigger edge of the following 5th to 16th data is deduced by analogy.

3 is a schematic diagram illustrating a circuit for eliminating coupling noise by using the first falling edge of the first data clock signal DQSAb and the first rising edge of the third data clock signal DQSCb in the memory according to this embodiment.

An example of the structure of the first comparator COMP_A and the third comparator COMP_C and the waveforms of the clock signals DQSAb and DQSCb is shown in FIG. 3 . When the first falling edge of DQSAb is input to the gate of the transistor P1 of the first comparator COMP_A, that is, the clock signal input terminal, the voltage of the transistor P1 will be pulled down, and the gate of the transistor P1 and the transistor P2 (the gate of the transistor P2) will be pulled down. The coupling capacitance generated between the two poles, namely the reference voltage input terminal VREFDQ) causes the voltage at the transistor P6 to rise, which is equivalent to the case where the reference voltage VREFDQ rises. At this time, by simultaneously inputting the first rising edge of DQSCb to the gate of the transistor P1 of the third comparator COMP_C, that is, the input terminal of the clock signal, the voltage of the transistor P1 will be pulled up, and the third comparator COMP_C The coupling capacitance generated between the transistor P1 and the transistor P2 in the circuit causes the raised reference voltage VREFDQ to be discharged through the transistor P6, that is, the reference voltage VREFDQ drops, so that the first falling edge of DQSAb and the first rising edge of DQSCb Inverted, so that the rise and fall of the reference voltage VREFDQ cancel each other, thereby eliminating the adverse effects caused by coupled noise.

FIG. 3 also shows waveform examples of the second data clock signal DQSBb and the fourth data clock signal DQSDb, which are similar to the cases of DQSAb and DQSCb, and will not be described again.

As described above, the data clock signals of the parallel-connected comparators in the memory of the present embodiment are shifted by 90°. Specifically, the first comparator, the second comparator, the third comparator, and the fourth comparator The phases of the respective data clock signals are 0°, 90°, 180°, and 270°, respectively, so that when the falling edge of any data clock signal triggers data, there is a corresponding rising edge of another inverted data clock signal. Therefore, it can not only perform offset calibration, but also eliminate the adverse effect on the reference voltage caused by the coupling noise during the calibration process, improve the comparison accuracy of the comparator, and improve the performance of the memory.

However, for the data clock signal, in the present invention, the high level is used as the initial state. Therefore, according to the phase setting of the above data clock signal, DQSAb and DQSBb start the first falling edge at the same time or after the data is triggered, The first falling edges of DQSCb and DQSDb both appear before the data is triggered. If the falling edge of the data clock signal occurs before the correct data is triggered, and there is no corresponding rising edge to eliminate the coupling noise caused by the falling edge, the wrong data will be triggered, which will cause the comparator to fail. As a result, the accuracy is reduced, which in turn affects the performance of the DDR memory.

4 is a timing chart showing signals during a write operation in the memory according to the embodiment of the present invention. In FIG. 4 , CKt, CKc, DQS_T, and DQS_C are two sets of clock signals whose phases are opposite to each other, and are used to generate clock signals required by the memory of this embodiment. The data signal DQ includes 16-bit data of D0, D1, D2, D3, ..., D15, which corresponds to the data signal DQ in the timing diagram of FIG. 2 . DQS_EN is the data clock enable signal, that is, the write operation enable signal. The waveforms of the data clock signals DQSAb, DQSBb, DQSCb, and DQSDb are the same as those shown in Figure 2 and Figure 3. Each falling edge has a corresponding rising edge to eliminate coupling noise. impact, which will not be repeated here.

In FIG. 4, the first falling edges of the data clock signals DQSCb, DQSDb are particularly marked. Since the two falling edges of DQSCb and DQSDb appear before the first falling edges of DQSAb and DQSBb, there is no corresponding rising edge to offset the two falling edges of DQSCb and DQSDb. Therefore, the first falling edge of DQSCb and DQSDb will cause coupling noise, and measures need to be taken to eliminate the resulting coupling noise.

FIG. 5 is a schematic diagram of the structure for eliminating coupling noise in the memory according to Embodiment 1 of the present invention. The figure shows the basic circuit structure for eliminating the coupling noise caused by the first falling edge of the data clock signals DQSCb and DQSDb, mainly showing the transistors P1-P3, the reference voltage input terminal VREFDQ, and the data signal input DQ_IN and the related structure of the clock signal input terminal, the illustration of other structures is omitted.

As shown in FIG. 5, when the first falling edge of the clock signal DQSCb/DQSDb is input to the gate of transistor P1, the voltage of transistor P1 will be pulled down, and the voltage of transistor P1 and transistor P2 (the gate of transistor P2 is Coupling occurs between the reference voltage input terminals VREFDQ), which is equivalent to generating a coupling capacitor C1. As described in Figure 3, this coupling capacitor C1 can cause noise in the comparators COMP_C or COMP_D.

In this regard, in this embodiment, the above-mentioned coupling noise is eliminated by providing a capacitor C2 connected to the reference voltage input terminal VREFDQ. Therefore, the capacitor C2 is referred to as a decoupling capacitor C2. And, the decoupling enable signal DECOUPLE_EN is input to the decoupling capacitor C2 to eliminate coupling noise generated by the first falling edge of the data clock signal DQSCb or DQSDb.

Specifically, on the first falling edge of the data clock signal DQSCb or DQSDb, the decoupling enable signal DECOUPLE_EN also generates a corresponding falling edge. The voltage produces a pull-down effect, so that coupling also occurs between the decoupling capacitor C2 (decoupling enable signal DECOUPLE_EN) and the gate of the transistor P2 (reference voltage input terminal VREFDQ), which is equivalent to generating a coupling capacitor C3 (essentially decoupling Coupling capacitor C3). The coupling capacitor C3 and the coupling capacitor C1 cancel each other out, thereby eliminating the above-mentioned coupling noise.

The signal timing chart of the decoupling method used in the memory according to Embodiment 1 is shown in the lower part of FIG. 6 . DQS_EN is the data clock enable signal, that is, when DQS_EN is high, each data clock signal DQSAb, DQSBb, DQSCb, DQSDb starts their respective signal edges (as shown in Figure 2). In FIG. 6 , only the signal edges of the data clock signals DQSCb and DQSDb are shown, and the illustration of DQSAb and DQSBb is omitted.

As shown in FIG. 6 , when DQS_EN changes to a high level, the first falling edge of the data clock signal DQSCb or DQSDb occurs accordingly.

GRSTb is a global reset signal, RSTb is a reset signal, and reset signal RSTb is a combination of the global reset signal GRSTb and a pulse generated by the falling edge of the signal DQS_EN indicating write enable. The logic circuit of the reset signal RSTb is shown in the upper left side of FIG. 6, and the data clock enable signal DQS_EN is input through the delay chain, the NOT gate, or the signal after the NOR gate and the global reset signal GRSTb through the signal after the NOT gate. to the NOR gate to generate the reset signal RSTb. The logic circuit here is just an example, and any circuit configuration can be adopted as long as the reset signal RSTb shown in the figure can be generated.

Then, the reset signal RSTb, the data clock signal DQSCb or DQSDb are input to the circuit shown in the upper right side of FIG. 6 to generate the decoupling enable signal DECOUPLE_EN. The decoupling enable signal DECOUPLE_EN becomes a low level at the moment of the first falling edge of the data clock signal DQSCb or DQSDb. When it is applied to the reference voltage input terminal VREFDQ as shown in FIG. 5, the decoupling enable The falling edge of the signal DECOUPLE_EN can cancel the noise due to coupling on the reference voltage level VREFDQ.

Specifically, the falling edge of the decoupling enable signal DECOUPLE_EN has a pull-down effect on the level of the reference voltage VREFDQ (ie, negative coupling), thereby eliminating the coupling on the reference voltage VREFDQ caused by the first falling edge of the data clock signal DQSCb/DQSDb. (that is, positive coupling).

When a write operation of the memory ends, that is, when the data clock enable signal DQS_EN changes to a low level, the corresponding reset signal RSTb also changes to a low level, and the data clock signal DQSCb or DQSDb welcomes a rising edge. Therefore, decoupling enables The enable signal DECOUPLE_EN also changes to high level, that is, when the write operation is completed, the decoupling operation ends and is reset in the next write operation.

According to this embodiment, the decoupling enable signal DECOUPLE_EN is used to eliminate the noise generated by coupling on the reference voltage VREFDQ, so as to ensure that its level is not affected by the coupling noise, thereby improving the comparison accuracy of the comparator and improving the performance of the memory.

The present invention has been described in detail, but the above-described embodiments are merely examples of all the embodiments, and the present invention is not limited thereto. In the present invention, the respective embodiments can be freely combined within the scope of the present invention, or any constituent elements of the respective embodiments can be modified, or any constituent elements of the respective embodiments can be omitted.

Industrial applicability

The memory with calibration function of the present invention can be applied to SRAM including SDR SRAM, DDR SRAM, QDR SRAM, ZBT SRAM; DRAM including SDRAM, DDR DRAM, RDRAM; ROM and other types of memories.

Claims (8)

1. a memory, can remove the noise that produces because of coupling when carrying out writing operation, it is characterized in that, comprise: an input receiving unit, the input receiving unit is provided with an interface for converting serial input into parallel output, and a first comparator, a second comparator, a third comparator, and a fourth comparator connected in parallel to the interface, The clock signal input terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator respectively input the divided first data clock signal, the second data clock signal, and the third Three data clock signals and a fourth data clock signal, respectively input reference voltage signals to the reference voltage input terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator, A data signal is input to the data signal input terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator, respectively, and the reference voltage signal and the data signal are processed. Compare and output the comparison result; a control unit that generates a control signal based on the respective comparison results of the first comparator, the second comparator, the third comparator, and the fourth comparator; and a storage unit that stores at least a data signal compared and gated by the first comparator, the second comparator, the third comparator, and the fourth comparator, and the first comparison the comparison results of the comparator, the second comparator, the third comparator, and the fourth comparator, The phases of the first data clock signal, the second data clock signal, the third data clock signal, and the fourth data clock signal differ by 90° respectively, and the first data clock signal falls The edge corresponds to the first rising edge of the third data clock signal, the first falling edge of the second data clock signal corresponds to the first rising edge of the fourth data clock signal, Decoupling capacitors are respectively connected to the reference voltage input terminals of the third comparator and the fourth comparator, and the third data clock signal or the fourth data is respectively applied to the decoupling capacitors The decoupling enable signal corresponding to the clock signal. 2. The memory of claim 1, wherein The decoupling enable signal applied to the decoupling capacitor of the third comparator is triggered at the first falling edge of the third data clock signal, thereby eliminating the first falling edge of the third data clock signal. A falling edge generates coupled noise on the reference voltage signal, The decoupling enable signal applied to the decoupling capacitor of the fourth comparator is triggered at the first falling edge of the fourth data clock signal, thereby eliminating the first falling edge of the fourth data clock signal. A falling edge generates coupled noise on the reference voltage signal. 3. The memory of claim 2, wherein The decoupling enable signal of the third comparator becomes a low level at the moment of the first falling edge of the third data clock signal, The decoupling enable signal of the fourth comparator changes to a low level at the moment of the first falling edge of the fourth data clock signal. 4. The memory of claim 3, wherein The decoupling enable signal of the third comparator and the decoupling enable signal of the fourth comparator are reset to a high level when a write operation of the memory is completed. 5. The memory of claim 1, wherein The decoupling enable signal of the third comparator and the decoupling enable signal of the fourth comparator are generated according to a global reset signal and a write operation enable signal of the memory. 6. The memory of claim 1, wherein After the first falling edge of the first data clock signal, each signal edge of the first data clock signal is inverted with each signal edge of the third data clock signal, After the first falling edge of the second data clock signal, each signal edge of the second data clock signal is inverted with each signal edge of the fourth data clock signal. 7. The memory of any one of claims 1 to 6, wherein The memory is DDR (Double Rate Synchronous Dynamic Random Access Memory). 8. A decoupling method capable of removing the noise generated by the coupling during the write operation of the memory, characterized in that, The memory includes: an input receiving unit, the input receiving unit is provided with an interface for converting serial input into parallel output, and a first comparator, a second comparator, a third comparator, and a fourth comparator connected in parallel to the interface, The clock signal input terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator respectively input the divided first data clock signal, the second data clock signal, and the third Three data clock signals and a fourth data clock signal, respectively input reference voltage signals to the reference voltage input terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator, Data signals are input to the data signal input terminals of the first comparator, the second comparator, the third comparator, and the fourth comparator, respectively, and the reference voltage signal and the data signal are processed. Compare and output the comparison result; a control unit that generates a control signal based on the respective comparison results of the first comparator, the second comparator, the third comparator, and the fourth comparator; and a storage unit that stores at least a data signal compared and gated by the first comparator, the second comparator, the third comparator, and the fourth comparator, and the first comparison the comparison results of the comparator, the second comparator, the third comparator, and the fourth comparator, The phases of the first data clock signal, the second data clock signal, the third data clock signal, and the fourth data clock signal differ by 90° respectively, and the first data clock signal falls The edge corresponds to the first rising edge of the third data clock signal, the first falling edge of the second data clock signal corresponds to the first rising edge of the fourth data clock signal, Decoupling capacitors are respectively connected to the reference voltage input terminals of the third comparator and the fourth comparator, and the third data clock signal or the fourth data is respectively applied to the decoupling capacitors The decoupling enable signal corresponding to the clock signal.

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