CN115084179B

CN115084179B - A low dark current image sensor pixel structure

Info

Publication number: CN115084179B
Application number: CN202210756089.9A
Authority: CN
Inventors: 王菁; 陈多金; 龚雨琛; 高峰
Original assignee: Will Semiconductor Ltd
Current assignee: Will Semiconductor Ltd
Priority date: 2022-06-30
Filing date: 2022-06-30
Publication date: 2025-06-27
Anticipated expiration: 2042-06-30
Also published as: CN115084179A

Abstract

The present invention discloses a low dark current image sensor pixel structure, including a photodiode, a transfer transistor, a floating diffusion node, a reset transistor, a source follower transistor, a row selection transistor, a power supply and a pixel output placed in a semiconductor substrate; a reverse PN junction isolation 301 is used between adjacent photodiodes, and a trapezoidal shallow groove isolation 205 is added between the photodiodes, so that the stress is concentrated in the four corners of the photodiode to form an obtuse angle structure. The stress on the photodiode is reduced by optimizing the pixel layout design, and in the pixel process, a low stress silicon nitride film is used to replace the high stress silicon nitride film and the thickness of the silicon nitride film is reduced. The dislocation defects caused by the high stress on the active area of the photodiode are reduced, thereby reducing the dark current generated by the pixel and improving the performance of the image sensor.

Description

Low dark current image sensor pixel structure

Technical Field

The present invention relates to a CMOS image sensor, and more particularly, to a pixel structure of a low dark current image sensor.

Background

CMOS image sensors are used in a large number of portable digital cameras, cell phones, smart cars, security and medical fields. Many of these applications require advanced performance such as wide dynamic range, high speed and high sensitivity.

As shown in fig. 1, the image sensor pixel is composed of a Photodiode (PD), a transfer Transistor (TX), a floating diffusion node (FD), a RESET transistor (RESET), a source follower transistor (SF), a row strobe transistor (SELECT), a power supply (VDD), and a pixel output (VOUT) in a semiconductor substrate. The photodiodes and the transistors need to adopt STI (Shallow Trench Isolation) isolation structures or reverse PN junction isolation structures so as to reduce leakage current and crosstalk (Cross talk) between the device circuits.

When using STI (Shallow Trench Isolation) isolation structures to isolate adjacent photodiodes, silicon is damaged during the STI trench etching process, resulting in higher dark current generated by the formed defects, and reducing the dynamic range of the image sensor.

Using the portion STI (Partial Shallow Trench Isolation), the reverse PN junction isolation structure between adjacent photodiodes can reduce the STI trench etched area. But portions of the STI isolation structures may form high stress regions between the photodiode and other transistors.

As shown in fig. 5, when lattice defects caused by ion implantation or by the self-doping of silicon exist in the high-stress region, dislocation defects are formed, and more dislocation defects are formed in the continuous high-stress region, so that a higher dark current is generated, and the dynamic range of the image sensor is reduced.

In view of this, the present invention has been made.

Disclosure of Invention

The invention aims to provide a pixel structure of a low dark current image sensor, which solves the technical problems in the prior art.

The invention aims at realizing the following technical scheme:

The low dark current image sensor pixel structure of the present invention includes a photodiode 101, a transfer transistor 102, a floating diffusion node 103, a reset transistor 104, a source follower transistor 106, a row strobe transistor 107, a power supply 105, and a pixel output 108 disposed in a semiconductor body;

The photodiodes are plural, reverse PN junction isolation 301 is adopted between adjacent photodiodes, and trapezoid shallow trench isolation 205 is added between the photodiodes, so that stress is concentrated in the four corners of the photodiodes to form an obtuse angle structure.

Compared with the prior art, the low dark current image sensor pixel structure provided by the invention reduces the stress around the photodiode and reduces dislocation defects of the photodiode by reducing the stress generated by STI etching.

Drawings

FIG. 1 is a circuit diagram of a CMOS image sensor 4-pipe active pixel (4T-APS)

101 Photodiode (PD)

102 Transmission gate Transistor (TX)

103 Floating diffusion node (FD)

104 RESET transistor (RESET)

105 Power supply (VDD)

106 Source follower transistor (SF)

107 Row strobe transistor (SEL)

108 Pixel output (Vout)

FIG. 2 is a diagram showing a stress distribution of a shallow trench isolation photodiode

201 Photodiode 1 (PD 1)

202 Photodiode 2 (PD 2)

203 Photodiode 3 (PD 3)

204 Photodiode 4 (PD 4)

205 Shallow Trench Isolation (STI)

206 High stress region

FIG. 3 is a stress distribution diagram of a reverse PN junction isolated photodiode

201 Photodiode 1 (PD 1)

202 Photodiode 2 (PD 2)

203 Photodiode 3 (PD 3)

204 Photodiode 4 (PD 4)

206 High stress region

301 Reverse PN junction isolation

FIG. 4 is a graph showing the stress distribution of the photodiode according to the present embodiment

201 Photodiode 1 (PD 1)

202 Photodiode 2 (PD 2)

203 Photodiode 3 (PD 3)

204 Photodiode 4 (PD 4)

206 High stress region

301 Reverse PN junction isolation

FIG. 5 is a schematic view of dislocation defects, (a) continuous high stress regions, (b) discontinuous high stress regions;

206 high stress region

501 Silicon substrate

502 Lattice defects

503 Low stress region

504 Dislocation defects (Dislocation defect)

FIG. 6 is a schematic diagram of a shallow trench isolation etching mask layer (a) of a conventional process and (b) of a process according to the present embodiment;

501 silicon substrate

601. Buffer Oxide layer (Oxide)

602 High stress hard mask layer (HIGH STRESS HARD MASK)

603 Buffer polysilicon layer (Poly Silicon)

604 A Low stress hard mask layer (Low STRESS HARD MASK);

FIG. 7 is a schematic diagram of a conventional process shallow trench isolation etching section, (a) a shallow trench isolation etching section of the present embodiment;

205 Shallow Trench Isolation (STI);

501 silicon substrate

601. Buffer Oxide layer (Oxide)

602 High stress hard mask layer (HIGH STRESS HARD MASK)

603 Buffer polysilicon layer (Poly Silicon)

604 Low stress hard mask layer (Low STRESS HARD MASK)

Detailed Description

The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments of the present invention, and this is not limiting to the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.

The terms that may be used herein will first be described as follows:

The term "and/or" is intended to mean that either or both may be implemented, e.g., X and/or Y are intended to include both the cases of "X" or "Y" and the cases of "X and Y".

The terms "comprises," "comprising," "includes," "including," "has," "having" or other similar referents are to be construed to cover a non-exclusive inclusion. For example, inclusion of a feature (e.g., a starting material, component, ingredient, carrier, dosage form, material, size, part, component, mechanism, apparatus, step, procedure, method, reaction condition, processing condition, parameter, algorithm, signal, data, product or article of manufacture, etc.) should be construed as including not only the feature explicitly recited, but also other features known in the art that are not explicitly recited.

The term "consisting of" means excluding any technical feature elements not explicitly listed. If such term is used in a claim, the term will cause the claim to be closed, such that it does not include technical features other than those specifically listed, except for conventional impurities associated therewith. If the term is intended to appear in only a clause of a claim, it is intended to limit only the elements explicitly recited in that clause, and the elements recited in other clauses are not excluded from the overall claim.

Unless specifically stated or limited otherwise, the terms "mounted," "connected," "secured" and the like should be construed broadly, as they are used in a fixed, removable or integral manner, as they are used in a mechanical or electrical connection, as they are used in a direct or indirect connection via an intervening medium, as they are used in a communication between two elements. The specific meaning of the terms herein above will be understood by those of ordinary skill in the art as the case may be.

The terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," etc. refer to an orientation or positional relationship based on that shown in the drawings, merely for ease of description and to simplify the description, and do not explicitly or implicitly indicate that the apparatus or element in question must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present disclosure.

What is not described in detail in the embodiments of the present invention belongs to the prior art known to those skilled in the art. The specific conditions are not noted in the examples of the present invention and are carried out according to the conditions conventional in the art or suggested by the manufacturer. The reagents or apparatus used in the examples of the present invention were conventional products commercially available without the manufacturer's knowledge.

In the isolation structure between adjacent photodiodes, reverse PN junction isolation 301 is adopted in the middle, trapezoidal shallow trench isolation 205 is adopted at two ends, and the trapezoidal shallow trench isolation 205 at two ends enables four corners of the photodiodes to form an obtuse angle structure.

A hard mask layer process is used in the shallow trench isolation etching process, and the hard mask layer is a silicon nitride film deposited by chemical vapor deposition and comprises a buffer oxide layer 601, a buffer polysilicon layer 603 and a low-stress hard mask layer 604 which are sequentially covered on a silicon substrate 501.

In the deposition process of the low-stress hard mask layer 604, the ratio of DSC to NH ₃ is adjusted to be 5 to 1 by adjusting the ratio of the reaction gases, so as to obtain the low-stress silicon nitride film, wherein the stress is 200MPa.

The thickness of the buffer oxide layer 601 is 11nm, the thickness of the buffer polysilicon layer 603 is 50nm, and the thickness of the low stress hard mask layer 604 is 75nm.

In summary, the low dark current image sensor pixel structure of the embodiment of the invention reduces the stress around the photodiode and reduces dislocation defects of the photodiode by reducing the stress generated by STI etching.

In order to more clearly demonstrate the technical scheme and the technical effects provided by the invention, the following detailed description of the embodiments of the invention is given by way of specific examples.

Example 1

The invention relates to a low dark current pixel structure design and a preparation method thereof, as shown in fig. 1:

The pixel structure includes at least a Photodiode (PD), a transfer Transistor (TX), a floating diffusion node (FD), a RESET transistor (RESET), a source follower transistor (SF), a row strobe transistor (SELECT), a power supply (VDD), and a pixel output (VOUT) disposed in a semiconductor body. In the embodiment, the stress on the Photodiode (PD) is reduced by optimizing the pixel layout design and using a low-stress silicon nitride (SiN) film to replace a high-stress silicon nitride film and reducing the thickness of the silicon nitride film in the pixel process. Dislocation defects (Dislocation Defect) caused by high stress on an active region (ACTIVE AREA) of the photodiode are reduced, so that dark current generated by pixels is reduced, and the performance of the image sensor is improved.

As shown in fig. 2, the use of shallow trench isolation adjacent photodiodes forms high stress regions only at four corners, but the shallow trench isolation in the middle of the photodiode is damaged during etching, and defects are formed to cause the pixel circuit to generate high dark current.

As shown in fig. 3, the use of reverse PN junctions to isolate adjacent photodiodes avoids damage during the shallow trench isolation etch, but forms a continuous high stress region around the photodiodes, which is more prone to dislocation defects after ion implantation and high temperature annealing, resulting in higher dark current in the pixel circuit.

As shown in fig. 4, the reverse PN junction is still used to isolate adjacent photodiodes, so as to avoid damage caused by shallow trench isolation etching. And a trapezoid shallow slot is added in the middle of the photodiode, so that stress is concentrated in four corners of the photodiode to form an obtuse angle structure, the formation of continuous high-stress areas is avoided, the formation of dislocation defects is reduced, and dark current generated by a pixel circuit is reduced.

As shown in fig. 6 and 7, a hard mask layer process is used during the shallow trench isolation etch. The hard mask layer is a silicon nitride film deposited by chemical vapor deposition, and in the traditional process, the ratio of DSC (dichlorosilane) and NH3 of the reaction gas for generating the silicon nitride film is 1 to 4, and the stress is about 1200MPa. In this example, the ratio of DSC (dichlorosilane) to NH3 was changed to 5 to 1 by adjusting the ratio of the reaction gases, to obtain a low stress silicon nitride film having a stress of about 200MPa.

Because silicon nitride (SiN) has a large lattice difference from a silicon substrate, a large stress is formed on the silicon nitride and silicon surfaces. An 11nm buffer oxide layer is typically grown between the silicon nitride and the silicon substrate to reduce the stress to which the silicon substrate is subjected. But the buffer oxide layer is insufficient to counteract the stress imparted by the hard mask layer and the stress increases with increasing hard mask layer thickness. In this embodiment, the thickness of silicon nitride is reduced to 75nm to reduce the generation of stress. But in order to avoid that the shallow trench isolation changes in height after filling the oxide, which leads to a change in the electrical properties of the individual transistors. In this embodiment, 50nm polysilicon is grown on the 11nm buffer oxide layer and 75nm low stress silicon nitride is deposited. The thickness of the hard mask layer is reduced under the condition that the thickness of the whole mask layer is not changed, the stress born by the photodiode is reduced, dislocation defects are reduced, and dark current generated by a pixel circuit is reduced.

The foregoing is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims. The information disclosed in the background section herein is only for enhancement of understanding of the general background of the invention and is not to be taken as an admission or any form of suggestion that this information forms the prior art already known to those of ordinary skill in the art.

Claims

1. A low dark current image sensor pixel structure comprising a photodiode (101), a transfer transistor (102), a floating diffusion node (103), a reset transistor (104), a source follower transistor (106), a row strobe transistor (107), a power supply (105) and a pixel output (108) disposed in a semiconductor body;

The number of the photodiodes (101) is multiple, reverse PN junction isolation (301) is adopted between adjacent photodiodes, and trapezoid shallow slot isolation (205) is added between the photodiodes, so that stress is concentrated in the four corners of the photodiodes to form an obtuse angle structure;

In the isolation structure between adjacent photodiodes, reverse PN junction isolation (301) is adopted in the middle, trapezoid shallow trench isolation (205) is adopted at two ends, and the trapezoid shallow trench isolation (205) at two ends enables four corners of the photodiodes to form an obtuse angle structure.

2. The low dark current image sensor pixel structure according to claim 1, wherein a hard mask layer process is used during shallow trench isolation etching, the hard mask layer is a chemical vapor deposited silicon nitride film comprising a buffer oxide layer (601), a buffer polysilicon layer (603) and a low stress hard mask layer (604) sequentially overlying a silicon substrate (501).

3. The low dark current image sensor pixel structure of claim 2, wherein the low stress silicon nitride film is obtained by adjusting the ratio of DSC to NH ₃ to 1 by adjusting the ratio of the reactive gases during the deposition of the low stress hard mask layer (604), the stress of the low stress silicon nitride film being 200MPa.

4. A low dark current image sensor pixel structure according to claim 3, wherein the thickness of the buffer oxide layer (601) is 11nm, the thickness of the buffer polysilicon layer (603) is 50nm, and the thickness of the low stress hard mask layer (604) is 75nm.