CN115080183A - VGPU acceleration method, equipment and storage medium - Google Patents

Abstract

Embodiments of the present application provide a VGPU acceleration method, device, and storage medium. A customized microprocessor can be introduced into the host, and the microprocessor can be configured with the same MMIO address space as the VGPU and mapped to each other. Based on this, when an MMIO request for VGPU occurs, the microprocessor will sense and take over the MMIO request, and the original virtual machine monitor will no longer sense and take over the MMIO request. The virtual machine is controlled to enter the exit mode by requesting, that is, the virtual machine exit problem will no longer occur during the processing of the MMIO request, which can avoid the performance impact of the virtual machine exit problem on the VGPU. The microprocessor can replace the virtual machine monitor to accurately calculate the address offset corresponding to the MMIO request, so that the original hardware simulation can be normally performed based on the address offset to respond to the MMIO request. The time-consuming of the machine exit problem is greatly reduced, which can effectively improve the performance of the VGPU.

Description

A VGPU acceleration method, device and storage medium

technical field

The present application relates to the field of virtual technology, and in particular, to a VGPU acceleration method, device and storage medium.

Background technique

In the field of cloud computing, GPU (Graphics Processing Unit, image processing unit) plays an increasingly important role in rendering, AI training and reasoning, big data, encoding and decoding and other fields. VGPU (virtual GPU, virtual GPU) technology came into being. VGPU technology can virtualize a physical GPU into multiple VGPUs, and realize the function of multiple virtual machines using one physical GPU at the same time.

However, at present, VGPU needs to trigger a large number of MMIO (Memory mapping I/O, memory mapping I/O) traps to simulate hardware behavior, which leads to frequent occurrence of VM Exit events in the virtual machine VM where the VGPU is located, which seriously affects the performance of the VGPU.

SUMMARY OF THE INVENTION

Various aspects of the present application provide a VGPU acceleration method, device and storage medium to improve the performance of the VGPU.

An embodiment of the present application provides a VGPU acceleration method. The host where the VGPU is located is equipped with a customized microprocessor, and the microprocessor is configured with an MMIO address space that has the same specifications as the VGPU and is mapped to each other. Methods include:

Based on the MMIO address space mapping relationship between the microprocessor and the VGPU, utilize the microprocessor to perceive the MMIO request for the VGPU, where the MMIO request includes the required target MMIO address;

Using the microprocessor to calculate the address offset corresponding to the MMIO request according to the mapping position of the target MMIO address in its MMIO address space;

calling the physical GPU resource pointed to by the address offset in response to the MMIO request;

After the response is completed, the VGPU is notified by the microprocessor, so that the VGPU continues to work.

The embodiment of the present application also provides a VGPU acceleration method, which is suitable for a customized microprocessor installed on a host computer, where the microprocessor is configured with an MMIO address space of the same specification as the VGPU and mapped to each other, the method include:

Based on the MMIO address space mapping relationship between the microprocessor and the VGPU, perceive the MMIO request for the VGPU, where the MMIO request includes the required target MMIO address;

Calculate the address offset corresponding to the MMIO request according to the mapping position of the target MMIO address in the MMIO address space of the microprocessor;

providing the address offset to the GPU driver in the host, for the GPU driver to call the physical GPU resource pointed to by the address offset in response to the MMIO request;

After the response is completed, the VGPU is notified so that the VGPU can continue to work.

The embodiment of the present application also provides a computing device, as a host, on which a customized microprocessor is equipped and a VGPU is created, the microprocessor is configured with an MMIO address space of the same specification as the VGPU and mapped to each other, the computing device includes a memory, a processor, and a communication component;

the memory for storing one or more computer instructions;

The processor is coupled to the memory and the communication component for executing the one or more computer instructions for:

Based on the MMIO address space mapping relationship between the microprocessor and the VGPU, utilize the microprocessor to perceive the MMIO request for the VGPU, where the MMIO request includes the required target MMIO address;

Using the microprocessor to calculate the address offset corresponding to the MMIO request according to the mapping position of the target MMIO address in its MMIO address space;

calling the physical GPU resource pointed to by the address offset in response to the MMIO request;

After the response is completed, the VGPU is notified by the microprocessor, so that the VGPU continues to work.

An embodiment of the present application further provides a microprocessor, which is assembled on a host computer, the microprocessor is configured with an MMIO address space of the same specification as the VGPU created on the host computer and is mapped to each other, and the microprocessor includes memory, processors and communication components;

the memory for storing one or more computer instructions;

The processor is coupled to the memory and the communication component for executing the one or more computer instructions for:

Based on the MMIO address space mapping relationship between the microprocessor and the VGPU, perceive the MMIO request for the VGPU, where the MMIO request includes the required target MMIO address;

Calculate the address offset corresponding to the MMIO request according to the mapping position of the target MMIO address in the MMIO address space of the microprocessor;

providing the address offset to the GPU driver in the host, for the GPU driver to call the physical GPU resource pointed to by the address offset in response to the MMIO request;

After the response is completed, the VGPU is notified so that the VGPU can continue to work.

Embodiments of the present application further provide a computer-readable storage medium storing computer instructions, and when the computer instructions are executed by one or more processors, cause the one or more processors to execute the aforementioned VGPU acceleration method.

In this embodiment of the present application, a customized microprocessor may be introduced into the host, and the microprocessor is configured with an MMIO address space of the same specification as the VGPU and mapped to each other. Based on this, when an MMIO request for VGPU occurs, the microprocessor will sense and take over the MMIO request, and the original virtual machine monitor will no longer sense and take over the MMIO request. The virtual machine is controlled to enter the exit mode by requesting, that is, the virtual machine exit problem will no longer occur during the processing of the MMIO request, which can avoid the performance impact of the virtual machine exit problem on the VGPU. The microprocessor can replace the virtual machine monitor to accurately calculate the address offset corresponding to the MMIO request, so that the original hardware simulation can be normally performed based on the address offset to respond to the MMIO request. The time-consuming of the machine exit problem is greatly reduced, which can effectively improve the performance of the VGPU.

Description of drawings

The drawings described herein are used to provide further understanding of the present application and constitute a part of the present application. The schematic embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation of the present application. In the attached image:

1 is a schematic flowchart of a VGPU acceleration method provided by an exemplary embodiment of the present application;

2 is a schematic logical diagram of a VGPU acceleration solution provided by an exemplary embodiment of the present application;

3 is a schematic diagram of a VGPU implementation logic under a traditional solution provided by an exemplary embodiment of the present application;

FIG. 4 is a schematic diagram of the implementation logic of VGPU under the acceleration scheme provided by an exemplary embodiment of the present application;

5 is a schematic flowchart of another VGPU acceleration method provided by an exemplary embodiment of the present application;

FIG. 6 is a schematic structural diagram of a microprocessor according to another exemplary embodiment of the present application.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be clearly and completely described below with reference to the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

At present, MMIO requests for VGPU often cause virtual machine exit problems, which seriously affects the performance of VGPU. To this end, in some embodiments of the present application, a customized microprocessor may be introduced into the host, and an MMIO address space that has the same specifications as the VGPU and is mapped to each other is configured for the microprocessor. Based on this, when an MMIO request for VGPU occurs, the microprocessor will sense and take over the MMIO request, and the original virtual machine monitor will no longer sense and take over the MMIO request. The virtual machine is controlled to enter the exit mode by requesting, that is, the virtual machine exit problem will no longer occur during the processing of the MMIO request, which can avoid the performance impact of the virtual machine exit problem on the VGPU. The microprocessor can replace the virtual machine monitor to accurately calculate the address offset corresponding to the MMIO request, so that the original hardware simulation can be normally performed based on the address offset to respond to the MMIO request. The time-consuming of the machine exit problem is greatly reduced, which can effectively improve the performance of the VGPU.

Before describing the technical solutions provided by the various embodiments of this application, the technical terms that may be involved in this application are briefly explained, as follows:

GPU: Graphics Processing Unit, an image processing unit, is a physical resource on the host.

VM: Virtual Machine, a virtual machine, is a computer simulated by software on a host machine, and multiple virtual machines can be simulated on one host machine.

VGPU is a virtual GPU (virtual GPU) virtualized by VGPU technology. VGPU technology can virtualize a physical GPU on the host into multiple virtual GPUs, enabling multiple virtual machines on the host to use a physical GPU at the same time. capabilities of the GPU. Among them, each virtual machine can be equipped with one VGPU.

Virtual monitor, virtual machine monitor, abbreviated as VMM, is the software, firmware or hardware used to create and execute virtual machines. Virtual monitor is sometimes translated as: Hypervisor.

MMIO: Memory mapping I/O, that is, memory mapped I/O, which is part of the PCI specification, I/O devices are placed in memory space instead of I/O space. From the processor's point of view, system devices are accessed like memory after memory-mapped I/O. In this way, the frame buffer, BIOS, and PCI devices on the AGP/PCI-E graphics card can be accessed using the same assembly instructions as reading and writing memory, which simplifies the difficulty of programming and the complexity of the interface.

MMIO TRAP: MMIO trap. In the VM, in order to simulate the behavior of the hardware, the VMM needs to take over the MMIO request through the trap trap, and control the VM to fall into the ROOT mode from the NON-ROOT mode, thereby completing the hardware simulation. MMIOTRAP will cause VM Exit issues.

A microprocessor is a physical piece of hardware that provides an off-the-shelf component with a wide variety of logic capabilities, characteristics, speed, and voltage characteristics, within which the processing logic can be programmed.

The technical solutions provided by the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a schematic flowchart of a VGPU acceleration method provided by an exemplary embodiment of the present application, and FIG. 2 is a logical schematic diagram of a VGPU acceleration solution provided by an exemplary embodiment of the present application.

Referring to Figure 2, the host computer may be equipped with a GPU and a custom microprocessor. The microprocessor may use programmable devices such as a programmable array logic device FPGA or a complex programmable logic device CPLD, which is not limited in this embodiment. Multiple virtual machine VMs can be created on the host, and the GPU can be virtualized to create multiple VGPUs. In this embodiment, the VMs on the host can be matched with VGPUs. The workflow of each VGPU is similar. For the convenience of description, the technical solution will be described from the perspective of a single VGPU in this embodiment, but it should be understood that the acceleration solution provided in this embodiment can be applied to the host computer. Any one of the VGPU for acceleration. In addition, in this embodiment, as with sharing the same GPU, multiple VGPUs can share the same microprocessor. Of course, this embodiment is not limited to this. In the case where the number of VGPUs is limited, independent VGPU allocation can also be provided. microprocessor.

After the microprocessor is introduced, in this embodiment, the microprocessor can be configured with an MMIO address space of the same specification as the VGPU and mapped to each other. Among them, the VGPU-based MMIO address space can map the physical GPU resources that can be used by the VGPU to the memory space, and similarly, the microprocessor-based MMIO address space can map the programmable space to the memory space. Optionally, in this embodiment, extended page table EPT (Extended Page Table), nested page table NPT (Nested page table) or similar technologies may be used to map the MMIO address space of the VGPU to the MMIO address space of the microprocessor in advance . EPT, NPT, etc. are page table virtualization hardware support technologies in CPU virtualization, and the detailed logic of these technologies will not be repeated here. It should be understood that in this embodiment, other mapping manners may also be used to establish a perceptual relationship between the hardware microprocessor and the virtual VGPU, and to establish a mapping relationship from the address dimension. It should be emphasized here that the specification of the MMIO address space of the programmable hardware must be consistent with the specification of the MMIO address space of the VGPU to ensure that the microprocessor can correctly perceive the address information in the MMIO request.

In addition, it should be noted that, as mentioned above, there may be a situation where multiple VGPUs share the same microprocessor. For this, in this embodiment, multiple independent MMIO address spaces can be configured for the microprocessor to Serve different VGPUs.

On this basis, with reference to FIG. 1 , the VGPU acceleration method provided in this embodiment may include:

Step 100, based on the MMIO address space mapping relationship between the microprocessor and the VGPU, utilize the microprocessor to perceive the MMIO request for the VGPU, and the MMIO request includes the required target MMIO address;

Step 101, utilize the microprocessor to calculate the address offset corresponding to the MMIO request according to the mapping position of the target MMIO address in its MMIO address space;

Step 102, calling the physical GPU resource pointed to by the address offset to respond to the MMIO request;

Step 103: After the response is completed, use the microprocessor to notify the VGPU, so that the VGPU continues to work.

It should be understood that, in this embodiment, since the MMIO address space of the VGPU is mapped to the MMIO address space corresponding to the microprocessor on the virtual machine, this will naturally cause the VGPU to no longer need to generate TRAP, but will be processed by the microprocessor. perceived by the device. The microprocessor can sense the MMIO request for the VGPU through the bus.

In practical applications, when an image processing task that requires physical GPU resources occurs in the VM, the VGPU driver in the VM can access the MMIO address space of the VGPU to initiate an MMIO request for the VGPU, and set the required value in the MMIO request. Target MMIO address. It should be understood that the MMIO address can be regarded as a kind of identification, and more specifically, it can be regarded as an identification defined for a certain physical GPU resource. In this way, specifying the target MMIO address in the MMIO request is essentially specifying the required call. However, since the host manages the physical GPU resources on it according to the host's physical address space, it is also necessary to convert the target MMIO address in the MMIO request to the host's physical address to really find the required physical GPU resources.

To this end, in step 101, the microprocessor may calculate the address offset corresponding to the MMIO request according to the mapping position of the target MMIO address in its MMIO address space.

As mentioned above, in this embodiment, the specifications of the MMIO address space of the microprocessor and the MMIO address space of the VGPU are consistent with each other, and they are mapped to each other. Therefore, after sensing the target MMIO address in the MMIO request, the microprocessor can The mapping position of the target MMIO address in the MMIO address space of the microprocessor is determined according to the mapping relationship, thereby calculating the address offset corresponding to the MMIO request. For example, if the MMIO address space of the VGPU is 4000-5000, and the target MMIO address specified in the MMIO request is 4100, then based on the mapping relationship, the microprocessor can determine that the target MMIO address 4100 is in the microprocessor's MMIO address space 6000-7000 The mapping position in is address 6100, so the offset between the calculated mapping position and the starting address 6000 of the MMIO address space of the microprocessor is 100, which is used as the address offset corresponding to the MMIO request.

In practical applications, in step 101, when the microprocessor senses the MMIO request, it can calculate the offset between the mapping position and the start address of the MMIO address space of the microprocessor as the address offset. Among them, the microprocessor driver can work in the kernel space of the host, and is used to drive the microprocessor to run.

It should be understood that, in this embodiment, the core work of the microprocessor is to calculate the address offset corresponding to the MMIO request, and the address offset can support the normal execution without the intervention of the virtual machine monitor. The original hardware emulation works. For this reason, in this embodiment, the MMIO address space of the microprocessor does not need to be associated with the physical GPU resources that can be used by the VGPU. This is mainly because the microprocessor in this embodiment is mainly used to undertake the address mapping function. The specific hardware simulation operation can still be dominated by the GPU driver on the host computer, which can avoid the problem of heavy workload of the microprocessor and ensure the lightweight of the microprocessor.

Referring to FIG. 1 and FIG. 2, in step 102, the physical GPU resource pointed to by the address offset may be invoked in response to the MMIO request.

As mentioned above, the target MMIO address in the MMIO request needs to be converted into the host physical address to actually find the required physical GPU resources. In this embodiment, although programmable hardware is used to take over the MMIO request, it can be reserved The original mapping space of the VGPU's MMIO address space in the host's physical address space is used as the physical address space corresponding to the VGPU's MMIO address space. On this basis, in step 102, the microprocessor can be used to provide the address offset to the GPU driver on the host; the host GPU driver searches for the corresponding target physical address through the address offset; calls the target physical address The physical GPU resource pointed to in response to MMIO requests. The GPU driver in the host machine works in the kernel space of the host machine, and is used to drive the work of physical GPU resources on the host machine. Optionally, the VGPU control can be awakened by the GPU driver, and then the VGPU control can be used to find the target physical address.

Following the previous example, the MMIO address space of the VGPU is 4000-5000, and the address offset calculated by the microprocessor is 100. According to the original mapping space of the reserved VGPU MMIO address space in the physical address space of the host machine 2000-3000, then it is determined that the target physical address required by the MMIO request is 2100 in the physical address space of the host. In this way, the GPU driver can call the physical GPU resource at physical address 2100 in response to the MMIO request.

In this embodiment, in the process that the microprocessor calculates the address offset and the GPU driver calls the relevant physical GPU resources to respond to the MMIO request, the VGPU can remain in the waiting state, and no MMIO TRAP occurs, and no virtual machine exit occurs. Compared with the time-consuming caused by the virtual machine exit, the waiting process in this embodiment is very short. After the response processing to the MMIO request is completed, the VGPU can end the waiting and enter a normal working state.

Referring to FIG. 1 and FIG. 2 , in step 103 , after the response is completed, the microprocessor may be used to notify the VGPU, so that the VGPU continues to work.

In this embodiment, the microprocessor may use a bus to notify the VGPU driver that the response has been completed, so that the virtual machine continues to execute. Specifically, the microprocessor may provide notifications to the VGPU driver based on the TLP packets.

Accordingly, in this embodiment, a customized microprocessor can be introduced into the host, and an MMIO address space of the same specification as the VGPU and mapped to each other is configured for the microprocessor. Based on this, when an MMIO request for VGPU occurs, the microprocessor will sense and take over the MMIO request, and the original virtual machine monitor will no longer sense and take over the MMIO request. The virtual machine is controlled to enter the exit mode by requesting, that is, the virtual machine exit problem will no longer occur during the processing of the MMIO request, which can avoid the performance impact of the virtual machine exit problem on the VGPU. The microprocessor can replace the virtual machine monitor to accurately calculate the address offset corresponding to the MMIO request, so that the original hardware simulation can be normally performed based on the address offset to respond to the MMIO request. The time-consuming of the machine exit problem is greatly reduced, which can effectively improve the performance of the VGPU.

FIG. 3 is a schematic diagram of the implementation logic of VGPU under a conventional solution provided by an exemplary embodiment of the present application. FIG. 4 is a schematic diagram of the implementation logic of the VGPU under the acceleration solution provided by an exemplary embodiment of the present application. The technical advantages of the VGPU acceleration solution provided by this embodiment will be described below by comparing the VGPU implementation logic in FIG. 3 and FIG. 4 .

Referring to FIG. 3 and FIG. 4 , two virtual machines VM1 and VM2 are created on the host machine in the two sets of implementation logic, and the implementation logic is described by taking the VGPU created on VM1 as an example.

Referring to Figure 3, the VGPU implementation logic under the traditional solution may include:

1. The VGPU driver in VM1 accesses the MMIO address space of the VGPU and generates an MMIO request;

2. An MMIO TRAP occurs, the MMIO request is intercepted by the hypervisor, and the hypervisor controls the VM to enter Root mode to prevent the VM from accessing hardware resources on the host through MMIO request unauthorized access; VM Exit occurs at this time;

3. Convert the target MMIO address of the MMIO TRAP into an address offset (GPA offset) and pass it to the GPU driver in the host;

4. The host GPU driver wakes up the VGPU manager (VGPU control), converts the address offset into the target physical address, and calls the corresponding hardware GPU resources for software simulation to respond to MMIO requests;

5. The VGPU manager simulation is over, and the GPU driver is notified;

6. The GPU Host driver notifies the hypervisor that the simulation is over;

7. Hypervisor controls VM to return to Non-Root mode;

8. The VGPU driver in the VM continues to run.

It can be seen that in the VGPU implementation logic provided in Figure 3, the hypervisor takes over the MMIO request and controls the VM to switch between Root mode and Non-Root mode. During this process, the VM Exit problem occurs, which requires VM pays a very large performance price, which seriously affects the performance of VGPU.

Referring to Figure 4, the difference from Figure 3 is that a customized FPGA is introduced, and the MMIO address space of the same specification as the VGPU is configured for the FPGA. When the VM is started, the MMIO address space of the VGPU and the host physics are no longer configured. The mapping relationship between the address spaces is to map the MMIO address space of the VGPU to the MMIO address space of the FPGA through EPT, and the original mapping space of the MMIO address space of the VGPU in the physical address space of the host can be reserved.

Based on this, with reference to Figure 4, the VGPU implementation logic under the acceleration scheme may include:

1. The VGPU driver in VM1 accesses the MMIO address space of the VGPU and generates an MMIO request;

2. The FPGA can perceive the MMIO request and calculate the address offset corresponding to the MMIO request;

3. The FPGA driver transmits the address offset of MMIO to the GPU driver in the host through an interrupt;

4. The host GPU driver wakes up the VGPU manager (VGPU control), converts the address offset into the target physical address, and calls the corresponding hardware GPU resources for software simulation to respond to MMIO requests

5. The VGPU manager simulation is over, and the GPU driver is notified;

6. The GPU Host driver informs the FPGA driver that the simulation is over;

7. The FPGA driver updates the simulation results to the hardware FPGA so that it can be read by the VGPU driver. At the same time, if necessary, the host FPGA driver can inject interrupts into the VM through post interrupt;

8. The end of FPGA execution leads to the end of VGPU driving MMIO, and the VM continues to run.

Referring to FIG. 4 , in the VGPU acceleration solution provided in this embodiment, the virtual machine exit problem is completely avoided, and the time occupied by the FPGA to calculate the address offset is also very short, which effectively improves the performance of the VGPU.

It should be noted that, the execution subject of each step of the method provided by the above embodiments may be the same device, or the method may also be executed by different devices. In addition, in some of the processes described in the above embodiments and the accompanying drawings, multiple operations appearing in a specific order are included, but it should be clearly understood that these operations may be performed out of the order in which they appear in this document or performed in parallel , the sequence numbers of the operations, such as 101, 102, etc., are only used to distinguish different operations, and the sequence numbers themselves do not represent any execution order. Additionally, these flows may include more or fewer operations, and these operations may be performed sequentially or in parallel.

FIG. 5 is a schematic flowchart of another VGPU acceleration method provided by an exemplary embodiment of the present application. The VGPU acceleration method in the aforementioned FIG. 1 is mainly the acceleration logic described with the host as the execution body. Here, in FIG. 5 , the acceleration logic described with the microprocessor as the execution body. Referring to FIG. 5 , the method is applicable to a customized microprocessor installed on the host computer. The microprocessor is configured with the same specification as the VGPU and is mapped to each other with MMIO address spaces. The method may include:

500. Based on the MMIO address space mapping relationship between the microprocessor and the VGPU, perceive the MMIO request for the VGPU, and the MMIO request contains the required target MMIO address;

501. Calculate the address offset corresponding to the MMIO request according to the mapping position of the target MMIO address in the MMIO address space of the microprocessor;

502. Provide the address offset to the GPU driver in the host, so that the GPU driver can call the physical GPU resource pointed to by the address offset to respond to the MMIO request;

503. After the response is completed, notify the VGPU so that the VGPU continues to work.

In an optional embodiment, the extended page table EPT or NPT technology can be used to map the MMIO address space of the VGPU to the MMIO address space of the microprocessor in advance; and disconnect the MMIO address space of the VGPU from the physical address space of the host machine. The mapping relationship between the original mapping spaces in .

In an optional embodiment, according to the mapping position of the target MMIO address in its MMIO address space, the process of calculating the address offset corresponding to the MMIO request may include:

The offset between the mapping position and the starting address of the MMIO address space of the microprocessor is calculated by the microprocessor as an address offset.

In an optional embodiment, after the response is completed, the process of notifying the VGPU may include:

Use the microprocessor to notify the VGPU through the bus.

In an alternative embodiment, the microprocessor includes a programmable array logic device FPGA or a complex programmable logic device CPLD.

It is worth noting that, for the technical details in the above-mentioned embodiment of FIG. 5 , reference may be made to the relevant description of the microprocessor in the above-mentioned embodiment of FIG. 1 . loss of protection.

FIG. 5 is a schematic structural diagram of a computing device provided by another exemplary embodiment of the present application. The computing device can be used as the aforementioned host computer, and is equipped with a customized microprocessor 53 and created with a VGPU. The microprocessor 53 Configured with MMIO address spaces of the same specifications as the VGPU and mapped to each other, as shown in FIG. 5 , the computing device may include: a memory 50 , a processor 51 and a communication component 52 .

A processor 51, coupled to the memory 50 and the communication component 52, executes a computer program in the memory 50 for:

Based on the MMIO address space mapping relationship between the microprocessor and the VGPU, the microprocessor senses the MMIO request for the VGPU, and the MMIO request contains the required target MMIO address;

Use the microprocessor to calculate the address offset corresponding to the MMIO request according to the mapping position of the target MMIO address in its MMIO address space;

Call the physical GPU resource pointed to by the address offset in response to an MMIO request;

After the response is completed, the microprocessor is used to notify the VGPU, so that the VGPU continues to work.

In an optional embodiment, the processor 51 may also be used to:

Using the extended page table EPT or NPT technology, the MMIO address space of the VGPU is mapped to the MMIO address space of the microprocessor in advance;

Disconnect the mapping relationship between the VGPU's MMIO address space and its original mapping space in the host's physical address space.

In an optional embodiment, in the process of invoking the physical GPU resource pointed to by the address offset in response to the MMIO request, the processor 51 may be used to:

Use the microprocessor to provide the address offset to the GPU driver on the host;

Use the GPU driver to find the target physical address corresponding to the address offset in the physical address space corresponding to the MMIO address space of the VGPU;

Call the physical GPU resource pointed to by the target physical address in response to an MMIO request.

In an optional embodiment, the processor 51 may also be used to:

The original mapping space of the VGPU's MMIO address space in the host's physical address space is reserved as the physical address space corresponding to the VGPU's MMIO address space.

In an optional embodiment, the processor 51 utilizes the microprocessor to calculate the address offset corresponding to the MMIO request according to the mapping position of the target MMIO address in its MMIO address space, and can be used for:

Use the microprocessor to calculate the offset between the mapping position and the starting address of the MMIO address space of the microprocessor as the address offset.

In an optional embodiment, after the response is completed, the processor 51 may use the microprocessor to notify the VGPU in the process of:

Notify the VGPU through the bus.

In an alternative embodiment, the microprocessor includes a programmable array logic device FPGA or a complex programmable logic device CPLD.

Further, as shown in FIG. 5 , the computing device further includes: a GPU 54 , a display component 55 , a power supply component 56 and other components. Only some components are schematically shown in FIG. 5 , which does not mean that the computing device only includes the components shown in FIG. 5 .

It is worth noting that, for the technical details in the above-mentioned embodiments of the computing device, reference may be made to the relevant descriptions in the foregoing related method embodiments in FIG. loss of range.

FIG. 6 is a schematic structural diagram of a microprocessor provided by another exemplary embodiment of the present application, which is assembled on a host computer, and the microprocessor is configured with MMIO address spaces of the same specifications and mapped to each other as the VGPU created on the host computer. , the microprocessor may include: a memory 60 , a processor 61 and a communication component 62 .

Processor 61 is coupled to memory 60 and communication component 62 for executing one or more computer instructions for:

Based on the MMIO address space mapping relationship between the microprocessor and the VGPU, the MMIO request for the VGPU is perceived, and the MMIO request contains the required target MMIO address;

Calculate the address offset corresponding to the MMIO request according to the mapping position of the target MMIO address in the MMIO address space of the microprocessor;

Provide the address offset to the GPU driver in the host, so that the GPU driver can call the physical GPU resource pointed to by the address offset in response to the MMIO request;

After the response is complete, notify the VGPU so that the VGPU can continue to work.

In an optional embodiment, the extended page table EPT technology can be used to map the MMIO address space of the VGPU to the MMIO address space of the microprocessor in advance; and disconnect the MMIO address space of the VGPU from its connection in the host physical address space. The mapping relationship between the original mapping spaces.

In an optional embodiment, in the process of calculating the address offset corresponding to the MMIO request according to the mapping position of the target MMIO address in its MMIO address space, the processor 61 can be used to:

The offset between the mapping position and the starting address of the MMIO address space of the microprocessor is calculated by the microprocessor as an address offset.

In an optional embodiment, in the process of notifying the VGPU after the response is completed, the processor 61 may be used to:

Notify the VGPU through the bus.

In an alternative embodiment, the microprocessor includes a programmable array logic device FPGA or a complex programmable logic device CPLD.

Further, as shown in FIG. 6 , the microprocessor also includes: a power supply component 63 and other components. Only some components are schematically shown in FIG. 6 , which does not mean that the microprocessor only includes the components shown in FIG. 6 .

It is worth noting that, for the technical details of the above-mentioned embodiments of the microprocessor, reference may be made to the relevant description of the microprocessor in the foregoing related method embodiments of FIG. The loss of the protection scope of this application shall be caused.

Correspondingly, the embodiments of the present application further provide a computer-readable storage medium storing a computer program, and when the computer program is executed, each step that can be executed by a computing device/microprocessor in the foregoing method embodiments can be implemented.

The memories in FIGS. 5 and 6 described above are used to store computer programs and may be configured to store various other data to support operations on the computing platform. Examples of such data include instructions for any application or method operating on the computing platform, contact data, phonebook data, messages, pictures, videos, etc. Memory can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Read Only Memory (PROM), Read Only Memory (ROM), Magnetic Memory, Flash Memory, Magnetic or Optical Disk.

The above-mentioned communication components in FIGS. 5 and 6 are configured to facilitate wired or wireless communication between the device where the communication component is located and other devices. The device where the communication component is located can access a wireless network based on a communication standard, such as WiFi, a mobile communication network such as 2G, 3G, 4G/LTE, 5G, or a combination thereof. In one exemplary embodiment, the communication component receives broadcast signals or broadcast related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication assembly further includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

The above-mentioned display assembly in FIG. 5 includes a screen, and the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touch, swipe, and gestures on the touch panel. The touch sensor may not only sense the boundaries of a touch or swipe action, but also detect the duration and pressure associated with the touch or swipe action.

The power supply assemblies in Figures 5 and 6 above provide power for various components of the equipment in which the power supply assemblies are located. A power supply assembly may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the equipment in which the power supply assembly is located.

As will be appreciated by those skilled in the art, the embodiments of the present application may be provided as a method, a system, or a computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present application. It will be understood that each flow and/or block in the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to the processor of a general purpose computer, special purpose computer, embedded processor or other programmable data processing device to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing device produce Means for implementing the functions specified in a flow or flow of a flowchart and/or a block or blocks of a block diagram.

These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory result in an article of manufacture comprising instruction means, the instructions The apparatus implements the functions specified in the flow or flow of the flowcharts and/or the block or blocks of the block diagrams.

These computer program instructions can also be loaded on a computer or other programmable data processing device to cause a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process such that The instructions provide steps for implementing the functions specified in the flow or blocks of the flowcharts and/or the block or blocks of the block diagrams.

In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.

Memory may include non-persistent memory in computer readable media, random access memory (RAM) and/or non-volatile memory in the form of, for example, read only memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.

Computer-readable media includes both persistent and non-permanent, removable and non-removable media, and storage of information may be implemented by any method or technology. Information may be computer readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read only memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), Flash Memory or other memory technology, Compact Disc Read Only Memory (CD-ROM), Digital Versatile Disc (DVD) or other optical storage, Magnetic tape cartridges, tape-based disk storage or other magnetic storage devices or any other non-transmission medium that can be used to store information that can be accessed by a computing device. Computer-readable media, as defined herein, excludes transitory computer-readable media, such as modulated data signals and carrier waves.

It should also be noted that the terms "comprising", "comprising" or any other variation thereof are intended to encompass a non-exclusive inclusion such that a process, method, article or device comprising a series of elements includes not only those elements, but also Other elements not expressly listed, or which are inherent to such a process, method, article of manufacture, or apparatus are also included. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in the process, method, article of manufacture, or device that includes the element.

The above descriptions are merely examples of the present application, and are not intended to limit the present application. Various modifications and variations of this application are possible for those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included within the protection scope of this application.

Claims (13)

1. A VGPU acceleration method, the VGPU is equipped with a customized microprocessor on a host computer, the microprocessor is configured with MMIO address space which has the same specification with the VGPU and is mapped with each other, the method comprises the following steps:

sensing an MMIO request aiming at the VGPU by utilizing the microprocessor based on the MMIO address space mapping relation between the microprocessor and the VGPU, wherein the MMIO request comprises a required target MMIO address;

utilizing the microprocessor to calculate address offset corresponding to the MMIO request according to the mapping position of the target MMIO address in the MMIO address space;

calling the physical GPU resource pointed by the address offset to respond to the MMIO request;

and after the response is finished, informing the VGPU by the microprocessor so that the VGPU continues to work.

2. The method of claim 1, further comprising:

mapping the MMIO address space of the VGPU to the MMIO address space of the microprocessor in advance;

and disconnecting the mapping relation between the MMIO address space of the VGPU and the original mapping space of the VGPU in the physical address space of the host machine.

3. The method of claim 1, the invoking the physical GPU resource pointed to by the address offset to respond to the MMIO request, comprising:

providing, with the microprocessor, the address offset to a GPU driver on the host;

searching a target physical address corresponding to the address offset in a physical address space corresponding to the MMIO address space of the VGPU by using the GPU driver according to the address offset;

and calling the physical GPU resource pointed by the target physical address to respond to the MMIO request.

4. The method of claim 3, further comprising:

and reserving the original mapping space of the MMIO address space of the VGPU in the physical address space of the host machine, and using the mapping space as the physical address space corresponding to the MMIO address space of the VGPU.

5. The method of claim 1, wherein said calculating, by the microprocessor, an address offset corresponding to the MMIO request according to a mapping location of the target MMIO address in its MMIO address space comprises:

and calculating the offset between the mapping position and the initial address of the MMIO address space of the microprocessor by using the microprocessor as the address offset.

6. The method of claim 1, said notifying the VGPU with the microprocessor after the response is complete, comprising:

and informing the VGPU by the microprocessor through a bus.

7. The method of claim 1, the microprocessor comprising a programmable array logic (FPGA) or a Complex Programmable Logic Device (CPLD).

8. A VGPU acceleration method, which is applicable to a customized microprocessor assembled on a host machine, wherein the microprocessor is configured with an MMIO address space which has the same specification as the VGPU and is mutually mapped, and the method comprises the following steps:

sensing an MMIO request aiming at the VGPU based on an MMIO address space mapping relation between the microprocessor and the VGPU, wherein the MMIO request comprises a required target MMIO address;

calculating the address offset corresponding to the MMIO request according to the mapping position of the target MMIO address in the MMIO address space of the microprocessor;

providing the address offset to a GPU driver in the host machine, so that the GPU driver calls a physical GPU resource pointed by the address offset to respond to the MMIO request;

and after the response is completed, notifying the VGPU to enable the VGPU to continue to work.

9. A computing device as a host, having a custom microprocessor assembled thereon and created with a VGPU, the microprocessor configured with MMIO address space of the same specification as the VGPU and mapped to each other, the computing device comprising a memory, a processor and a communication component;

the memory is to store one or more computer instructions;

the processor, coupled with the memory and the communication component, to execute the one or more computer instructions to:

sensing an MMIO request aiming at the VGPU by utilizing the microprocessor based on the MMIO address space mapping relation between the microprocessor and the VGPU, wherein the MMIO request comprises a required target MMIO address;

utilizing the microprocessor to calculate the address offset corresponding to the MMIO request according to the mapping position of the target MMIO address in the MMIO address space;

calling the physical GPU resource pointed by the address offset to respond to the MMIO request;

and after the response is finished, informing the VGPU by the microprocessor so that the VGPU continues to work.

10. The computing device of claim 9, the processor further to:

adopting an Extended Page Table (EPT) technology to map the MMIO address space of the VGPU to the MMIO address space of the microprocessor in advance;

and disconnecting the mapping relation between the MMIO address space of the VGPU and the original mapping space of the VGPU in the physical address space of the host machine.

11. A microprocessor mounted on a host, said microprocessor configured with MMIO address space of the same specification as a VGPU created on said host and mapped to each other, said microprocessor comprising a memory, a processor and a communication component;

the memory is to store one or more computer instructions;

the processor, coupled with the memory and the communication component, to execute the one or more computer instructions to:

sensing an MMIO request aiming at the VGPU based on an MMIO address space mapping relation between the microprocessor and the VGPU, wherein the MMIO request comprises a required target MMIO address;

calculating the address offset corresponding to the MMIO request according to the mapping position of the target MMIO address in the MMIO address space of the microprocessor;

providing the address offset to a GPU driver in the host machine, so that the GPU driver calls a physical GPU resource pointed by the address offset to respond to the MMIO request;

and after the response is completed, notifying the VGPU to enable the VGPU to continue to work.

12. The microprocessor of claim 11, comprising a programmable array logic (FPGA) or a Complex Programmable Logic Device (CPLD).

13. A computer-readable storage medium storing computer instructions that, when executed by one or more processors, cause the one or more processors to perform the VGPU acceleration method of any one of claims 1-8.

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