CN115101485B - Chip structure and manufacturing method, and electronic device - Google Patents
Chip structure and manufacturing method, and electronic device Download PDFInfo
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- CN115101485B CN115101485B CN202210735433.6A CN202210735433A CN115101485B CN 115101485 B CN115101485 B CN 115101485B CN 202210735433 A CN202210735433 A CN 202210735433A CN 115101485 B CN115101485 B CN 115101485B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 49
- 238000009792 diffusion process Methods 0.000 claims abstract description 95
- 238000000034 method Methods 0.000 claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims description 84
- 239000000758 substrate Substances 0.000 claims description 31
- 239000000463 material Substances 0.000 claims description 8
- 239000011093 chipboard Substances 0.000 claims description 7
- 230000000149 penetrating effect Effects 0.000 claims description 6
- 239000011800 void material Substances 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 3
- 239000012811 non-conductive material Substances 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 12
- 238000003698 laser cutting Methods 0.000 abstract description 7
- 238000005520 cutting process Methods 0.000 abstract description 6
- 238000004220 aggregation Methods 0.000 abstract description 2
- 230000002776 aggregation Effects 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 description 10
- 238000005240 physical vapour deposition Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 238000003486 chemical etching Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000001125 extrusion Methods 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 238000004227 thermal cracking Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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Abstract
The invention provides a chip structure, a manufacturing method and electronic equipment, wherein a thermal diffusion buffer layer is arranged at the edge of a conventional chip structure, has higher heat conduction capacity, can diffuse a large amount of heat generated in the process of cutting a chip by laser to an adjacent area, effectively relieves the problem of overhigh local temperature in the cutting process, and improves the stability of the chip. Meanwhile, a thermal diffusion buffer zone is arranged below the thermal diffusion buffer zone, gaps exist in the thermal diffusion buffer zone, and the gaps can effectively absorb expansion deformation generated when a chip structure is heated in the laser cutting process, so that structural damage caused by stress aggregation is relieved.
Description
Technical Field
The present application relates to the field of chip manufacturing, and in particular, to a chip structure, a manufacturing method, and an electronic device.
Background
In the manufacturing process of the chips, the chips are not independent, but a plurality of chips are integrally connected together. The laser cutting operation is not performed until most of the manufacturing processes are completed, and an independent chip is obtained, as shown in fig. 1. Very high temperatures and heat are generated at localized locations of the scribe line during the laser cutting operation. Under the condition of too concentrated temperature and heat, the phenomenon of expansion and even cracking of the chip in the cutting process can be caused, so that the chip is abnormal.
Disclosure of Invention
In order to solve one of the technical problems, the invention provides a chip structure, a manufacturing method and electronic equipment.
A first aspect of an embodiment of the present invention provides a chip structure, including:
A first semiconductor layer, a second semiconductor layer, an active layer between the first semiconductor layer and the second semiconductor layer,
A first conductive layer electrically connected with the first semiconductor layer, a reflective layer electrically connected with the first conductive layer, a second conductive layer electrically connected with the reflective layer, and an electrode electrically connected with the second conductive layer, wherein the first conductive layer, the reflective layer, the second conductive layer and the electrode form a first electrical connection layer,
A recess penetrating the first semiconductor layer and the active layer and extending into the second semiconductor layer, a void being formed in the recess,
A first insulating layer covering the side wall of the recess and one side of the first electrical connection layer, a third conductive layer partially contacting the insulating layer and partially electrically connected to the second semiconductor layer through the recess,
A substrate in contact with the third conductive layer,
The chip structure further comprises a thermal diffusion buffer structure, the thermal diffusion buffer structure comprises a thermal diffusion buffer layer and a thermal diffusion buffer zone, the thermal diffusion buffer layer is arranged around the edge of the second conductive layer and isolated from the first electrical connection layer, the first semiconductor layer, the second semiconductor layer, the active layer and the third conductive layer, and the thermal diffusion buffer zone is located under the thermal diffusion buffer layer and comprises the third conductive layer with a gap.
Optionally, the chip structure further includes a second insulating layer partially located between the first semiconductor layer and the second conductive layer and laterally adjacent to the first conductive layer and the reflective layer, and partially exposed outside the first semiconductor layer.
Optionally, the thermal diffusion buffer layer and the second conductive layer are made of the same material.
Optionally, the thermal conductivity of the thermal diffusion buffer layer is greater than 10W/(m·k).
Optionally, the gap in the thermal diffusion buffer region has an opening, and the opening is located towards the outside of the chip structure.
Optionally, the gap in the thermal diffusion buffer region has an opening, and the opening is located towards the outside of the chip structure.
Optionally, the reflective layer, the second conductive layer, the third conductive layer, and the electrode are all multiple metal layers.
Optionally, when the substrate is made of a non-conductive material, the third conductive layer is a second electrical connection layer, and when the substrate is conductive, the third conductive layer and the substrate form the second electrical connection layer.
A second aspect of the embodiment of the present invention provides a method for manufacturing a chip structure, where the method includes:
Sequentially growing a second semiconductor layer, an active layer and a first semiconductor layer on an epitaxial growth substrate, and manufacturing at least two depressions penetrating through the first semiconductor layer and the active layer and extending into the second semiconductor layer, wherein at least one depression is positioned at the edge of a chip and surrounds most of the area of the edge of the chip, and at least one depression is positioned in the inner position of the chip;
Sequentially manufacturing a first conductive layer and a reflecting layer on part of the surface of the first semiconductor layer, manufacturing a second conductive layer on part of the surface of the first semiconductor layer, the side surfaces of the first conductive layer and the reflecting layer and the surface of the reflecting layer, manufacturing a thermal diffusion buffer layer on the rest of the surface of the first semiconductor layer and the side surface of the chip edge recess, and leaving a gap between the thermal diffusion buffer layer and the adjacent side surface of the second conductive layer;
manufacturing a first insulating layer on the surface of the second conductive layer, the surface of the thermal diffusion buffer layer and the concave side surface in the chip, wherein the first insulating layer is filled in a gap between the thermal diffusion buffer layer and the adjacent side surface of the second conductive layer;
Manufacturing third conductive layers on the surfaces of the first insulating layer and the substrate respectively, wherein the third conductive layers on the surface of the first insulating layer are electrically connected with the second semiconductor layer through the concave parts in the chip, and when the third conductive layers on the surface of the first insulating layer and the third conductive layers on the surface of the substrate are connected into a whole, gaps are formed in the third conductive layers at all concave positions, wherein the third conductive layers which are positioned at the edge of the chip and are internally provided with gaps form a thermal diffusion buffer zone;
Removing the epitaxial growth substrate, removing the redundant second semiconductor layer, the active layer and the first semiconductor layer, and manufacturing an electrode electrically connected with the second conductive layer to obtain a chip board formed by a plurality of chip structures;
dicing is performed at the thermal diffusion buffer layer position to obtain an independent chip structure.
Optionally, the method further comprises:
Forming a second insulating layer on the surface of the rest part of the first semiconductor layer, and arranging the second insulating layer around the first conductive layer and the reflecting layer;
and manufacturing a second conductive layer on the surface of the first conductive layer and the surface of the second insulating layer part, manufacturing a thermal diffusion buffer layer on the residual surface of the second insulating layer part and the side surface of the chip edge recess, and leaving a gap between the thermal diffusion buffer layer and the adjacent side surface of the second conductive layer.
A third aspect of the embodiment of the present invention provides an electronic device, where the electronic device includes the chip structure according to the first aspect of the embodiment of the present invention.
The chip structure and the manufacturing method have the beneficial effects that the heat diffusion buffer layer is arranged at the edge of the conventional chip structure, has higher heat conduction capacity, can diffuse a large amount of heat generated in the process of cutting the chip by laser to adjacent areas, effectively relieves the problem of overhigh local temperature in the cutting process, and improves the stability of the chip. Meanwhile, a thermal diffusion buffer zone is arranged below the thermal diffusion buffer zone, gaps exist in the thermal diffusion buffer zone, and the gaps can effectively absorb expansion deformation generated when a chip structure is heated in the laser cutting process, so that structural damage caused by stress aggregation is relieved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:
FIG. 1 is a schematic diagram of a chip board dicing process;
FIG. 2 is a schematic diagram of a conventional chip structure;
fig. 3 is a schematic structural diagram of a chip structure according to embodiment 1 of the present invention;
FIG. 4 is a schematic diagram of a thermal diffusion buffer layer and a thermal diffusion buffer zone according to embodiment 1 of the present invention;
FIG. 5 is a schematic diagram of another chip structure according to embodiment 1 of the present invention;
FIG. 6 is a flowchart of a method for fabricating a chip structure according to embodiment 2 of the present invention;
Fig. 7 to 13 are schematic views illustrating a manufacturing process of a chip structure according to embodiment 2 of the present invention;
FIG. 14 is a flowchart of another method for fabricating a chip structure according to embodiment 2 of the present invention;
fig. 15 to 19 are schematic views illustrating a manufacturing process of another chip structure according to embodiment 2 of the present invention.
Reference numerals:
1. The semiconductor device comprises a first semiconductor layer, 2, a second semiconductor layer, 3, an active layer, 4, a first conductive layer, 5, a reflecting layer, 6, a second conductive layer, 7, an electrode, 8, a recess, 9, a first insulating layer, 10, a second insulating layer, 11, a third conductive layer, 12, a substrate, 13, a gap, 14, a thermal diffusion buffer layer, 15, a thermal diffusion buffer zone, 16 and an epitaxial growth substrate.
Detailed Description
In order to make the technical solutions and advantages of the embodiments of the present application more apparent, the following detailed description of exemplary embodiments of the present application is provided in conjunction with the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present application and not exhaustive of all embodiments. It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other.
Example 1
As shown in fig. 2, a chip structure specifically includes:
A first semiconductor layer 1, a second semiconductor layer 2, an active layer 3 between said first semiconductor layer 1 and said second semiconductor layer 2,
A first conductive layer 4 electrically connected to the first semiconductor layer 1, a reflective layer 5 electrically connected to the first conductive layer 4, a second conductive layer 6 electrically connected to the reflective layer 5, and an electrode 7 electrically connected to the second conductive layer 6, wherein the first conductive layer 4, the reflective layer 5, the second conductive layer 6, and the electrode 7 constitute a first electrical connection layer,
A recess 8 penetrating the first semiconductor layer 1 and the active layer 3 and extending into the second semiconductor layer 2, a void 13 being formed in the recess 8,
A first insulating layer 9 covering the side walls of the recess 8 and the side of the first electrical connection layer, a third conductive layer 11 partially contacting the first insulating layer 9 and partially electrically connected to the second semiconductor layer 2 through the recess 8,
A substrate 12 in contact with the third conductive layer 11.
Wherein the reflective layer 5, the second conductive layer 6, the third conductive layer 11 and the electrode 7 are all multi-layered metal layers. When the substrate 12 is made of non-conductive material, the third conductive layer 11 is a second electrical connection layer, and when the substrate 12 is conductive, the third conductive layer 11 and the substrate 12 form the second electrical connection layer. It is to be noted that a step may occur between the third conductive layer 11 and the first insulating layer 9 at different positions. In the actual production and manufacturing process, the height of the step is far smaller than that of the recess, and no obvious gap is formed at the step.
The chip structure is a conventional structure of the existing chip structure. In the conventional structure of the chip structure, high heat is generated at the dicing street surface due to the laser irradiation during the laser dicing. The present embodiment provides a thermal diffusion buffer structure on the basis of the conventional chip structure described above. The thermal diffusion buffer structure includes a thermal diffusion buffer layer 14 and a thermal diffusion buffer zone 15, as shown in fig. 3. The thermal diffusion buffer layer 14 is located outside the second conductive layer 6, i.e., at the edge of the overall chip structure. The thermal diffusion buffer layer 14 is also located on the line through which the dicing streets must be passed when the chip is laser diced. The thermal diffusion buffer layer 14 is made of a material having high thermal conductivity, for example, a metal material or the like, and has a thermal conductivity of more than 10W/(m·k). In this way, when the chip is cut by laser, the thermal diffusion buffer layer 14 can rapidly diffuse a large amount of heat generated on the surface of the dicing channel due to laser irradiation to the adjacent area, so that the problem of local overhigh temperature is effectively alleviated. In order to save the manufacturing cost of the thermal diffusion buffer layer 14 and simplify the manufacturing process, the thermal diffusion buffer layer 14 may be made of exactly the same material and structure as the second conductive layer 6.
In addition, in the present embodiment, since the thermal diffusion buffer layer 14 only plays a role of heat conduction, in order not to affect the performance of the chip, when the thermal diffusion buffer layer 14 is made of a conductive material, for example, a metal material, the thermal diffusion buffer layer 14 needs to be insulated from other structures, so as to avoid the thermal diffusion buffer layer 14 being electrically connected with other structures to affect the normal use of the chip. Specifically, the present embodiment uses the existing first insulating layer 9 in the conventional chip structure to insulate the thermal diffusion buffer layer 14 from the first electrical connection layer, the first semiconductor layer 1, the second semiconductor layer 2, the active layer 3 and the third conductive layer 11, and only fine-tuning the size of the first insulating layer 9 is required, so that no complicated process is generated.
Further, the edge of the third conductive layer 11 is raised away from the substrate 12 to form a thermal diffusion buffer zone 15, the thermal diffusion buffer zone 15 is insulated from the thermal diffusion buffer layer 14 by the first insulating layer 9, and a gap 13 is formed inside the thermal diffusion buffer zone 15.
Specifically, in this embodiment, a thermal diffusion buffer 15 is also disposed at the edge of the chip structure and on the line of the laser scribe line. The thermal diffusion buffer 15 is substantially the same as the principle of the generation of the recess 8, and the difference in naming in this embodiment facilitates the functional distinction between the two. The thermal diffusion buffer zone 15 is also formed with a void 13 inside, and the void 13 is caused by the excessively large height difference inside the recess 8 and the thermal diffusion buffer zone 15 during the bonding process of the third conductive layer 11 under the process of heating and pressurizing during the fabrication of the chip structure, and the conventional phenomenon is not described in the present embodiment. The thermal diffusion buffer 15 has a side-opening structure with its opening facing the outside of the chip structure. The voids 13 inside the thermal diffusion buffer zone 15 can achieve an excellent mating effect with the thermal diffusion buffer layer 14. As shown in fig. 4, when the heat generated during laser cutting causes expansion of the dicing street material, the voids 13 inside the thermal diffusion buffer layer 14 can effectively absorb the partially expanded volume, thereby buffering the extrusion of the material generated during expansion, and effectively avoiding the risk of thermal cracking.
Further, as shown in fig. 5, the chip structure of the present embodiment further includes a second insulating layer partially located between the first semiconductor layer and the second conductive layer and adjacent to the side surfaces of the first conductive layer and the reflective layer, and partially exposed outside the first semiconductor layer, where the second insulating layer can ensure that a better insulating effect is obtained in the manufacturing process of the chip structure.
Example 2
The present embodiment provides a method for manufacturing a chip structure, which can refer to the content described in embodiment 1, and the description of this embodiment is omitted. The method proposed by the embodiment firstly comprises the steps of manufacturing a chip board, arranging a plurality of independent chip structures in an array manner, and obtaining the independent chip structures after laser cutting operation is performed after the chip board is manufactured. As shown in fig. 6, the method proposed in this embodiment includes the following steps:
S101, sequentially growing a second semiconductor layer 2, an active layer 3 and a first semiconductor layer 1 on an epitaxial growth substrate 16, and making at least two recesses 8 penetrating the first semiconductor layer 1 and the active layer 3 and extending into the second semiconductor layer 2, wherein at least one recess is located at the edge of the chip and surrounds most of the area of the edge of the chip.
First, the second semiconductor layer 2, the active layer 3, and the first semiconductor layer 1 are sequentially grown on the basis of the epitaxial growth substrate 16, as shown in fig. 7. Then, a recess 8 extending through the first semiconductor layer 1 and the active layer 3 and into the second semiconductor layer 2 is obtained by patterning with an ultraviolet mask and chemical etching, as shown in fig. 8. Wherein the recesses 8 are distributed in the middle region and in the edge region of the second semiconductor layer 2.
S102, sequentially manufacturing a first conductive layer 4 and a reflecting layer 5 on part of the surface of the first semiconductor layer 1, manufacturing a second conductive layer 6 on part of the surface of the first semiconductor layer 1, the side surfaces of the first conductive layer 4 and the reflecting layer 5 and the surface of the reflecting layer 5, manufacturing a thermal diffusion buffer layer 14 on the rest of the surface of the first semiconductor layer 1 and the side surface of the chip edge recess, and leaving a gap between the thermal diffusion buffer layer 14 and the adjacent side surfaces of the second conductive layer 6.
A first conductive layer 4 and a reflective layer 5 are sequentially formed on a part of the surface of the first semiconductor layer 1 using a method of ultraviolet mask patterning and physical vapor deposition, as shown in fig. 9. A second conductive layer 6 is formed on a part of the surface of the first semiconductor layer 1, the side surfaces of the first conductive layer 4 and the reflective layer 5, and the surface of the reflective layer 5 by using a method of ultraviolet mask patterning and physical vapor deposition, a thermal diffusion buffer layer 14 is formed on the remaining surface of the first semiconductor layer 1 and the side surface of the chip edge recess, and a gap is left between the thermal diffusion buffer layer 14 and the adjacent side surface of the second conductive layer 6, as shown in fig. 10. It should be noted that if the materials and structures of the second conductive layer 6 and the thermal diffusion buffer layer 14 are consistent, the ultraviolet mask patterning and physical vapor deposition are performed once, and if the materials and structures of the second conductive layer 6 and the thermal diffusion buffer layer 14 are different, at least two ultraviolet mask patterning and physical vapor deposition processes are required.
S103, manufacturing a first insulating layer 9 on the surface of the second conductive layer 6, the surface of the thermal diffusion buffer layer 14 and the concave side surface inside the chip, wherein the first insulating layer 9 is filled in a gap between the thermal diffusion buffer layer 14 and the adjacent side surface of the second conductive layer 6.
The first insulating layer 9 is formed on the surface of the second conductive layer 6, the surface of the thermal diffusion buffer layer 14 and the side surface of the recess 8 in the chip by vapor deposition in combination with ultraviolet mask patterning and chemical etching, as shown in fig. 11. And the first insulating layer 9 fills in the gap between the adjacent sides of the thermal diffusion buffer layer 14 and the second conductive layer 6 to ensure no electrical connection between the thermal diffusion buffer layer 14 and the second conductive layer 6.
And S104, respectively manufacturing third conductive layers 11 on the surfaces of the first insulating layer 9 and the substrate 12, wherein the third conductive layers 11 on the surface of the first insulating layer 9 are electrically connected with the second semiconductor layer 2 through the concave 8 in the chip, and when the third conductive layers 11 on the surface of the first insulating layer 9 and the third conductive layers 11 on the surface of the substrate 12 are connected into a whole, gaps 13 are formed in the third conductive layers 11 at all the concave 8 positions, wherein the third conductive layers 11 which are positioned at the edge of the chip and are internally provided with gaps form a thermal diffusion buffer zone 15.
The third conductive layer 11 is formed on the surface of the first insulating layer 9 and the surface of the substrate 12 by physical vapor deposition, and the third conductive layer 11 on the surface of the first insulating layer 9 is electrically connected to the second semiconductor layer 2 through the recess 8 in the chip, as shown in fig. 12. Then, the third conductive layer 11 on the surface of the first insulating layer 9 and the third conductive layer 11 on the surface of the substrate 12 are connected together under the condition of heating and pressurizing. In this process, a significant gap 13 remains due to the excessive level difference inside the recess 8, as shown in fig. 13. The third conductive layer is positioned at the edge of the chip and is internally provided with a gap to form a thermal diffusion buffer area.
And S105, removing the epitaxial growth substrate 16, removing the redundant second semiconductor layer 2, the active layer 3 and the first semiconductor layer 1, and manufacturing the electrode 7 electrically connected with the second conductive layer 6 to obtain a chip board formed by a plurality of chip structures.
The epitaxial growth substrate 16 is removed and the unwanted second semiconductor layer 2, active layer 3 and first semiconductor layer 1 are removed by means of uv mask patterning and chemical etching. Then, an electrode 7 electrically connected to the second conductive layer 6 is obtained by means of physical vapor deposition, as shown in fig. 3. At this time, a chip board formed by arranging a plurality of chip structures in an array manner can be obtained.
S106, cutting at the position of the thermal diffusion buffer layer 14 to obtain an independent chip structure.
Finally, only laser cutting is needed at the position of the thermal diffusion buffer layer 14 to obtain an independent chip structure.
Further, before the first insulating layer is fabricated, a second insulating layer is also fabricated according to the method proposed in this embodiment, as shown in fig. 14, and the specific process is as follows:
Forming a second insulating layer 10 on the surface of the remaining portion of the first semiconductor layer 1, and disposing the second insulating layer 10 around the first conductive layer 4 and the reflective layer 5;
The second conductive layer 6 is formed on the surface of the first conductive layer 4 and part of the surface of the second insulating layer 10, the thermal diffusion buffer layer 14 is formed on the rest surface of the second insulating layer 10 and the concave side surface of the chip edge, and a gap is reserved between the thermal diffusion buffer layer 14 and the adjacent side surface of the second conductive layer 6.
A first conductive layer 4 and a reflective layer 5 are sequentially formed on a part of the surface of the first semiconductor layer 1 using a method of ultraviolet mask patterning and physical vapor deposition, as shown in fig. 9. Then, the second insulating layer 10 is obtained by vapor deposition, patterning with ultraviolet mask, and chemical etching, as shown in fig. 15. The side of the second insulating layer 10 is in contact with the side of the first conductive layer 4 and the reflective layer 5. A second conductive layer 6 is formed on the surface of the first conductive layer 4 and a part of the surface of the second insulating layer 10 by using a method of ultraviolet mask patterning and physical vapor deposition, a thermal diffusion buffer layer 14 is formed on the remaining surface of the second insulating layer 10, and a gap is left between the thermal diffusion buffer layer 14 and the adjacent side surface of the second conductive layer 6, as shown in fig. 16.
The second insulating layer 10 can ensure a better insulating effect during the fabrication of the chip structure. Except for the process steps in the process of manufacturing the second insulating layer 10, the other manufacturing process steps are not different from the process steps of manufacturing the chip structure without the second insulating layer 10, and the detailed description of the manufacturing process is omitted in this embodiment, as shown in fig. 17 to 19.
Example 3
The embodiment proposes an electronic device, which includes the chip structure described in embodiment 1, and will not be described herein.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (10)
1. A chip structure, comprising:
A first semiconductor layer, a second semiconductor layer, an active layer between the first semiconductor layer and the second semiconductor layer,
A first conductive layer electrically connected with the first semiconductor layer, a reflective layer electrically connected with the first conductive layer, a second conductive layer electrically connected with the reflective layer, and an electrode electrically connected with the second conductive layer, wherein the first conductive layer, the reflective layer, the second conductive layer and the electrode form a first electrical connection layer,
A recess penetrating the first semiconductor layer and the active layer and extending into the second semiconductor layer, a void being formed in the recess,
A first insulating layer covering the side wall of the recess and one side of the first electrical connection layer, a third conductive layer partially contacting the insulating layer and partially electrically connected to the second semiconductor layer through the recess,
A substrate in contact with the third conductive layer,
The chip structure is characterized by further comprising a thermal diffusion buffer structure, the thermal diffusion buffer structure comprises a thermal diffusion buffer layer and a thermal diffusion buffer zone, the thermal diffusion buffer layer is arranged around the edge of the second conductive layer and isolated from the first electric connection layer, the first semiconductor layer, the second semiconductor layer, the active layer and the third conductive layer, and the thermal diffusion buffer zone is positioned under the thermal diffusion buffer layer and comprises the third conductive layer with a gap.
2. The chip structure of claim 1, further comprising a second insulating layer partially between the first semiconductor layer and the second conductive layer and laterally adjacent the first conductive layer and the reflective layer, and partially exposed outside the first semiconductor layer.
3. The chip structure of claim 1, wherein the thermal diffusion buffer layer is the same material as the second conductive layer.
4. The chip structure of claim 1, wherein the thermal conductivity of the thermal diffusion buffer layer is greater than 10W/(m-K).
5. The chip structure of claim 1, wherein the void in the thermal diffusion buffer is open and the open is located towards the outside of the chip structure.
6. The chip structure of claim 1, wherein the reflective layer, the second conductive layer, the third conductive layer, and the electrode are each a plurality of metal layers.
7. The chip structure of claim 1, wherein the third conductive layer is a second electrical connection layer when the substrate is a non-conductive material, and wherein the third conductive layer and the substrate form a second electrical connection layer when the substrate is conductive.
8. A method for fabricating a chip structure, the method comprising:
Sequentially growing a second semiconductor layer, an active layer and a first semiconductor layer on an epitaxial growth substrate, and manufacturing at least two depressions penetrating through the first semiconductor layer and the active layer and extending into the second semiconductor layer, wherein at least one depression is positioned at the edge of a chip and surrounds most of the area of the edge of the chip, and at least one depression is positioned in the inner position of the chip;
Sequentially manufacturing a first conductive layer and a reflecting layer on part of the surface of the first semiconductor layer, manufacturing a second conductive layer on part of the surface of the first semiconductor layer, the side surfaces of the first conductive layer and the reflecting layer and the surface of the reflecting layer, manufacturing a thermal diffusion buffer layer on the rest of the surface of the first semiconductor layer and the side surface of the chip edge recess, and leaving a gap between the thermal diffusion buffer layer and the adjacent side surface of the second conductive layer;
manufacturing a first insulating layer on the surface of the second conductive layer, the surface of the thermal diffusion buffer layer and the concave side surface in the chip, wherein the first insulating layer is filled in a gap between the thermal diffusion buffer layer and the adjacent side surface of the second conductive layer;
Manufacturing third conductive layers on the surfaces of the first insulating layer and the substrate respectively, wherein the third conductive layers on the surface of the first insulating layer are electrically connected with the second semiconductor layer through the concave parts in the chip, and when the third conductive layers on the surface of the first insulating layer and the third conductive layers on the surface of the substrate are connected into a whole, gaps are formed in the third conductive layers at all concave positions, wherein the third conductive layers which are positioned at the edge of the chip and are internally provided with gaps form a thermal diffusion buffer zone;
Removing the epitaxial growth substrate, removing the redundant second semiconductor layer, the active layer and the first semiconductor layer, and manufacturing an electrode electrically connected with the second conductive layer to obtain a chip board formed by a plurality of chip structures;
dicing is performed at the thermal diffusion buffer layer position to obtain an independent chip structure.
9. The method of claim 8, wherein the method further comprises:
Forming a second insulating layer on the surface of the rest part of the first semiconductor layer, and arranging the second insulating layer around the first conductive layer and the reflecting layer;
and manufacturing a second conductive layer on the surface of the first conductive layer and the surface of the second insulating layer part, manufacturing a thermal diffusion buffer layer on the residual surface of the second insulating layer part and the side surface of the chip edge recess, and leaving a gap between the thermal diffusion buffer layer and the adjacent side surface of the second conductive layer.
10. An electronic device, characterized in that it comprises a chip structure as claimed in any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210735433.6A CN115101485B (en) | 2022-06-27 | 2022-06-27 | Chip structure and manufacturing method, and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210735433.6A CN115101485B (en) | 2022-06-27 | 2022-06-27 | Chip structure and manufacturing method, and electronic device |
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| Publication Number | Publication Date |
|---|---|
| CN115101485A CN115101485A (en) | 2022-09-23 |
| CN115101485B true CN115101485B (en) | 2024-12-10 |
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| CN108550552A (en) * | 2018-04-24 | 2018-09-18 | 昆山国显光电有限公司 | Display panel, display device, display panel motherboard and preparation method thereof |
| CN108598112A (en) * | 2018-04-24 | 2018-09-28 | 昆山国显光电有限公司 | Flexible Displays motherboard and flexible display panels |
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| CN104868058B (en) * | 2015-03-27 | 2018-01-09 | 上海天马微电子有限公司 | Display panel, display device and display panel mother board |
| US9553036B1 (en) * | 2015-07-09 | 2017-01-24 | Powertech Technology Inc. | Semiconductor package and manufacturing method thereof |
| KR20170025653A (en) * | 2015-08-31 | 2017-03-08 | 엘지디스플레이 주식회사 | Organic light emitting diode display and manufacturing method of the same |
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| CN209496874U (en) * | 2019-02-28 | 2019-10-15 | 云谷（固安）科技有限公司 | Display panel and display device |
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| CN113658871B (en) * | 2021-06-27 | 2024-08-02 | 厦门芯光润泽科技有限公司 | Manufacturing method of power module |
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| CN108598112A (en) * | 2018-04-24 | 2018-09-28 | 昆山国显光电有限公司 | Flexible Displays motherboard and flexible display panels |
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