CN115117148A - Structure and manufacturing method of dummy active region of MOS transistor - Google Patents

Abstract

The invention discloses a structure of a dummy active area of a MOS transistor. A plurality of dummy active areas separated by field oxygen are formed around the active area. Each dummy active region has a stripe structure, and the length direction of the dummy active region is parallel to the length direction of the active region. The length of the dummy active region is smaller than the length of the active region. A plurality of dummy active area array blocks are provided along the length of the active area. Along the width direction of the active area, the dummy active area array block is formed by alternately arranging a plurality of dummy active areas and field oxygen located between the dummy active areas, and the plurality of fields in the dummy active area array block Oxygen prevents a leakage channel formed through the dummy active region from appearing at the periphery of the active region, thereby reducing leakage of the MOS transistor. The invention also discloses a manufacturing method of the dummy active region of the MOS transistor. The present invention can prevent the dummy active region itself from forming a leakage channel, thereby reducing the leakage between MOS transistors in adjacent active regions.

Description

Structure and manufacturing method of dummy active region of MOS transistor

technical field

The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a structure of a dummy active region of a MOS transistor. The invention also relates to a structure and a manufacturing method of a dummy active region of a MOS transistor.

Background technique

In the existing LDMOS structure, a dummy active area (AA dummy) is usually inserted around the active area (AA). The AA dummy inserted in the dummy active area insertion area (AA dummy deck) will be perpendicular to the AA, and metal silicide such as NiSi will also be grown on the AA dummy. As a result, the AA dummy will straddle the input and output N wells (IO NW )/input and output P well (IO PW), so that the IO NW/PW is turned on, and there is a leakage channel between the IO NW and the IO PW.

As shown in FIG. 1, it is the layout of the dummy active region 105 of the conventional MOS transistor. In the structure of the source region 105 , a field oxygen 107 is formed on the semiconductor substrate 106 , and the field oxygen 107 isolates the active region 101 . The field oxygen 107 usually adopts shallow trench isolation.

A plurality of dummy active regions 105 isolated by the field oxygen 107 are formed around the active region 101 . The formation area of the dummy active region 105 is shown as the dotted frame 102 . The shown field oxygen 107 typically employs shallow trench isolation (STI).

Each of the dummy active regions 105 has a strip-shaped structure, and the length direction of the dummy active region 105 is perpendicular to the length direction of the active region 101 . As shown in FIG. 1 , the length of each of the dummy active regions 105 spans the entire formation region 102 of the dummy active regions 105 .

Generally, an N-well 104 and a P-well 103 are formed on the semiconductor substrate 106, and the junction depths of the N-well 104 and the P-well 103 are larger than the depth of the field oxygen 107; each of the active regions 101 consists of the N-well 104 or the P-well 103 in the surrounding area of the field oxygen 107 .

The N well 104 includes an IO N well, and the P well 103 includes an IO P well. In FIG. 1 , each of the dummy active regions intersecting with the N well 104 is individually marked with a mark 105 . The graph of the circled area in FIG. 1 is also enlarged. As shown in FIG. 2 , in the direction of extending the length of the dummy active region 105 a , the dummy active region 105 a spans the two adjacent N wells 104 and the P well 103 . Moreover, metal silicide 107 is also formed on the surface of the dummy active region 105a, which causes a leakage channel to be formed in the dummy active region 105a, so that the active regions on both sides of the dummy active region 105a MOS transistors such as LDMOS are prone to leakage.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is to provide a structure of a dummy active region of a MOS transistor, which can prevent the dummy active region itself from forming a leakage channel, thereby reducing the leakage between MOS transistors in adjacent active regions. To this end, the present invention also provides a structure and a manufacturing method of a dummy active region of a MOS transistor.

In order to solve the above technical problems, in the structure of the dummy active region of the MOS transistor provided by the present invention, field oxygen is formed on the semiconductor substrate, and the field oxygen isolates the active region.

A plurality of dummy active regions isolated by the field oxygen are formed around the active region.

Each of the dummy active regions has a stripe structure, and the length direction of the dummy active region is parallel to the length direction of the active region.

The length of the dummy active region is smaller than the length of the active region.

A plurality of dummy active area array blocks are arranged along the length side of the active area, and each of the dummy active area array blocks corresponds to an area segment along the length side of the active area.

For each of the dummy active area array blocks, along the width direction of the active area, the dummy active area array block is composed of a plurality of the dummy active areas and located between the dummy active areas The field oxygen is alternately arranged, and a plurality of the field oxygen in the dummy active area array block prevents the leakage channel formed by the dummy active area from appearing in the periphery of the active area, thereby reducing the Leakage of MOS transistors.

A further improvement is that an N-well and a P-well are formed on the semiconductor substrate, and the junction depths of the N-well and the P-well are both greater than the depth of the field oxygen; each of the active regions is formed by the The N-well or the P-well in the field oxygen surround region is formed.

A further improvement is that the N well includes an IO N well, and the P well includes an IO P well.

A further improvement is that the MOS transistor includes a gate structure, a channel region, a source region and a drain region, and the channel region is located before the source region and the drain region and is covered by the gate structure.

A further improvement is that the gate structure of the MOS transistor includes a gate dielectric layer and a gate conductive material layer stacked in sequence.

A further improvement is that the gate structure of the MOS transistor adopts a high dielectric constant metal gate (HKMG), and the gate dielectric layer includes a high dielectric constant layer (HK), which is formed at the bottom of the high dielectric constant layer. There is an interface layer including a bottom barrier layer on top of the high dielectric layer.

The gate conductive material layer adopts a metal gate (MG), and there is a work function layer between the metal gate and the bottom barrier layer.

A further improvement is that the MOS transistor includes NMOS and PMOS.

The work function layer of the NMOS is an N-type work function layer, and the work function layer of the PMOS is a P-type work function layer.

A further improvement is that the material of the N-type work function layer includes TiAl; the material of the P-type work function layer includes TiN.

A further improvement is that metal silicide is formed on the surface of the source region and the drain region; metal silicide is also formed on the surface of the dummy active region.

A further improvement is that the material of the metal silicide includes NiSi.

A further improvement is that the MOS transistor includes an LDMOS, and the LDMOS further includes a drift region located between the channel region and the drain region.

A further improvement is that a drift region field oxygen is also formed in the surface region of the drift region, and the depth of the drift region field oxygen is smaller than the depth of the field oxygen.

The gate conductive material layer also extends onto the surface of the drift region field oxygen.

In order to solve the above technical problems, the method for manufacturing the dummy active region of the MOS transistor provided by the present invention includes the following steps:

Step 1. Define an active area and a dummy active area on the layout at the same time, the dummy active area is located at the periphery of the active area, and the active area and the periphery of the dummy active area are fields Oxygen formation area.

Each of the dummy active regions has a stripe structure, and the length direction of the dummy active region is parallel to the length direction of the active region.

The length of the dummy active region is smaller than the length of the active region.

A plurality of dummy active area array blocks are arranged along the length side of the active area, and each of the dummy active area array blocks corresponds to an area segment along the length side of the active area.

For each of the dummy active area array blocks, along the width direction of the active area, the dummy active area array block is composed of a plurality of the dummy active areas and located between the dummy active areas The field oxygens are arranged alternately.

Step 2, using the layout to make a mask.

Step 3: Transfer the layout on the reticle to the semiconductor substrate by using a photolithography process, form the field oxygen on the semiconductor substrate, and isolate the active region and the active region through the field oxygen. The dummy active region; the plurality of field oxides in the dummy active region array block prevent the leakage channel formed through the dummy active region from appearing in the periphery of the active region, thereby reducing the resistance of the MOS transistor. Leakage.

A further improvement is that in step 1, it also includes providing an original layout, the original layout includes an original dummy active area, the original dummy active area is located around the active area, and the original dummy has The length direction of the active area is perpendicular to the length direction of the active area;

The dummy active area in the layout is obtained by rotating the original dummy active area in the original layout by 90 degrees.

A further improvement is that, in step 1, in the mask tooling production stage, the original pseudo active area in the original layout is rotated by 90 degrees through a logic operation to obtain all the images in the layout. Describe the pseudo active region.

It is different from that in the prior art, in the formation area of the dummy active area around the active area, which is perpendicular to the length of the active area, so that the length of each dummy active area spans the entire formation area of the dummy active area. , the length side of each dummy active area of the present invention is set to be in the same direction as the length side of the active area, and the dummy active area array block formed by the parallel arrangement of a plurality of dummy active areas spans the formation of the dummy active area Since there is field oxygen between each dummy active area of the dummy active area array block, it can form a good isolation for the active areas on both sides of the dummy active area array block, and can prevent the dummy active area itself. A leakage channel is formed so that leakage between MOS transistors in adjacent active regions can be reduced.

The dummy active region of the present invention can be obtained only by rotating the original dummy active region in the original layout by 90 degrees through logic operation in the mask tooling production stage, so the present invention also has the feature of simple process.

Description of drawings

The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments:

FIG. 1 is a layout of a dummy active region of a conventional MOS transistor;

FIG. 2 is a cross-sectional structural view along the length direction of the dummy active region corresponding to the mark 105a in FIG. 1;

FIG. 3 is a layout of a dummy active region of a MOS transistor according to an embodiment of the present invention.

Detailed ways

As shown in FIG. 3, it is the layout of the dummy active region 205 of the MOS transistor according to the embodiment of the present invention. In the structure of the dummy active region 205 of the MOS transistor according to the embodiment of the present invention, field oxygen is formed on the semiconductor substrate. Oxygen isolates the active region 201 .

A plurality of dummy active regions 205 isolated by the field oxygen are formed around the active region 201 . The formation area of the dummy active region 205 is shown as the dotted frame 202 . The field oxide shown typically employs Shallow Trench Isolation (STI).

Each of the dummy active regions 205 has a strip-shaped structure, and the length direction of the dummy active region 205 is parallel to the length direction of the active region 201 .

The length of the dummy active region 205 is smaller than the length of the active region 201 .

A plurality of dummy active area array blocks 206 are disposed along the length of the active area 201 , and each of the dummy active area array blocks 206 corresponds to an area segment along the length of the active area 201 .

For each of the dummy active area array blocks 206, along the width direction of the active area 201, the dummy active area array block 206 consists of a plurality of the dummy active areas 205 and the The field oxygens between the active regions 205 are alternately arranged, and a plurality of the field oxygens in the dummy active region array block 206 prevent the occurrence of passing through the dummy active regions at the periphery of the active region 201 205 to form a leakage channel, thereby reducing the leakage of the MOS transistor.

In the embodiment of the present invention, an N well 204 and a P well 203 are formed on the semiconductor substrate, and the junction depths of the N well 204 and the P well 203 are both greater than the depth of the field oxygen; The source region 201 consists of the N-well 204 or the P-well 203 in the field oxygen surround region.

The N well 204 includes an IO N well, and the P well 203 includes an IO P well.

The MOS transistor includes a gate structure, a channel region, a source region and a drain region, the channel region being located before the source and drain regions and covered by the gate structure.

The gate structure of the MOS transistor includes a gate dielectric layer and a gate conductive material layer stacked in sequence.

The gate structure of the MOS transistor adopts a high dielectric constant metal gate, the gate dielectric layer includes a high dielectric constant layer, an interface layer is formed at the bottom of the high dielectric constant layer, and the high dielectric constant layer is formed on the bottom of the high dielectric constant layer. The top includes a bottom barrier.

The gate conductive material layer adopts a metal gate, and has a work function layer between the metal gate and the bottom barrier layer.

The MOS transistors include NMOS and PMOS. The work function layer of the NMOS is an N-type work function layer, and the work function layer of the PMOS is a P-type work function layer. Usually, in the formation region of the NMOS, the P-type work function layer is removed; in the formation region of the PMOS, the N-type work function layer remains, that is, in the P-type work function layer The surface is also superimposed with an N-type work function layer.

The material of the N-type work function layer includes TiAl; the material of the P-type work function layer includes TiN.

Metal silicide is formed on the surface of the source region and the drain region; metal silicide is also formed on the surface of the dummy active region 205 . In some preferred embodiments, the material of the metal silicide includes NiSi.

The MOS transistor includes an LDMOS, and the LDMOS further includes a drift region located between the channel region and the drain region. The N-type LDMOS is LDNMOS, and the P-type LDMOS is LDPMOS.

A drift region field oxygen is also formed in the surface region of the drift region, and the depth of the drift region field oxygen is smaller than the depth of the field oxygen. The gate conductive material layer also extends onto the surface of the drift region field oxygen.

In FIG. 3 , the dummy active region overlapping the N-well 204 is denoted by reference numeral 205a alone. In the dummy active area array block 206 having the dummy active areas 205a, in the alternate arrangement direction of the dummy active areas 205a, there are a plurality of fields located between the dummy active areas 205a oxygen. Compared with FIG. 1 , under the condition that the length in the extending direction of the dummy active area array block 206 is the same as or even longer than the length of the dummy active area 105 in FIG. 1 , the dummy active area A plurality of the field oxygens in the active area array block 206 can achieve good isolation of the active areas 201 on both sides of the dummy active area array block 206, especially the difference between IO NW and IO PW can be achieved. The isolation between them can prevent leakage.

In the prior art, in the formation area of the dummy active area 205 around the active area 201, the length side of the active area 201 is perpendicular to the length side so that the length side of each dummy active area 205 spans the entire dummy active area. The formation area of 205 is different. In the embodiment of the present invention, the length sides of each dummy active area 205 are set to be in the same direction as the length sides of the active area 201, and the dummy active areas 205 are formed by arranging multiple dummy active areas in parallel. The area array block 206 spans the formation area of the dummy active area 205. Since there is field oxygen between the dummy active areas 205 of the dummy active area array block 206, the dummy active area array block 206 on both sides of the dummy active area array block 206 has field oxygen. The source region 201 forms a good isolation, which can prevent the dummy active region 205 from forming a leakage channel, thereby reducing the leakage between the MOS transistors in the adjacent active regions 201 .

The manufacturing method of the dummy active region 205 of the MOS transistor according to the embodiment of the present invention includes the following steps:

Step 1. Define an active area 201 and a dummy active area 205 on the layout at the same time, the dummy active area 205 is located around the active area 201, the active area 201 and the dummy active area The peripheral side of 205 is the formation area of field oxygen.

Each of the dummy active regions 205 has a strip-shaped structure, and the length direction of the dummy active region 205 is parallel to the length direction of the active region 201 .

The length of the dummy active region 205 is smaller than the length of the active region 201 .

A plurality of dummy active area array blocks 206 are disposed along the length of the active area 201 , and each of the dummy active area array blocks 206 corresponds to an area segment along the length of the active area 201 .

For each of the dummy active area array blocks 206, along the width direction of the active area 201, the dummy active area array block 206 consists of a plurality of the dummy active areas 205 and the The field oxygens between the source regions 205 are alternately arranged.

In the method according to the embodiment of the present invention, the method further includes providing an original layout, and the original layout is shown in FIG. 1 . The original layout includes an original dummy active area, the original dummy active area is located at the periphery of the active area 201 , and the length direction of the original dummy active area and the length direction of the active area 201 are vertical. The dummy active area 205 in the layout is obtained by rotating the original dummy active area in the original layout by 90 degrees.

In the stage of making a plate-making file, the original dummy active area in the original layout is rotated by 90 degrees through a logical operation to obtain the dummy active area 205 in the layout.

Step 2, using the layout to make a mask.

Step 3: Transfer the layout on the reticle to the semiconductor substrate by using a photolithography process, form the field oxygen on the semiconductor substrate, and isolate the active region 201 through the field oxygen and the dummy active region 205; a plurality of the field oxygens in the dummy active region array block 206 prevent the leakage channel formed by the dummy active region 205 from appearing in the periphery of the active region 201, Thereby, the leakage of the MOS transistor is reduced.

In the method of the embodiment of the present invention, an N-well 204 and a P-well 203 are formed on the semiconductor substrate, and the junction depths of the N-well 204 and the P-well 203 are both greater than the depth of the field oxygen; The active region 201 consists of the N-well 204 or the P-well 203 in the field-oxygen surround region.

The N well 204 includes an IO N well, and the P well 203 includes an IO P well.

Then, a MOS transistor is formed in the active region 201. When the MOS transistor adopts HKMG, it is usually necessary to use a polysilicon dummy gate, and a process of HK first and then MG is performed, and HK first represents the formation process of the high dielectric constant layer. Before the polysilicon dummy gate; Post MG indicates that the metal gate is formed after the polysilicon dummy gate. The steps of forming the MOS transistor include:

A dummy gate structure is formed on the structure of the active region 201 and the field oxygen, and the dummy gate structure includes an interface layer, a high dielectric constant layer, a bottom barrier layer and the polysilicon dummy gate stacked in sequence; The interface layer, the high dielectric constant layer, the bottom barrier layer and the polysilicon dummy gate are stacked to form the dummy gate structure.

Then, lightly drained doping implantation (LDD) is performed on the side of the dummy gate structure as a self-alignment condition to form an LDD region; sidewalls are formed on the side of the dummy gate structure, and the sidewall of the dummy gate structure is used to form an LDD region. The sidewalls on the side are self-aligned for source-drain implantation to form source-drain regions. An embedded epitaxial layer is usually introduced into the source and drain regions. The embedded epitaxial layer of PMOS is usually a silicon germanium epitaxial layer, and the embedded epitaxial layer of NMOS is usually a phosphorous silicon epitaxial layer. Then, source-drain implantation is performed to form source-drain regions on both sides of the dummy gate structure. ,

Then, the doping impurities in the source and drain regions are annealed and activated.

After that, metal silicide such as nickel silicide is formed on the surface of the source and drain regions of the active region, and the metal silicide is also formed on the surface of the dummy active region. The metal silicide includes NiSi.

Afterwards, a photoresist etch-back process is used to reduce the unevenness of the gate height; and the sidewall spacers are thinned.

Then, the method further includes forming a zeroth interlayer film, and performing a chemical mechanical polishing process to make the surface of the zeroth interlayer film and the top surface of the polysilicon dummy gate level.

After that, the polysilicon dummy gate is removed.

Then, an ALD process is used to prepare a P-type work function layer such as a TiN layer; the P-type work function layer in the NMOS formation region is removed; and an N-type work function layer such as a TiAl layer is formed.

After that, fill the gate conductive material layer such as Al; perform chemical mechanical polishing to remove excess metal Al, and control the gate height.

Afterwards, the contact holes and the back-end metal connections are made and annealed. Finally, a MOS device is formed.

The present invention has been described in detail above through specific embodiments, but these are not intended to limit the present invention. Without departing from the principles of the present invention, those skilled in the art can also make many modifications and improvements, which should also be regarded as the protection scope of the present invention.

Claims (15)

1. A structure of a dummy active region of a MOS transistor, characterized in that: forming field oxygen on the semiconductor substrate, wherein the field oxygen isolates an active region;

forming a plurality of dummy active regions isolated by the field oxide on the periphery of the active region;

each pseudo active region is of a strip structure, and the length direction of each pseudo active region is parallel to the length direction of each active region;

the length of the dummy active region is smaller than that of the active region;

a plurality of pseudo active area array blocks are arranged on the length edge of the active area, and each pseudo active area array block corresponds to one area section of the length edge of the active area;

for each pseudo active region array block, in the width direction of the active region, the pseudo active region array block is formed by alternately arranging a plurality of pseudo active regions and the field oxide positioned between the pseudo active regions, and the plurality of field oxides in the pseudo active region array block prevent a leakage channel formed by the pseudo active regions from occurring at the periphery of the active region, thereby reducing the leakage of the MOS transistor.

2. The structure of the dummy active region of the MOS transistor according to claim 1, wherein: forming an N well and a P well on the semiconductor substrate, wherein the junction depths of the N well and the P well are both greater than the depth of the field oxygen; each of the active regions is composed of the N-well or the P-well in the field oxide surrounding region.

3. The structure of the dummy active region of the MOS transistor according to claim 2, wherein: the N-well comprises an IO N-well and the P-well comprises an IO P-well.

4. The structure of the dummy active region of the MOS transistor according to claim 3, wherein: the MOS transistor comprises a gate structure, a channel region, a source region and a drain region, wherein the channel region is positioned in front of the source region and the drain region and is covered by the gate structure.

5. The structure of the dummy active region of the MOS transistor according to claim 4, wherein: the gate structure of the MOS transistor comprises a gate dielectric layer and a gate conductive material layer which are sequentially overlapped.

6. The structure of a dummy active region of a MOS transistor according to claim 5, wherein: the gate structure of the MOS transistor adopts a high-dielectric-constant metal gate, the gate dielectric layer comprises a high-dielectric-constant layer, an interface layer is formed at the bottom of the high-dielectric-constant layer, and the top of the high-dielectric layer comprises a bottom barrier layer;

the grid conductive material layer adopts a metal grid, and a work function layer is arranged between the metal grid and the bottom barrier layer.

7. The structure of the dummy active region of the MOS transistor according to claim 6, wherein: the MOS transistor comprises an NMOS and a PMOS;

the work function layer of the NMOS is an N-type work function layer, and the work function layer of the PMOS is a P-type work function layer.

8. The structure of the dummy active region of the MOS transistor according to claim 7, wherein: the material of the N-type work function layer comprises TiAl; the material of the P-type work function layer comprises TiN.

9. The structure of the dummy active region of the MOS transistor according to claim 4, wherein: forming metal silicide on the surfaces of the source region and the drain region; and forming metal silicide on the surface of the pseudo active region.

10. The structure of the dummy active region of the MOS transistor according to claim 9, wherein: the material of the metal silicide comprises NiSi.

11. The structure of the dummy active region of the MOS transistor according to claim 7, wherein: the MOS transistor comprises an LDMOS, and a drift region located between the channel region and the drain region.

12. The structure of the dummy active region of the MOS transistor according to claim 11, wherein: a drift region field oxide is further formed in the surface region of the drift region, and the depth of the drift region field oxide is smaller than that of the field oxide;

the gate conductive material layer also extends onto a surface of the drift region field oxide.

13. A method for manufacturing a pseudo active region of a MOS transistor is characterized by comprising the following steps:

step one, defining an active area and a pseudo active area on a layout at the same time, wherein the pseudo active area is positioned at the periphery of the active area, and the peripheral sides of the active area and the pseudo active area are formed with field oxide forming areas;

each pseudo active region is of a strip structure, and the length direction of each pseudo active region is parallel to the length direction of each active region;

the length of the dummy active region is smaller than that of the active region;

a plurality of pseudo active area array blocks are arranged on the length edge of the active area, and each pseudo active area array block corresponds to one area section of the length edge of the active area;

for each dummy active region array block, the dummy active region array block is formed by alternately arranging a plurality of dummy active regions and the field oxide between the dummy active regions in a width direction along the active regions;

secondly, manufacturing a mask plate by adopting the layout;

transferring the layout on the mask onto a semiconductor substrate by adopting a photoetching process, forming field oxygen on the semiconductor substrate, and isolating the active region and the pseudo active region by the field oxygen; the plurality of field oxides in the dummy active region array block prevents a leakage path formed through the dummy active region from occurring at the periphery of the active region, thereby reducing leakage of the MOS transistor.

14. A method of manufacturing a dummy active region of a MOS transistor according to claim 13, wherein: the method comprises the following steps that firstly, an original layout is further provided, the original layout comprises an original pseudo active region, the original pseudo active region is located on the periphery of the active region, and the length direction of the original pseudo active region is perpendicular to the length direction of the active region;

and rotating the original pseudo active region in the original layout by 90 degrees to obtain the pseudo active region in the layout.

15. The method of manufacturing a dummy active region of a MOS transistor according to claim 14, wherein: in the first step, in the manufacturing stage of the layout file, the original pseudo active region in the original layout is rotated by 90 degrees through logic operation to obtain the pseudo active region in the layout.

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