CN115117149B - Fast recovery diode based on wet etching process and preparation method thereof - Google Patents

Abstract

The application belongs to the technical field of power devices and provides a fast recovery diode based on a wet etching process and a preparation method thereof, wherein a photoresist is formed on the front surface of an N-type epitaxial layer, and a groove is formed on the front surface of the N-type epitaxial layer by adopting the wet etching process under the protection of the photoresist; then, injecting first P-type doped ions into the front surface of the N-type epitaxial layer to form a first P-type doped region at the bottom of the groove, and annealing after removing the photoresist; injecting second P-type doping ions with doping concentration smaller than that of the first P-type doping ions into the front surface of the N-type epitaxial layer to form second P-type doping regions on the side wall of the groove and the front surface of the N-type epitaxial layer, and annealing; and finally, an anode metal layer and a cathode metal layer are formed, and a high-concentration P junction and a lightly doped P junction are simultaneously prepared in the groove, so that the area of a shallow P region can be increased under the condition of not increasing the plane area, the IRM and VF of the diode can be reduced, and the softness of the diode is improved.

Description

A fast recovery diode based on wet etching process and its preparation method

technical field

The application belongs to the technical field of power devices, and in particular relates to a fast recovery diode based on a wet etching process and a preparation method thereof.

Background technique

Fast recovery diodes are usually formed by the epitaxy of the PIN structure. Under the application of global or local carrier lifetime control technology, the carrier lifetime is reduced, so that the diode has fast recovery characteristics. This type of diode is usually used in parallel with the IGBT. The peak current generated during the reverse recovery process of the diode usually increases the turn-on loss of the IGBT. If the epitaxial buffer layer is not well controlled, it will lead to lower softness and affect the gate voltage of the IGBT. Generally, the higher the forward turn-on voltage drop (VF) of the fast recovery diode controlled by the global carrier life is, the anode injection efficiency is low, the reverse peak current (IRM) is relatively small, and the impact on the IGBT is smaller, but the loss of the diode Increase.

However, in the current preparation process of fast recovery diodes, the Schottky barrier is low and does not meet the conditions for preparing high-voltage fast recovery diodes. In addition, by reducing the injection efficiency of the anode of the diode and reducing the concentration and depth of the P junction, But there is a problem that is not conducive to anti-surge current.

Contents of the invention

The purpose of the present application is to provide a fast recovery diode based on a wet etching process and its preparation method, aiming to solve the problem that the existing fast recovery diode cannot be compatible with high voltage and anti-surge current at the same time.

The first aspect of the embodiment of the present application provides a preparation method of a fast recovery diode, the preparation method comprising:

Forming a photoresist on the front side of the N-type epitaxial layer;

Under the protection of the photoresist, a groove is formed on the front surface of the N-type epitaxial layer by a wet etching process; wherein, the area of the groove is larger than the area of the etching hole on the photoresist;

Implanting first P-type dopant ions to the front of the N-type epitaxial layer under the protection of the photoresist to form a first P-type dopant region at the bottom of the groove, and removing the photoresist Post annealing treatment;

Implanting second P-type dopant ions into the front side of the N-type epitaxial layer to form a second P-type doped region on the sidewall of the groove and the front side of the N-type epitaxial layer, and annealing; wherein , the doping concentration of the second P-type doped region is less than the doping concentration of the first P-type doped region;

An anode metal layer is formed on the surface of the first P-type doped region, and a cathode metal layer is formed on the back of the N-type epitaxial layer.

In one embodiment, the thickness of the second P-type doped region is smaller than the thickness of the first P-type doped region.

In one embodiment, under the protection of the photoresist, the first P-type doping ions are implanted into the front surface of the N-type epitaxial layer to form a first P-type doping region at the bottom of the groove, And the steps of annealing after removing the photoresist include:

Implanting first P-type dopant ions into the groove through the etching hole on the photoresist at a first implantation angle; wherein, the first implantation angle is greater than 0 degrees and less than 30 degrees;

The photoresist is removed, and then annealed at a temperature of 1000-1200 degrees for 100-600 minutes.

In one embodiment, the implantation dose of the first P-type dopant ions into the groove is 3*10 ¹² -8*10 ¹³ .

In one embodiment, the implanting of second P-type dopant ions to the front surface of the N-type epitaxial layer forms a second P-type dopant ion on the sidewall of the groove and the front surface of the N-type epitaxial layer. heterogeneous regions, and the steps of annealing include:

Implanting second P-type dopant ions into the front of the N-type epitaxial layer to form a second P-type doped region on the sidewall of the groove and the front of the N-type epitaxial layer; wherein, the first The two P-type doped regions include a planar P-type doped region and an arc-shaped P-type doped region, the planar P-type doped region is located on both sides of the groove, and the arc-shaped P-type doped region located on the sidewall of the groove;

Annealing treatment at a temperature of 300° C. to 500° C. for 60 minutes to 600 minutes.

The second aspect of the embodiment of the present application also provides a fast recovery diode, including:

N-type epitaxial layer, the front side of the N-type epitaxial layer is provided with grooves;

The first P-type doped region is located at the bottom of the groove;

A planar P-type doped region is provided on both sides of the groove, and the thickness of the planar P-type doped region is smaller than the depth of the groove;

The arc-shaped P-type doped region is arranged on the sidewall of the groove; wherein, the doping concentration of the planar P-type doped region and the arc-shaped P-type doped region is lower than that of the first P The doping concentration of the type doping region;

a positive electrode metal layer disposed on the front side of the N-type epitaxial layer;

The cathode metal layer is arranged on the back side of the N-type epitaxial layer.

In one embodiment, the thickness of the planar P-type doped region and the arc-shaped P-type doped region is smaller than the thickness of the first P-type doped region.

In one embodiment, the implantation dose of the first P-type doped region is 3*10 ¹² -8*10 ¹³ .

In one embodiment, the width of the groove gradually increases from the bottom to the top.

In one embodiment, the sidewall of the groove is arc-shaped, and the cross-sectional area of the groove gradually increases from the bottom to the top.

The application provides a fast recovery diode based on a wet etching process and its preparation method. First, a photoresist is formed on the front side of the N-type epitaxial layer, and a wet etching process is used under the protection of the photoresist on the N-type epitaxial layer. The front of the N-type epitaxial layer forms a groove; then under the protection of the photoresist, the first P-type dopant ions are implanted into the front of the N-type epitaxial layer to form the first P-type doped region at the bottom of the groove, and after removing the light Annealing treatment after the resist; implanting the second P-type dopant ions with a doping concentration lower than the first P-type dopant ions to the front of the N-type epitaxial layer to form the first P-type dopant ions on the side walls of the groove and the front surface of the N-type epitaxial layer Two P-type doped regions, and annealing treatment; finally form the anode metal layer and cathode metal layer, by preparing high-concentration P junction and lightly doped P junction in the groove at the same time, not only can increase the surface area without increasing the plane area The area of the shallow P region can also reduce the IRM and VF of the diode and improve the softness of the diode.

Description of drawings

FIG. 1 is a schematic flowchart of a method for preparing a fast recovery diode provided in an embodiment of the present application.

FIG. 2 is an exemplary diagram of forming grooves on the front surface of the N-type epitaxial layer 100 provided by the embodiment of the present application.

FIG. 3 is an example diagram of forming the first P-type doped region 110 provided by the embodiment of the present application.

FIG. 4 is an exemplary diagram of forming the second P-type doped region 120 provided by the embodiment of the present application.

FIG. 5 is an example diagram of forming a fast recovery diode provided by an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application.

It should be noted that when an element is referred to as being “fixed” or “disposed on” another element, it may be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

It is to be understood that the terms "length", "width", "top", "bottom", "front", "rear", "left", "right", "vertical", "horizontal", "top" , "bottom", "inner", "outer" and other indicated orientations or positional relationships are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the application and simplifying the description, rather than indicating or implying the referred device Or elements must have a certain orientation, be constructed and operate in a certain orientation, and thus should not be construed as limiting the application.

In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the present application, "plurality" means two or more, unless otherwise specifically defined.

Fast recovery diodes usually have the epitaxial structure of PIN structure. Under the application of global or local carrier lifetime control technology, the carrier lifetime is reduced, so that the diode has the characteristics of fast recovery. This type of diode is usually used in parallel with the IGBT. The peak current generated during the reverse recovery process of the diode usually increases the turn-on loss of the IGBT. If the buffer layer is not well controlled, it will lead to low softness and affect the gate voltage of the IGBT. Generally, the higher the forward turn-on voltage drop VF of the fast recovery diode with global carrier lifetime control is, the lower the anode injection efficiency is, and the reverse peak current IRM is relatively small, and the impact on the IGBT is smaller, but the loss of the diode increases.

In order to obtain a fast recovery diode with low VF, high softness, and low IRM, the N-silicon in the drift region with a withstand voltage of 1200V or higher obtained by epitaxy is etched in the embodiment of the present application by wet chemical method, and the photoresist is etched Under the mask, perform local implantation of P junction enrichment to the photolithographic opening, then remove the photoresist and anneal to push the junction, and then implant lightly doped P junction implantation into the active region again. Since the arc-shaped structure is prepared by the wet chemical method, the enriched P-junction after annealing only partially occupies the bottom of the arc, and the secondary light P-junction doping covers all arcs and planes. The PN junction with high-concentration P junction and light P junction structure can be prepared, and the P junction with moderate anode injection efficiency can be obtained by adjusting the amount of corrosion. Under the application of global carrier lifetime control technology, it can achieve low VF, low IRM, purpose of high softness fast recovery diodes.

An embodiment of the present application provides a method for manufacturing a fast recovery diode based on a wet etching process. Referring to FIG. 1 , the method for manufacturing in this embodiment includes steps S100 to S500.

In step S100 , a photoresist is formed on the front surface of the N-type epitaxial layer 100 .

In this embodiment, as shown in FIG. 2, a photoresist 200 is spin-coated on the front side of the N-type epitaxial layer 100, and then a photolithographic development process is performed to obtain a photolithographic pattern with an etching hole on the photoresist film, which is A subsequent wet etching process provides an etched pattern.

In step S200, under the protection of the photoresist, a groove is formed on the front surface of the N-type epitaxial layer by using a wet etching process.

In this embodiment, as shown in FIG. 2, a wet etching process is performed on the front side of the N-type epitaxial layer 100 under the protection of the photoresist 200. The exposed part of the front side of the epitaxial layer 100 is etched, so as to form a groove 301 on the front side of the N-type epitaxial layer 100 .

In a specific application embodiment, the N-type epitaxial layer 100 may be an N-type silicon layer, and the etching solution may be hydrofluoric acid.

In a specific application embodiment, the position of the groove 301 is located directly below the etching hole, and since the groove 301 is prepared by a wet etching process, the area of the groove 301 is larger than that of the etching on the photoresist 200. The area of the hole.

In a specific application embodiment, the sidewall of the groove 302 is arc-shaped, and the cross-sectional area of the groove 302 gradually increases from the bottom to the top.

In a specific application embodiment, the bottom area of the groove 301 is opposite to the position of the etching hole, and the sidewall of the groove 301 is located below the photoresist 200. As shown in FIG. 2 , the sidewall of the groove 301 is vertically direction is covered by photoresist 200 .

In step S300, under the protection of the photoresist, the first P-type doping ions are implanted into the front surface of the N-type epitaxial layer to form a first P-type doping region at the bottom of the groove, and after removing The photoresist is post-annealed.

In this embodiment, the first P-type dopant ions are implanted into the front surface of the N-type epitaxial layer 100 under the protection of the photoresist 200. Due to the cover of the photoresist 200, the first P-type dopant ions are mainly implanted into the concave The bottom region of the groove 301, thereby forming the first P-type doped region 110 at the bottom of the groove 301, and the P-type junction at the bottom of the groove 301 is advanced by annealing treatment, so that the P-type junction expands outwards. At this time, The P-type junction covers the bottom area of the groove 301 , and the sidewall of the groove 301 remains an N-type epitaxial layer, as shown in FIG. 3 .

In one embodiment, in step S300, the first P-type dopant ions are implanted into the front surface of the N-type epitaxial layer under the protection of the photoresist to form a first P-type dopant ion at the bottom of the groove. region, and the step of annealing after removing the photoresist includes step S310 and step S320.

In step S310, first P-type dopant ions are implanted into the groove through the etching hole on the photoresist at a first implantation angle.

In this embodiment, the first implantation angle can be a small implantation angle, for example, the first implantation angle is greater than 0 degrees and less than 30 degrees, so that the first P-type dopant ions are implanted into the etching hole of the photoresist 200. below.

In a specific application embodiment, the first P-type dopant ions may be boron ions or aluminum ions.

In one embodiment, the implantation dose of the first P-type dopant ions implanted into the groove 301 may be 3*10 ¹² -8*10 ¹³ .

In step S320, the photoresist is removed, and then annealed at a temperature of 1000-1200 degrees for 100-600 minutes.

In this embodiment, after removing the photoresist 200, the device implanted with the first P-type dopant ions is annealed at a temperature of 1000-1200 degrees for 100-600 minutes to further promote the first P-type doping The P-type junction of the region 110 is deep, so that the P-type junction of the first P-type doped region 110 expands outwards, the P-type junction covers the arc bottom region of the groove 301, and the doping type of the sidewall of the groove 301 remains It is N type.

In a specific application example, as shown in FIG. 3 , the first P-type doped region 110 formed after annealing is arc-shaped, and the arc-shaped gap wraps the bottom of the groove 301 . The first P-type doped region 110 formed after annealing The P-type doped region 110 is due to the diffusion of P-type doped ions. At this time, the cross-sectional area of the first P-type doped region 110 gradually increases from the bottom of the groove 301 to the back of the N-type epitaxial layer 100, and then gradually decreases. , the effect of increasing the junction area between the first P-type doped region 110 and the N-type epitaxial layer 100 can be achieved.

In step S400, implanting second P-type dopant ions into the front side of the N-type epitaxial layer to form a second P-type doped region on the sidewall of the groove and the front side of the N-type epitaxial layer, and annealed.

In this embodiment, after the photoresist 200 is removed, the second P-type dopant ions are implanted into the front surface of the N-type epitaxial layer 100. Since there is no cover of the photoresist 200, the second P-type dopant ions are implanted at this time. To the entire front surface of the N-type epitaxial layer 100 , a second P-type doped region 120 is formed on the entire front surface of the N-type epitaxial layer 100 .

In a specific application embodiment, the doping concentration of the second P-type doped region 120 is lower than the doping concentration of the first P-type doped region 110. At this time, the entire front surface of the N-type epitaxial layer 100 can have a shallow P-type structure, and by implanting the second P-type dopant ions on the entire front surface of the N-type epitaxial layer 100, the first P-type dopant region 110, which is a deep P-type region, can be enriched with P-type dopant ions.

In one embodiment, the first P-type doped region 110 is formed by implanting the first P-type dopant ions into the bottom of the front groove of the N-type epitaxial layer 100 using a high-dose implantation process, and the second P-type doped region 120 is formed by using The low-dose high-energy implantation process implants the second P-type dopant ions into the front side of the N-type epitaxial layer 100 to form.

In a specific application embodiment, the implantation dose of the high-dose implantation process may be 3*10 ¹² -8*10 ¹³ , which is at least 10 times the implantation dose of the low-dose high-energy implantation process.

In one embodiment, in step S400, second P-type dopant ions are implanted into the front surface of the N-type epitaxial layer to form a second P-type dopant on the sidewall of the groove and the front surface of the N-type epitaxial layer. type doped region, and the step of annealing includes step S410 and step S420.

In step S410 , implanting second P-type dopant ions into the front side of the N-type epitaxial layer to form a second P-type doped region on the sidewall of the groove and the front side of the N-type epitaxial layer.

In this embodiment, as shown in FIG. 4, the second P-type doped region 120 includes a planar P-type doped region 122 and an arc-shaped P-type doped region 121, and the planar P-type doped region 122 is located in the groove 301. On both sides of the groove 301 , the arc-shaped P-type doped region 121 is located on the sidewall of the groove 301 .

In step S420 , annealing is performed at a temperature of 300° C.-500° C. for 60 minutes-600 minutes.

In this embodiment, after implanting the second P-type dopant ions into the front surface of the N-type epitaxial layer 100, the dopant ions are activated by low-temperature annealing. For example, the annealing temperature can be 300°C-500°C, and the annealing time can be 60 minutes - 600 minutes.

In one embodiment, as shown in FIG. 4 , the thickness of the second P-type doped region 120 is smaller than the thickness of the first P-type doped region 110 .

In this embodiment, since the sidewall of the groove 301 is arc-shaped, the arc-shaped P-type doped region 121 is located on the sidewall of the groove 301, and is connected to the planar P-type doped region 122 and the first P-type doped region. Between the doped regions 110, the area of the shallow P region (namely the first P-type doped region 110) can be increased without increasing the planar area due to the existence of the arc sidewall of the groove 301. The utilization rate of the silicon surface is improved, the anode injection efficiency is generally reduced, the surface (plane plus arc surface) current density is unchanged, but the plane current density is increased, so as to achieve low IRM, Low VF, high soft fast recovery diode.

In step S500, an anode metal layer is formed on the surface of the first P-type doped region, and a cathode metal layer is formed on the back of the N-type epitaxial layer.

In this embodiment, as shown in FIG. 5 , by forming an anode metal layer 410 on the surface of the first P-type doped region 110, and then forming a cathode metal layer 420 on the back of the N-type epitaxial layer 100, the fast recovery diode is completed. preparation.

The embodiment of the present application also provides a fast recovery diode, which is prepared based on a wet etching process. In a specific application, the preparation method described in any one of the above embodiments can be used to prepare the fast recovery diode.

In one embodiment, as shown in FIG. 5 , the fast recovery diode includes: an N-type epitaxial layer 100, a first P-type doped region 110, a planar P-type doped region 122, an arc-shaped P-type doped region 121, Positive electrode metal layer 410 , cathode metal layer 420 .

Specifically, the front of the N-type epitaxial layer 100 is provided with a groove; the first P-type doped region 110 is arranged at the bottom of the groove on the front of the N-type epitaxial layer 100; the planar P-type doped region 122 is arranged on the N-type epitaxial layer On both sides of the groove on the front of the 100, and the thickness of the planar P-type doped region 122 is less than the depth of the groove; the arc-shaped P-type doped region 121 is arranged on the sidewall of the groove on the front of the N-type epitaxial layer 100, and the positive electrode The metal layer 410 is disposed on the front side of the N-type epitaxial layer 100 ; the cathode metal layer 420 is disposed on the back side of the N-type epitaxial layer 100 .

In this embodiment, the planar P-type doped region 122 and the arc-shaped P-type doped region 121 form the second P-type doped region 120, and the planar P-type doped region 122 and the arc-shaped P-type doped region 121 The doping concentration is less than that of the first P-type doping region 110, the planar P-type doping region 122 is located on both sides of the groove 301, and the arc-shaped P-type doping region 121 is located on the sidewall of the groove 301.

In a specific embodiment, the annealing temperature of the first P-type doped region 110 is at least twice the annealing temperature of the second P-type doped region 120 .

In one embodiment, the thickness of the second P-type doped region 120 is smaller than the thickness of the first P-type doped region 110 .

In one embodiment, as shown in FIG. 5 , the thicknesses of the planar P-type doped region 122 and the arc-shaped P-type doped region 121 are smaller than the thickness of the first P-type doped region 110 .

In one embodiment, the implantation dose of the first P-type dopant ions in the first P-type doped region 110 is 3*10 ¹² -8*10 ¹³ .

In one embodiment, the first P-type doped region 110 is formed by implanting the first P-type dopant ions into the bottom of the front groove of the N-type epitaxial layer 100 using a high-dose implantation process, and the second P-type doped region 120 is formed by using The low-dose high-energy implantation process implants the second P-type dopant ions into the front side of the N-type epitaxial layer 100 to form.

In a specific application embodiment, the implantation dose of the high-dose implantation process may be 3*10 ¹² -8*10 ¹³ , which is at least 10 times the implantation dose of the low-dose high-energy implantation process.

In one embodiment, the doping concentration of the first P-type doped region 110 is at least 10 times that of the second P-type doped region 120 .

In one embodiment, the width of the groove on the front side of the N-type epitaxial layer 100 gradually increases from the bottom to the top.

In a specific application embodiment, the sidewall of the groove 302 is arc-shaped, and the cross-sectional area of the groove 302 gradually increases from the bottom to the top.

The embodiment of the present application also provides a chip, including the fast recovery diode described in any one of the above embodiments; or the fast recovery diode prepared by the preparation method described in any one of the above embodiments.

The application provides a fast recovery diode based on a wet etching process and its preparation method. First, a photoresist is formed on the front side of the N-type epitaxial layer, and a wet etching process is used under the protection of the photoresist on the N-type epitaxial layer. The front of the N-type epitaxial layer forms a groove; then under the protection of the photoresist, the first P-type dopant ions are implanted into the front of the N-type epitaxial layer to form the first P-type doped region at the bottom of the groove, and after removing the light Annealing treatment after the resist; implanting the second P-type dopant ions with a doping concentration lower than the first P-type dopant ions to the front of the N-type epitaxial layer to form the first P-type dopant ions on the side walls of the groove and the front surface of the N-type epitaxial layer Two P-type doped regions, and annealing treatment; finally form the anode metal layer and cathode metal layer, by preparing high-concentration P junction and lightly doped P junction in the groove at the same time, not only can increase the surface area without increasing the plane area The area of the shallow P region can also reduce the IRM and VF of the diode and improve the softness of the diode.

Those skilled in the art can clearly understand that for the convenience and brevity of description, only the division of the above-mentioned doped regions is used as an example. In practical applications, the above-mentioned functional regions can be assigned to different doped regions according to needs. Completion means that the internal structure of the device is divided into different doped regions, so as to complete all or part of the functions described above.

Each doped region in the embodiment can be integrated in one functional region, or each doped region can exist separately physically, or two or more doped regions can be integrated in one functional region. The above-mentioned integrated functional region It can be realized by using the same kind of dopant ions, and can also be realized by using multiple dopant ions together. In addition, the specific names of the doped regions are only for the convenience of distinguishing each other, and are not used to limit the protection scope of the present application. For the specific working process of the medium-doped region in the above-mentioned device manufacturing method, reference may be made to the corresponding process in the foregoing method embodiments, and details will not be repeated here.

The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still implement the foregoing embodiments Modifications to the technical solutions described in the examples, or equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the application, and should be included in the Within the protection scope of this application.

Claims (10)

1. a preparation method of fast recovery diode, is characterized in that, described preparation method comprises: Forming a photoresist on the front side of the N-type epitaxial layer; Under the protection of the photoresist, a groove is formed on the front surface of the N-type epitaxial layer by a wet etching process; wherein, the area of the groove is larger than the area of the etching hole on the photoresist; The side wall of the groove is set in an arc shape; Implanting first P-type dopant ions to the front of the N-type epitaxial layer under the protection of the photoresist to form a first P-type dopant region at the bottom of the groove, and removing the photoresist Post-annealing treatment; Implanting second P-type dopant ions into the front side of the N-type epitaxial layer to form a second P-type doped region on the sidewall of the groove and the front side of the N-type epitaxial layer, and annealing; wherein , the doping concentration of the second P-type doped region is less than the doping concentration of the first P-type doped region; both the first P-type doped region and the second P-type doped region are Arc shape; An anode metal layer is formed on the surface of the first P-type doped region, and a cathode metal layer is formed on the back of the N-type epitaxial layer. 2. The preparation method according to claim 1, wherein the thickness of the second P-type doped region is smaller than the thickness of the first P-type doped region. 3. The preparation method according to claim 1, characterized in that, under the protection of the photoresist, the first P-type dopant ions are implanted into the front side of the N-type epitaxial layer to form a gap in the groove. The step of forming a first P-type doped region at the bottom, and annealing after removing the photoresist includes: Implanting first P-type dopant ions into the groove through the etching hole on the photoresist at a first implantation angle; wherein, the first implantation angle is greater than 0 degrees and less than 30 degrees; The photoresist is removed, and then annealed at a temperature of 1000° C.-1200° C. for 100-600 minutes. 4 . The manufacturing method according to claim 3 , wherein the implantation dose of the first P-type dopant ions into the groove is 3*10 ¹² -8*10 ¹³ . 5. The preparation method according to claim 1, wherein the second P-type dopant ions are implanted into the front side of the N-type epitaxial layer, so as to inject a second P-type dopant ion on the sidewall of the groove and the N-type epitaxial layer. A second P-type doped region is formed on the front side of the epitaxial layer, and the steps of annealing include: Implanting second P-type dopant ions into the front of the N-type epitaxial layer to form a second P-type doped region on the sidewall of the groove and the front of the N-type epitaxial layer; wherein, the first The two P-type doped regions include a planar P-type doped region and an arc-shaped P-type doped region, the planar P-type doped region is located on both sides of the groove, and the arc-shaped P-type doped region located on the sidewall of the groove; Annealing treatment at a temperature of 300° C. to 500° C. for 60 minutes to 600 minutes. 6. A fast recovery diode, characterized in that, comprising: N-type epitaxial layer, the front side of the N-type epitaxial layer is provided with grooves; The first P-type doped region is arranged at the bottom of the groove; the sidewall of the groove is arranged in an arc shape; A planar P-type doped region is provided on both sides of the groove, and the thickness of the planar P-type doped region is smaller than the depth of the groove; The arc-shaped P-type doped region is arranged on the sidewall of the groove; wherein, the doping concentration of the planar P-type doped region and the arc-shaped P-type doped region is lower than that of the first P The doping concentration of the type doped region; the planar P-type doped region and the arc-shaped P-type doped region form the second P-type doped region, and the first P-type doped region is arc-shaped ; a positive electrode metal layer disposed on the front side of the N-type epitaxial layer; The cathode metal layer is arranged on the back side of the N-type epitaxial layer; wherein, the fast recovery diode is prepared by the preparation method described in any one of claims 1-5. 7. The fast recovery diode according to claim 6, wherein the thickness of the planar P-type doped region and the arc-shaped P-type doped region is smaller than the thickness of the first P-type doped region . 8 . The fast recovery diode according to claim 6 , wherein the implantation dose of the first P-type doped region is 3*10 ¹² -8*10 ¹³ . 9. The fast recovery diode according to claim 6, wherein the width of the groove gradually increases from the bottom to the top. 10. The fast recovery diode according to claim 6, wherein the sidewall of the groove is arc-shaped, and the cross-sectional area of the groove gradually increases from the bottom to the top.

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