CN115134541B - A high dynamic CMOS image sensor with high and low gain and logarithmic response and a timing control method and a reading method - Google Patents
A high dynamic CMOS image sensor with high and low gain and logarithmic response and a timing control method and a reading method Download PDFInfo
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Abstract
一种同时具有高低增益和对数响应的高动态CMOS图像传感器及时序控制方法和读取方式，属于半导体光电方向图像传感器领域。本发明利用了在不同光强下电荷补偿元件分别工作在截止区和亚阈值区的原理：弱光和强光下电荷补偿元件处于截止区，无导通电流，此时本发明的像素结构与具有高低增益结构的高动态像素技术功能相同，因此在弱光下具有很强的探测能力；在超强光或者长积分时间下电荷补偿元件工作在亚阈值区，利用亚阈值区晶体管电流电压为对数关系的特性实现对过溢光生电荷的补偿，因此可在超高光强下成像。本发明在一次曝光下可以获得多幅相同积分时间的图像，对应弱光、强光和超强光，多幅图像即可合成一幅具有超高动态范围的图像。
A high-dynamic CMOS image sensor with both high and low gain and logarithmic response and a timing control method and a reading method, belonging to the field of semiconductor photoelectric directional image sensors. The present invention utilizes the principle that the charge compensation element works in the cut-off region and the subthreshold region respectively under different light intensities: the charge compensation element is in the cut-off region under weak light and strong light, and there is no conduction current. At this time, the pixel structure of the present invention has the same function as the high-dynamic pixel technology with high and low gain structure, so it has a strong detection capability under weak light; under ultra-strong light or long integration time, the charge compensation element works in the subthreshold region, and the characteristic that the current and voltage of the transistor in the subthreshold region are in a logarithmic relationship is used to achieve compensation for the overflow photogenerated charge, so imaging can be achieved under ultra-high light intensity. The present invention can obtain multiple images with the same integration time under one exposure, corresponding to weak light, strong light and ultra-strong light, and multiple images can be synthesized into an image with an ultra-high dynamic range.
Description
Technical Field
The invention belongs to the field of semiconductor photoelectric direction image sensors, and particularly relates to a high-dynamic CMOS image sensor with high-low gain and logarithmic response, a time sequence control method and a reading mode corresponding to the high-dynamic CMOS image sensor.
Background
The dynamic range is an important index for evaluating the CMOS image sensor, and represents the range of the maximum light intensity signal and the minimum light intensity signal which can be detected by the CMOS image sensor in the same frame of image at the same time, and the larger the dynamic range is, the higher the gray level detail level of the obtained image is. With the continuous development of integrated circuit technology, CMOS image sensors have been widely used in the field of image sensing. The dynamic range of the common CMOS image sensor can only reach 60-70 dB, however, in the fields of automobile imaging, security monitoring, military, automatic optical detection and the like, the range of ambient light can reach more than 100dB, and the common CMOS image sensor cannot meet the imaging requirement of an actual scene.
A widely used high-dynamic CMOS image sensor employs a pixel structure having a high-low gain, as shown in fig. 1. The pixel structure consists of a clamping photodiode 1, a charge transfer control transistor 2, a reset transistor 3, a high dynamic range transistor 4, a source follower 5 and a row selection transistor 6, wherein 2-6 are standard NMOS transistors. The operation sequence is shown in fig. 2, the transistors 2, 3 and 4 are all turned on once, then the pixel enters an integration stage, and then the FD point is reset once before the integration is finished, the low gain reset value rst_l and the high gain reset value rst_h are respectively read, then the integration is finished, the charge transfer control transistor 2 is turned on, the photo-generated charge generated by the clamping photodiode 1 is transferred to the FD point to obtain the high gain signal voltage sig_h, and then the charge transfer control transistor 2 and the high dynamic range transistor 4 are turned on simultaneously, and the low gain signal value sig_l is read. During the on period of the high dynamic range transistor 4, the FD point is connected to the FDL point, which corresponds to increasing the capacitance of the FD point, and can accommodate more photo-generated charges from the clamp photodiode 1, thereby improving the dynamic range of the pixel. The method for respectively obtaining high gain and low gain through twice charge transfer can enlarge the dynamic range of the pixel by 20-30 dB, so that the total dynamic range is close to or reaches 90dB.
The high dynamic pixel with high-low gain structure, although the dynamic range is improved by two charge transfer, the clamping photodiode has limited well capacity due to the limitation of pixel area and filling ratio, and when the light intensity is too strong or the integration time is longer, the clamping photodiode reaches full well in the integration time, and more charges cannot be accommodated, so that the dynamic range of the image sensor is limited.
In addition, the method also adopts a mode of expanding dynamic range by adopting a multistage transverse overflow gate, a double photodiode, a logarithmic mode of diode connection and the like, and has the defects of large capacitance, complex circuit structure, large pixel area, inapplicability to a large area array image sensor, large dark current, poor signal to noise ratio and the like which are manufactured by a special process.
Disclosure of Invention
The invention relates to a high dynamic CMOS image sensor with high and low gain and logarithmic response, and a corresponding time sequence control method and a corresponding reading mode. The invention aims to additionally perform ion implantation on a reset transistor and a high dynamic range transistor based on a traditional high dynamic pixel structure based on high and low gains, adjust the threshold voltages of the two NMOS transistors to be lower than a normal value, and jointly form the charge compensation element provided by the invention. The charge compensation element works in a subthreshold region under super-strong illumination or in an ultra-long integration time, and can inject charges into the FD point to compensate photo-generated charges overflowed to the FD point by the clamping photodiode, so that signal saturation caused by the fact that the clamping photodiode reaches a full trap is avoided, and the dynamic range is expanded. The invention utilizes the principle that the charge compensation element respectively works in a cut-off region and a subthreshold region under different light intensities, namely, under certain integration time (such as 10 ms), the charge compensation element is in the cut-off region under weak light (0.0001 lux to 0.1 lux) and strong light (0.1 lux to 10 lux), and has no conducting current, at the moment, the pixel structure of the invention has the same technical function as a high-dynamic pixel with a high-low gain structure, thus having strong detectability under weak light, the charge compensation element works in the subthreshold region under super light (exceeding 10 lux), and the compensation of photo-generated charges is realized by utilizing the characteristic that the transistor current voltage in the subthreshold region is in logarithmic relation, thus being capable of imaging under super light intensity. The invention can obtain a plurality of images with the same integration time under one exposure, and the images can be combined into an image with ultra-high dynamic range corresponding to weak light, strong light and super strong light. The invention also uses the principle that the charge compensation element works in the cut-off area and the subthreshold area respectively under different integration time, when the pixel structure is under a certain light intensity (such as 10 lux), when the integration time is very short (such as 100 mu s), the charge compensation element is in the cut-off area and has no conducting current, at the moment, the pixel structure is the same as the technical function, so that the invention has strong imaging capability when the integration time is relatively short under a certain light intensity, when the integration time is very long (such as 10 ms), the clamping photodiode reaches the full trap, the charge compensation element works in the subthreshold area, and the compensation of the photo-generated charge is realized by utilizing the characteristic that the current voltage of the transistor in the subthreshold area is in a logarithmic relation. At this time, the output signal is proportional to the logarithm of the light intensity, irrespective of the integration time.
The technical scheme of the invention is as follows:
A high dynamic CMOS image sensor having both high and low gain and logarithmic response is constructed as shown in FIG. 3. The pixel structure comprises a clamp photodiode 1, a charge transfer control transistor 2, a novel reset transistor 7, a novel high dynamic range transistor 8, a source follower 5 and a row select transistor 6. The novel reset transistor 7 and the novel high dynamic range transistor 8 together form a charge compensation element 9 according to the invention.
The clamp photodiode 1 is used as a photodetector element, and can convert a received optical signal into an electrical signal and accumulate photo-generated charges, and the P-terminal GND of the clamp photodiode 1 and the N-terminal source of the charge transfer control transistor 2 are connected. The charge transfer control transistor 2 is used to transfer the photo-generated charge accumulated in the clamp photodiode 1 to the FD point, and the control signal TX of the gate of the charge transfer control transistor 2 is from the row control module in the image sensor system, and the drain is connected to the FD point. The charge compensation element 9 comprises a novel reset transistor 7 and a novel high dynamic range transistor 8, wherein the drain electrode of the novel reset transistor 7 is connected with the Vpix potential, the source electrode is connected to the drain electrode of the novel high dynamic range transistor 8, and the source electrode of the novel high dynamic range transistor 8 is connected to the FD point. The gate control signals RST and HDR of the charge compensation element 9, which is jointly formed by the novel reset transistor 7 and the novel high dynamic range transistor 8, come from a row control module, and the element works in a cut-off region under weak light and strong light, and works in a subthreshold region under super strong light or super long integration time, so as to increase the dynamic range of the image sensor. The source follower 5 and the row selection transistor 6 are used for outputting pixel signals to a subsequent readout circuit, the gate of the source follower 5 is connected to the FD point, the drain is connected to VDD, and the source is connected to the drain of the row selection transistor 6. The control signal SEL at the gate terminal of the row select transistor 6 comes from a row control block, and the source is connected to the column bus for outputting the signal value of the pixel to a subsequent readout circuit of the image sensor system.
The charge transfer control transistor 2, the source follower 5 and the row select transistor 6 are all fabricated using standard NMOS transistor processes.
The novel reset transistor 7 and the novel high dynamic range transistor 8 are subjected to one additional ion implantation based on a standard process and are used for adjusting the threshold voltage of the transistors to be lower than a normal value, so that the two transistors together form the charge compensation element 9. The element works in a subthreshold region under ultra-strong light or long-time integration, and can inject charges to the FD point to compensate photo-generated charges overflowed to the FD point by the clamping photodiode 1, so that signal saturation caused by the fact that the clamping photodiode reaches a full trap is avoided. The characteristic that the current and the voltage of the transistor in the subthreshold region are in logarithmic relation is utilized, so that logarithmic response is obtained on the basis of linear response of weak light and strong light, and the dynamic range of the image sensor is greatly expanded.
A timing control method and a reading mode of a high dynamic CMOS image sensor with high-low gain and logarithmic response are shown in FIG. 4, and the specific steps are as follows:
And step one, resetting operation.
First, the pixel enters a reset state, the charge transfer control transistor 2 and the charge compensation element 9 are turned on simultaneously once, the charge in the clamp photodiode 1 is cleared, and the FD point voltage is reset to Vpix.
And step two, integrating operation.
After the reset operation is finished, the gate control signal voltages of the charge transfer control transistor 2 and the charge compensation element 9 drop to VTXL and VRL, respectively, the pixel enters an integration stage, and the accumulation of photo-generated charge starts in the clamp photodiode 1.
1) When the exposure time is not long enough under weak light or strong light, the photo-generated charge generated in the clamp photodiode 1 is less than or equal to the full-well capacity of the clamp photodiode 1, and all photo-generated charge is accumulated in the clamp photodiode 1, and no excessive photo-generated charge flows to the FD point through the charge transfer control transistor 2, so that the FD point voltage does not change during the integration time. The gate-source voltage V GS of the charge compensation element 9 is much smaller than the threshold voltage, so that the charge compensation element 9 operates in the off-region and no current flows to the FD point.
2) With the increase of the light intensity or the extension of the integration time, the photo-generated charge accumulated in the clamping photodiode 1 during the integration process exceeds the full well capacity of the photo-generated charge, and the redundant photo-generated charge flows to the FD point through the charge transfer control transistor 2 to form an over-current I OV which is equal to the photo-generated current I ph generated by the clamping photodiode 1,
IOV＝Iph＝ηRPin
Wherein eta, R, P in are respectively the quantum efficiency, the response rate and the incident light power of the clamping photodiode 1, the current causes the voltage of the FD point to drop, the voltage change value DeltaV FD is in direct proportion to the integral time t,
ΔVFD＝ηRPin·t
Since the light intensity is not large enough at this time, the photo-generated charge flowing to the FD point is limited within a certain integration time, the voltage of the FD point is not reduced much, both transistors in the charge compensation element 9 are in the off state, and the working state is not changed. This is reflected in the fact that the FD point voltage varies in proportion to the light intensity. The voltage value of FD is read out as a linear signal value log_s1 in logarithmic mode through the source follower 5, the row select transistor 6, and the subsequent circuit.
3) When the light intensity is too strong or the integration time is long, the photo-generated charge accumulated in the clamp photodiode 1 far exceeds the full well capacity of itself, and the excessive photo-generated charge flows to the FD point through the charge transfer control transistor 2 and accumulates at the FD point, generating a continuous photo-generated excessive current I OV, causing the FD point voltage to continuously drop, so that V GS of the charge compensation element 9 continuously increases. Since the transistor inside the charge compensation element 9 is subjected to an additional ion implantation on the basis of standard processes, the threshold voltage is lower than normal, and the V GS value approaches the threshold voltage, so that the charge compensation element 9 enters the subthreshold operation region from the cut-off region, and a current flows from Vpix to the FD point. This current can cancel the excessive current I OV flowing from the clamp photodiode 1 to the FD point, and is therefore referred to as the charge compensation current I C. If the light intensity is strong enough or the integration time is long enough, the photo-generated over-current I OV and the charge compensation current I C reach an equilibrium state, the FD point voltage will not change with the integration time any more. At this time, the charge compensation element 9 operates in the subthreshold region, and the charge compensation current I C has the following formula:
Where I S is a constant having a current dimension, V RST is a gate voltage of the charge compensation element 9, V FD is a voltage of the FD point, V TH is a threshold voltage of the charge compensation element 9, m is a subthreshold slope factor, and V T is a thermal voltage.
After balancing, the charge compensation current is equal to the photo-generated over-current,
IOV＝IC＝ηRPin
The expression V FD can be derived:
as can be seen from the above equation, the voltage change at FD point is proportional to the logarithm of the incident light intensity. This voltage can be read out by the source follower 5, the row select transistor 6 and the subsequent circuits as a signal value log_s2 in logarithmic mode.
Before integration is finished, the FD point is reset once, the novel reset transistor 7 and the novel high dynamic range transistor 8 in the charge compensation element 9 are respectively turned on, when the gate control signal HDR of the novel high dynamic range transistor 8 is at a high level VHDRH, the FD point voltage is used as a reset value rst_l of low gain and can be read out by the source follower 5, the row selection transistor 6 and the subsequent circuit, then the HDR signal voltage is dropped to VRL, and the FD point voltage is used as a reset value rst_h of high gain and can be read out by the source follower 5, the row selection transistor 6 and the subsequent circuit. The integration phase of the pixel circuit ends.
And step three, a first charge transfer process.
First, the charge transfer control transistor 2 is turned on, and the photo-generated charge accumulated in the clamp photodiode 1 is transferred to the FD point by the charge transfer control transistor 2 by the potential difference. At this time, the high gain signal value sig_h of the FD point is read, and the voltage can be read out through the source follower 5, the row selection transistor 6, and the subsequent circuits.
And step four, a second charge transfer process.
After the first charge transfer, the novel high dynamic range transistor 8 is turned on, the FD and FDL points are shorted, the charge transfer control transistor 2 is turned on again, and the remaining photo-generated charge in the clamp photodiode 1 continues to be transferred to the FD and FDL points through the charge transfer control transistor 2. The FD point voltage value is read as a low gain signal value sig_l, which can be read out by the source follower 5, the row select transistor 6, and subsequent circuits.
The relation between the input light intensity and the output signal of the pixel of the high-dynamic CMOS image sensor with high-low gain and logarithmic response is shown in figure 5. Under certain integral time, the high-dynamic pixel can be divided into 4 working states, namely a state 1 (HG) and a state 2 (LG) which are linear regions, wherein the difference between the two states is that the state 1 corresponds to the weakest input light intensity, at the moment, the novel high-dynamic-range transistor 8 of the pixel is closed, the capacitance value of the FD point is small, and the CVG (charge-voltage conversion gain) of the pixel is large, so that the high signal-to-noise ratio can be obtained under weak light. The state 2 corresponds to strong light, and at the moment, the novel high dynamic range transistor 8 is started, the CVG of the pixel is smaller, and the capacity of the full well is increased. State 3 is the transition between state 2 and state 4, where the output signal is still proportional to the light intensity. The pixel works in the state 4 under the ultra-strong light, the charge compensation element 9 works in the subthreshold region, the current flowing from the clamping photodiode to the FD and the compensation current formed by the charge compensation element 9 reach balance, and the output signal is in direct proportion to the logarithm of the input light intensity, so that the dynamic range is enlarged. Under a certain integration time (such as 10 ms), the corresponding light intensity range of the state 1 is 0.0001lux magnitude to 0.1lux magnitude, the light intensity range of the state 2 is 0.1lux magnitude to 10lux magnitude, the light intensity range of the state 3 still maintains 10lux magnitude, and the light intensity range of the state 4 is more than 10lux magnitude to 10000lux magnitude. Therefore, by adopting the charge compensation element 9 and the control timing and signal reading mode, 4 pictures with the same exposure time can be output under one frame of imaging, and the pictures respectively aim at weak light, strong light and super strong light. Compared with the traditional method for improving the dynamic range by adopting high and low gains, the method provided by the invention has the advantages that states 3 and 4 are added besides the states 1 and 2 corresponding to weak light and strong light, wherein the state 3 is a transition state, the input light intensity changes by no more than 1 order of magnitude, and the state 4 corresponds to super strong light, at the moment, because the charge compensation element 9 provided by the invention works at a subthreshold value, the pixel output signals are in direct proportion to the logarithm of the light intensity, the dynamic range of the image sensor is greatly improved, and the dynamic range of at least 60dB is further increased on the basis of improving the dynamic range by adopting the high and low gains.
The invention has the beneficial effects that:
(1) Compared with the traditional high-dynamic image sensor pixel structure based on high and low gains, the high-dynamic CMOS image sensor with high and low gains and logarithmic response simultaneously does not change the pixel circuit structure, and the threshold voltages of the reset transistor and the high-dynamic range transistor forming the charge compensation element are reduced by adding one extra ion implantation to the charge compensation element, so that the charge compensation element works in a subthreshold region when the light intensity is too strong or the integration time is too long. At this time, the compensation current generated by the charge compensation element, which is exponentially related to the gate-source voltage, compensates for the photo-generated overflow current flowing to the FD point through the charge transfer control transistor. With the increase of light intensity or the increase of integration time, the two currents can reach balance, at this time, the FD point voltage will not change along with the integration time, and the voltage value is proportional to the logarithm of the incident light intensity, thereby greatly expanding the dynamic range of the image sensor.
(2) Compared with the prior image sensor which improves the dynamic range, the pixel structure of the high-dynamic CMOS image sensor with high-low gain and logarithmic response has a simple circuit structure, and the charge compensation element works in a subthreshold region under super-strong light or long-time exposure through threshold adjustment injection, so that the logarithmic response of input light intensity and output signals is realized. The method can simultaneously acquire a plurality of images with logarithmic mode, high gain, low gain and the like for objects with different light intensity and illuminance under one frame, and the images have the same exposure time, so that the LED flickering effect which cannot be detected by a high-dynamic image sensor based on the combination of double photodiodes and different integration time technologies is realized.
(3) Compared with the traditional image sensor pixel structure for realizing the high dynamic range, the high dynamic CMOS image sensor pixel structure with high and low gain and logarithmic response has the advantages that the high dynamic CMOS image sensor pixel structure is in linear response in weak light and strong light, the signal to noise ratio is the same as that of the traditional 4T pixel structure based on the clamp photodiode, the super weak light detection capability is achieved, the logarithmic response is achieved in super light, the output signal is not saturated along with the increase of light intensity, and the dynamic range can be expanded by 3-4 orders of magnitude.
(4) Compared with the traditional image sensor pixel structure for realizing the high dynamic range, the high dynamic CMOS image sensor pixel structure with high and low gain and logarithmic response can be divided into 4 working states according to the incident light intensity interval, namely linear high gain, linear low gain, logarithmic linearity and logarithmic response, and corresponds to weak light, strong light and super strong light transition and super strong light respectively. After the signal is amplified and analog-to-digital converted by the subsequent read-out circuit, the digital output signals in 4 states all contain sufficient information. And fusing the output results of the 4 states to obtain a high dynamic range image which simultaneously retains all details of the image from weak light to super light.
Drawings
FIG. 1 is a high low gain high dynamic pixel circuit configuration;
FIG. 2 is a high-low gain high dynamic pixel operation timing;
FIG. 3 is a high dynamic pixel circuit configuration with both high and low gain and logarithmic response;
FIG. 4 is a high dynamic pixel operating timing and readout scheme with both high and low gain and logarithmic response;
FIG. 5 is a plot of high dynamic pixel input light intensity versus output signal with both high and low gain and logarithmic response;
FIG. 6 is a timing diagram of the operation and reading of embodiment 1;
FIG. 7 is a timing and reading scheme for the operation of embodiment 2;
FIG. 8 is a high dynamic pixel circuit configuration of example 3 with both single gain linear response and logarithmic response;
FIG. 9 is a timing diagram of the operation and reading of embodiment 3;
in the figure, a clamp photodiode 1, a charge transfer control transistor 2, a reset transistor 3, a high dynamic range transistor 4, a source electrode follower 5, a row selection transistor 6, a novel reset transistor 7, a novel high dynamic range transistor 8 and a charge compensation element 9 are shown.
Detailed Description
Example 1
The high-dynamic CMOS image sensor pixel circuit structure having both high-low gain and logarithmic response described in embodiment 1 is shown in fig. 3. The pixel structure is composed of a clamping photodiode 1, a charge transfer control transistor 2, a novel reset transistor 7, a novel high dynamic range transistor 8, a source electrode follower 5 and a row selection transistor 6, wherein the charge transfer control transistor 2, the source electrode follower 5 and the row selection transistor 6 in the pixel are manufactured by adopting a standard NMOS transistor process, the novel reset transistor 7 and the novel high dynamic range transistor 8 jointly form the charge compensation element 9, and the charge compensation element is subjected to one additional ion implantation on the basis of the standard process and is used for adjusting the threshold voltage of the transistor to be minus 0.3V. The charge compensation element 9 operates in a subthreshold region under super-strong light or long-time integration, injects charges into the FD point, and is used for compensating photo-generated charges overflowing from the trap of the clamping photodiode 1 to the FD point, so as to avoid signal saturation caused by the fact that the clamping photodiode reaches a full trap. The clamping photodiode 1 is used as a photoelectric detection element, and can convert a received optical signal into an electric signal, wherein the P terminal is 0V, and the N terminal is connected with the source electrode of the charge transfer control transistor 2. The control signal TX of the gate of the charge transfer control transistor 2 comes from a row control module in the image sensor system, and the drain is connected to the FD point. The charge compensation element 9 comprises a novel reset transistor 7 and a novel high dynamic range transistor 8, wherein the drain electrode of the novel reset transistor 7 is connected with a Vpix potential of 3.3V, a grid control signal RST is from a row control module, the source electrode is connected to the drain electrode of the novel high dynamic range transistor 8, a grid control signal HDR of the novel high dynamic range transistor 8 is from the row control module, and the source electrode is connected to an FD point. The gate of the source follower 5 is connected to the FD point, the drain is connected to 3.3V, and the source is connected to the drain of the row select transistor 6. The control signal SEL at the gate terminal of the row select transistor 6 comes from a row control block, and the source is connected to the column bus for outputting the signal value of the pixel to a subsequent readout circuit of the image sensor system.
The specific time sequence control method and the reading mode of the high-dynamic CMOS image sensor with high-low gain and logarithmic response are shown in fig. 4, and the specific steps are as follows:
And step one, resetting operation.
First, the pixel enters a reset state, the charge transfer control transistor 2 and the charge compensation element 9 are turned on at the same time once, the charge in the clamp photodiode 1 is cleared, and the FD point voltage is reset to 3.3V.
And step two, integrating operation.
After the reset operation is completed, the gate control signal voltages of the charge transfer control transistor 2 and the charge compensation element 9 are both reduced to 0V, the pixel enters the integration stage, and the accumulation of photo-generated charge starts in the clamp photodiode 1.
1) When the exposure time is not long enough under weak light or strong light, the photo-generated charge generated in the clamping photodiode 1 is less than or equal to the full well capacity of the clamping photodiode 1, all photo-generated charges are accumulated in the clamping photodiode 1, and no excessive photo-generated charge flows to the FD point through the charge transfer control transistor 2, so the voltage of the FD point does not change in the integration time. The gate-source voltage V GS of the charge compensation element 9 is much smaller than the threshold voltage-0.3V, so that the charge compensation element 9 operates in the off-region and no current flows to the FD point.
2) With the increase of the light intensity or the extension of the integration time, the photo-generated charge accumulated in the clamping photodiode 1 during the integration process will have its own full well capacity, and the redundant photo-generated charge will flow to the FD point through the charge transfer control transistor 2 to form an over-current I OV, which is equal to the photo-generated current I ph generated by the clamping photodiode 1, and the voltage of the FD point is reduced, and the voltage change value is proportional to the integration time.
At this time, the light intensity is not large enough, so that the photo-generated charge flowing to the FD point is limited within a certain integration time, the voltage of the FD point is not reduced greatly, and two transistors in the charge compensation element are in an off state, so that the working state is not changed. This is shown by the FD point voltage being proportional to the light intensity. The voltage value of FD is read once before the integration is completed as a linear signal value log_s1 of the logarithmic mode.
3) When the light intensity is too strong or the integration time is long, the photo-generated charge accumulated in the clamping photodiode 1 far exceeds the full well capacity of the clamping photodiode, and the excessive photo-generated charge flows to the FD point through the charge transfer control transistor 2 and is accumulated at the FD point, so that a continuous photo-generated over-current I OV is generated, the voltage of the FD point is continuously reduced, and the V GS of the charge compensation element is continuously increased. Since the threshold voltage of the two transistors inside the charge compensation element 9 is adjusted to-0.3V, at which time the V GS value approaches the threshold voltage, the two transistors enter the subthreshold operating region from the off-region, resulting in a current flowing from Vpix to the FD point. This current can cancel the photo-generated overflow current I OV flowing from the clamp photodiode 1 to the FD point, and is therefore referred to as charge compensation current I C. If the light intensity is strong enough or the integration time is long enough, the photo-generated over-current I OV and the charge compensation current I C reach an equilibrium state, the FD point voltage will not change with the integration time any more. At this time, the charge compensation element 9 operates in the subthreshold region, and after balancing, the charge compensation current is equal to the photo-generated overflow current, so that the voltage value of the FD point is proportional to the logarithm of the incident light intensity. This voltage can be read out by the source follower 5, the row select transistor 6 and the subsequent circuits as a signal value log_s2 in logarithmic mode.
Before integration is finished, the FD point is reset once again, the transistors 7 and 8 in the charge compensation element are respectively turned on, when the gate control signal HDR of the novel high dynamic range transistor 8 is at a high level 4V, the image sensor readout circuit reads the reset value rst_l of the low gain, then the signal voltage of the HDR is reduced to 0V, the readout circuit of the image sensor reads the reset value rst_h of the high gain, and finally the gate control signal HDR of the novel high dynamic range transistor 8 is reduced to a low level 0V. The integration phase of the pixel circuit ends.
And step three, a first charge transfer process.
First, the charge transfer control transistor 2 is turned on, and the photo-generated charge accumulated in the clamp photodiode 1 is transferred to the FD point by the charge transfer control transistor 2 by the potential difference. At this time, the high gain signal value sig_h of the FD point is read.
And step four, a second charge transfer process.
After the first charge transfer, the novel high dynamic range transistor 8 is turned on, the FD and FDL points are shorted, the charge transfer control transistor 2 is turned on again, and the remaining photo-generated charge in the clamp photodiode 1 continues to be transferred to the FD and FDL points through the charge transfer control transistor 2. The signal value sig_l with the FD point voltage value of low gain is read.
Example 2
The high dynamic range image sensor pixel circuit configuration described in embodiment 2 is shown in fig. 3. The timing and reading patterns of the pixel structure of the high dynamic range CMOS image sensor described in embodiment 2 are shown in fig. 7. Embodiment 2 operates substantially the same as embodiment 1 except that the gate voltage value of the charge compensation element is not reduced to 0V but to 1V during integration in order to raise the source voltage of the charge compensation element, i.e., the voltage of the FD point, so that it is easier to perform signal processing and readout by a readout circuit following a pixel in the image sensor.
Example 3
The charge compensation element in the pixel of the high dynamic CMOS image sensor with both high and low gain and logarithmic response according to the present invention is composed of two transistors, and in this embodiment, the novel reset transistor and the novel high dynamic range transistor in the charge compensation element may be combined into one transistor to form the high dynamic range pixel with both single gain linear response and logarithmic response, and the circuit structure thereof is shown in fig. 8.
The operation timing and reading manner of the pixel circuit structure described in embodiment 3 are as shown in fig. 9. The pixel circuit operation is still divided into a reset phase, an integration phase and a charge transfer phase. The charge compensation element 9 and the charge transfer control transistor 2 are turned on once at the same time in the reset stage, the charges in the clamp photodiode 1 are emptied and the FD point is reset to 3.3V, the readout circuit samples the LOG signal LOG_SIG once before the integration is finished, then the FD point is reset once, the readout circuit reads the linear reset signal value LIN_RST, then the charge transfer control transistor 2 is turned on once, the photo-generated charges in the clamp photodiode 1 are transferred to the FD point, and the readout circuit reads the linear signal value LIN_SIG.
Claims (4)
1. A high dynamic CMOS image sensor having both high and low gain and logarithmic response, characterized in that the pixel structure comprises a clamp photodiode (1), a charge transfer control transistor (2), a charge compensation element (9), a source follower (5) and a row select transistor (6);
The charge compensation element (9) comprises a novel reset transistor (7) and a novel high dynamic range transistor (8), wherein the drain electrode of the novel reset transistor (7) is connected with a Vpix potential, the source electrode of the novel high dynamic range transistor (8) is connected with the drain electrode of the novel high dynamic range transistor (8), the source electrode of the novel high dynamic range transistor (8) is connected with the FD point, a grid control signal RST and an HDR of a charge compensation element (9) which are jointly formed by the novel reset transistor (7) and the novel high dynamic range transistor (8) are from a row control module in an image sensor system, the drain electrode of the charge compensation element is connected with the FD point, the charge compensation element (9) comprises a novel reset transistor (7) and a novel high dynamic range transistor (8), the grid control signal RST and the HDR of the novel reset transistor and the novel high dynamic range transistor (8) are connected with the grid electrode of the image sensor system, the grid control element is connected with the high-light and the high-light source electrode of the image sensor system, the high-light and the high-light-super-power light sensor circuit is connected with the grid electrode of the image sensor (5) when the image sensor system is in a continuous working time period, the grid electrode of the high-light sensor is connected with the high-power source electrode of the image sensor (5), the control signal SEL of the gate end of the row selection transistor (6) comes from a row control module, and the source is connected with a column bus and used for outputting the signal value of the pixel to a subsequent readout circuit of the image sensor system;
the charge transfer control transistor (2), the source follower (5) and the row selection transistor (6) are manufactured by adopting a standard NMOS transistor process;
The novel reset transistor (7) and the novel high dynamic range transistor (8) are subjected to one-time extra ion implantation based on a standard process and are used for adjusting the threshold voltage of the transistor to be lower than a normal value, so that the threshold voltage of the transistor and the threshold voltage are combined to form the charge compensation element (9), the charge compensation element works in a subthreshold region under super-strong light or long-time integration, photo-generated charges overflowed to the FD point by the charge compensation clamping photodiode (1) are injected to the FD point, signal saturation caused by the fact that the clamping photodiode (1) reaches a full trap is avoided, the characteristic that the current and the voltage of the transistor in the subthreshold region are in logarithmic relation is utilized, logarithmic response is obtained based on linear response of weak light and strong light, and the dynamic range of the image sensor is greatly expanded.
2. A timing control method and a reading mode of a high dynamic CMOS image sensor having both high and low gain and logarithmic response according to claim 1, characterized by the following specific steps:
step one, resetting operation;
firstly, the pixel enters a reset state, a charge transfer control transistor (2) and a charge compensation element (9) are conducted once at the same time, the charge in a clamping photodiode (1) is emptied, and the FD point voltage is reset to Vpix;
step two, integrating operation;
After the reset operation is finished, the voltages of gate control signals of the charge transfer control transistor (2) and the charge compensation element (9) are respectively reduced to VTXL and VRL, the pixel enters an integration stage, and the photo-generated charge begins to be accumulated in the clamping photodiode (1);
step three, a first charge transfer process;
Firstly, a charge transfer control transistor (2) is conducted, and photo-generated charges accumulated in a clamping photodiode (1) are transferred to an FD point through the charge transfer control transistor (2) under the action of potential difference, and then a high-gain signal value SIG_H of the FD point is read, and the voltage is read out through a source follower (5), a row selection transistor (6) and a subsequent circuit;
Step four, a second charge transfer process;
After the first charge transfer, the novel high dynamic range transistor (8) is started, the FD and FDL points are short-circuited, the charge transfer control transistor (2) is conducted again during the period, the rest photo-generated charges in the clamping photodiode (1) are continuously transferred to the FD and FDL points through the charge transfer control transistor (2), the voltage value of the FD point is a low-gain signal value SIG_L, and the voltage is read through the source follower (5), the row selection transistor (6) and a subsequent circuit.
3. The timing control method and the reading mode of the high-dynamic CMOS image sensor with both high-low gain and logarithmic response according to claim 2 are characterized in that under a certain integration time, the high-dynamic pixel is divided into 4 working states according to the intensity of incident light, namely, states 1-HG and states 2-LG are linear regions, wherein the difference between the states 1 and 2-LG is that the input light intensity is weakest corresponding to the states 1, at the moment, the novel high-dynamic range transistor (8) of the pixel is closed, the capacitance value of the FD point is small, the CVG of the pixel is large, and therefore, the very high signal to noise ratio can be obtained under weak light; the state 2 corresponds to strong light, the novel high dynamic range transistor (8) is started, the CVG of the pixel is smaller, the full-well capacity is increased, the state 3 is a transition part of the state 2 and the state 4, the output signal is still in direct proportion to the light intensity, the pixel works in the state 4 under the super-strong light, the charge compensation element (9) works in a subthreshold region, the current flowing from the clamping photodiode (1) to the FD and the compensation current formed by the charge compensation element (9) reach balance, the output signal is in direct proportion to the logarithm of the input light intensity, the dynamic range is enlarged, the state 1 corresponds to the light intensity range which is 0.0001-0.1 lux, the light intensity range of the state 2 is 0.1 lux-10 lux, the light intensity range of the state 3 is still in direct proportion to the light intensity, the light intensity range of the state 4 is in direct proportion to the 10 lux-10000 lux, the charge compensation element (9) and the control time sequence and the signal reading mode are used for outputting 4 pictures with the same exposure time under one frame of imaging, and the super-strong light respectively.
4. A high dynamic CMOS image sensor having both high and low gain and logarithmic response according to claim 1, characterized in that the charge compensation element (9) formed by the novel reset transistor (7) and the novel high dynamic range transistor (8) can be replaced by combining the novel reset transistor (7) and the novel high dynamic range transistor (8) in the charge compensation element (9) into one transistor to form a high dynamic range pixel having both single gain linear response and logarithmic response, the pixel circuit still operates as a reset phase, an integration phase and a charge transfer phase, the charge compensation element (9) and the charge transfer control transistor (2) are turned on once at the same time, the charges in the clamp photodiode (1) are cleared while the FD point is reset to Vpix, the readout circuit samples the logarithmic signal log_sig once before the integration is completed, then performs a reset operation on the FD point once, the readout circuit reads the linear reset signal value lin_rst_rst, and then the charge transfer control transistor (2) is turned on once to read the photo-generated FD point in the clamp photodiode (1), and the charge transfer control transistor (2) is turned on once.
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