CN115132256B

CN115132256B - NOR flash memory chip and its erase operation control system and control method

Info

Publication number: CN115132256B
Application number: CN202210812529.8A
Authority: CN
Inventors: 丛维; 林小峰; 朱庆军; 郑展为; 张晓印
Original assignee: Nanjing Youcun Technology Co ltd
Current assignee: Nanjing Youcun Technology Co ltd
Priority date: 2022-07-11
Filing date: 2022-07-11
Publication date: 2025-04-15
Anticipated expiration: 2042-07-11
Also published as: CN115132256A

Abstract

The present invention discloses a NOR flash memory chip and an erase operation control system and a control method thereof, the system comprising a first state marking module, a marking information storage device and a repair processing module; the first state marking module is used to set the first state marking information stored in the non-volatile marking information storage device as a state characterizing an abnormal interruption of the erase operation before the NOR flash memory chip is powered off or restarted due to power interference or abnormal power failure that causes the erase interruption during the erase operation; the repair processing module is used to obtain the first state marking information after power-on startup to control the use of a preset erase repair strategy for erase repair. The entire power-on and repair process of the present invention is automatically completed by the internal circuit of the chip, avoiding external complex control processes, improving the erase recovery processing efficiency and accuracy of the erase interruption situation in the chip, and avoiding the occurrence of data errors after the chip restarts due to power interruption during the erase operation.

Description

NOR type flash memory chip and erasing operation control system and control method thereof

Technical Field

The present invention relates to the field of flash memory technologies, and in particular, to a NOR (a type of flash memory chip) flash memory chip, and an erase operation control system and control method thereof.

Background

Semiconductor Memory is an indispensable component in modern information processing systems, and is mainly classified into two major categories, VM (Volatile Memory) and NVM (Nonvolatile Memory ) according to storage physical properties. Flash Memory (Flash Memory) is currently the most common nonvolatile Memory, and is mainly classified into NOR type Flash Memory and NAND type Flash Memory according to the Memory cell array structure and the read/write manner. The basic operation of flash memory includes writing (Program), erasing (Erase) and reading (Read), wherein writing and erasing correspond to the charging and discharging processes of FG (floating gate layer) or ONO (silicon oxide-silicon nitride-silicon oxide) layer of flash memory, respectively.

For example, the operation of erasing NOR flash memory corresponds to the discharge process of FG or ONO, which is generally implemented by FN Tunneling (FN Tunneling). Depending on the arrangement of the flash memory array, the erasure can operate in whole in terms of sectors (sectors) or blocks (blocks). To ensure uniformity of threshold Voltage (VT) distribution of flash memory cells (cells), conventional NOR flash erase operation flows include several steps, such as "pre-write (Preprogram Step)", "erase (ERASE STEP)", "over erase restore (Recovery Step)", "data refresh (REFRESH STEP)", and the like.

The erase operation in NOR flash memory is longer in time, on the order of tens or hundreds of milliseconds, than other operations such as reading, writing, etc. If there is interruption or disturbance of the power supply during the erase operation, resulting in restarting the chip, the erase operation is interrupted accidentally, and there is a high risk of errors in reading the data stored in the chip. The reason is that after the chip is restarted, the chip working state register is reset and the operation which is not completed before is not automatically continued. After the erase operation is interrupted, the state of the data of the area in which the erase operation is being performed before the restart is uncertain. Figure 1 lists the possible effects of interrupts on data at different steps in a typical erase operation of a NOR-type flash memory. In addition, in addition to the risk of data misreading in the target area, the data in the adjacent area may be affected because, on one hand, if the power interruption restart occurs at ERASE STEP or Recovery Step, the VT decrease caused by the interference of the erasing negative voltage in the adjacent area may not be recovered, which may affect the data reliability, and on the other hand, if the threshold voltage VT of the Cell in the target erase operation area is too low, the adjacent area of the common Bit line (Bit line) may have Bit line leakage current during the read operation, resulting in the read error, as shown in fig. 2.

Currently, for flash memory chips (particularly for NOR-type flash memory chips), the following two protection measures are mainly adopted for data errors caused after power failure occurs during an erase operation:

(1) The user is required to keep the power to the flash memory chip stable and check the status register state before any software or hardware mode is restarted to ensure that the erase operation is complete. But this approach does not prevent the occurrence of a passive restart of the flash memory due to system power instability.

(2) The method has the advantages that a specific over-erasure recovery operation command is added, but the method has the problems of external supervision and control, complex external flow and the like.

Disclosure of Invention

The technical problem to be solved by the invention is to overcome the defects that in the prior art, aiming at a NOR type flash memory chip, when interruption or interference of a power supply occurs in an erasing operation, the execution scheme that the erasing interruption easily causes data errors has the defects that the starting time of the chip is required to be increased or external supervision and control are required, the external flow is complex and the like, and the invention aims to provide the NOR type flash memory chip, and an erasing operation control system and a control method thereof.

The invention solves the technical problems by the following technical scheme:

The invention provides an erasure operation control system of a NOR flash memory chip, which comprises a first state marking module, a marking information memory and a repair processing module which are electrically connected in sequence;

The first state marking module is used for setting first state marking information stored in the nonvolatile marking information memory to be a state representing abnormal interruption of the erasing operation before the NOR type flash memory chip is powered down or restarted because of power supply interference or abnormal power failure which cause the erasing interruption in the erasing operation process;

And the repair processing module is used for acquiring the first state mark information stored in the mark information memory after power-on and starting, and controlling to adopt a preset erasure repair strategy to carry out erasure repair according to the first state mark information.

In the scheme, when the NOR type flash memory chip is powered down or restarted and then powered up again and started because of power supply interference or abnormal power failure which cause erasure interruption in the erasure operation process, the first state marking information which characterizes the erasure operation to be abnormally interrupted in the marking information storage can be automatically read, and then the erasure repairing scheme corresponding to the first state marking information is determined according to the first state marking information so as to automatically execute the erasure repairing operation by adopting the erasure repairing scheme. The whole power-on and repair process is automatically completed by the internal circuit of the chip, no external system supervision and control are needed, the external complex control process is avoided, meanwhile, the chip starting time can be saved, the erasure recovery processing efficiency of the erasure interruption condition in the NOR type flash memory chip is effectively improved under the condition that the external system supervision and control are not needed, the precision and the reliability of the erasure recovery operation are ensured, and the condition that the data is wrong after the chip is restarted due to the power interruption in the erasure operation is avoided.

Preferably, the erasure operation control system further comprises an erasure state monitoring module electrically connected with the first state marking module;

The erasing state monitoring module is used for monitoring the power state of the NOR type flash memory chip in the erasing operation, generating a trigger signal and transmitting the trigger signal to the first state marking module when the power disturbance or abnormal power failure causing the erasing interruption is monitored;

The first state marking module is used for setting the first state marking information stored in the nonvolatile marking information memory to be a state representing abnormal interruption of the erasing operation based on the trigger signal.

In the scheme, the erasure interruption interference factor causing the erasure operation interruption can be monitored in real time, the first state marking information representing the erasure operation interruption is timely triggered and set and stored in the nonvolatile marking information memory, so that the first state marking information in the marking information memory can be automatically read once the NOR type flash memory chip is powered down or restarted and then is powered up again due to the power supply interference or abnormal power failure causing the erasure interruption in the erasure operation process, and the timeliness, reliability and precision of erasure recovery processing on the erasure interruption condition in the NOR type flash memory chip are effectively improved.

Preferably, the repair processing module comprises a state reading unit and an erasure repair control unit which are electrically connected with the mark information memory in sequence;

the state reading unit is used for reading the first state marking information in the marking information memory and sending the first state marking information to the erasure repairing control unit after the NOR type flash memory chip is electrified and started;

The erasure repairing control unit is used for acquiring the corresponding preset erasure repairing strategy to carry out erasure repairing when the first state marking information is a state representing that the erasure operation is abnormally interrupted.

In the scheme, the repair processing module comprises two functional units, the reading function of the first state marking information and the control function of the erasure repairing operation based on the first state marking information are respectively and independently completed, the execution efficiency of the repair processing operation is guaranteed based on mutual independence and association coordination between the two functional units, the whole power-on and repair process is automatically completed by an internal circuit of the chip, no external system supervision and control are needed, and the method also belongs to the improved design requirement of the NOR type flash memory chip, and the rationality and the effectiveness of the erasure operation control scheme in the NOR type flash memory chip are guaranteed.

Preferably, the erase operation control system further comprises a block erase status flag module;

the block erasure state marking module comprises a plurality of erasure operation completion marking storage units which are in one-to-one correspondence with each physical block of the NOR flash memory chip;

The erasing operation control system is used for controlling the erasing operation completion mark storage unit and the corresponding physical block to perform erasing operation together;

the erasing operation control system is further used for executing writing operation on the erasing operation completion mark storage unit after the physical block corresponding to the erasing operation completion mark storage unit completes erasing operation;

And the repair processing module is used for confirming the block address of the physical block with the erase interrupt according to the condition that whether the erase operation is performed or not by the marked storage unit when the first state marked information is the state representing the abnormal interrupt of the erase operation, and executing the erase repair on the physical block at the block address.

In this scheme, each physical block of the NOR-type flash memory chip is provided with an erase operation completion flag storage unit corresponding one by one, the erase operation completion flag storage unit executes the same erase operation in the corresponding physical block erase process, and the difference between the two operations is that after the erase operation is completed on the physical block corresponding to the erase operation completion flag storage unit, the write operation representing that the corresponding physical block has completed the complete erase operation is also executed on the erase operation completion flag storage unit. Therefore, by judging whether the erasing operation is completed to mark the specific condition of the writing operation or not, the physical block with the erasing interruption can be rapidly and accurately positioned, and the erasing interruption condition in the NOR flash memory chip can be automatically repaired based on the block address of the physical block, so that the accuracy and the efficiency of the erasing recovery processing of the erasing interruption condition in the NOR flash memory chip are ensured.

Preferably, the erase operation control system further includes a bit line current detection module;

The repair processing module is used for calling the bit line current detection module when the first state marking information is a state representing that the erasing operation is abnormally interrupted;

The bit line current detection module is used for acquiring bit line current information of the whole flash memory array in the NOR flash memory chip, acquiring address information corresponding to a physical block or a physical sector where bit line leakage current occurs when the bit line current information represents that the bit line leakage current exists, and performing erasure repair on the physical block or the physical sector corresponding to the address information.

In the scheme, when the erasing operation in the NOR type flash memory chip is abnormally interrupted, whether the bit line current information of the whole flash memory array indicates the existence of the bit line leakage current is detected in time after the power-on again, and once the address of a physical block with the bit line leakage current or the address of a corresponding physical sector is automatically acquired, the erasing repair can be executed on the corresponding physical block or the physical sector, so that the efficiency, the feasibility and the flexibility of the erasing recovery processing on the erasing interruption condition in the NOR type flash memory chip are effectively ensured. The whole power-on and repair process is automatically completed by the internal circuit of the chip, and no external system supervision and control are needed.

Preferably, the erase state monitoring module is further configured to monitor a power state of the NOR flash memory chip during an erase repair operation, and when it is monitored that a power disturbance or an abnormal power failure, which causes an erase interrupt, occurs, generate the trigger signal again and transmit the trigger signal to the first state marking module.

In the scheme, in the erasure repairing process, whether the influence factors causing erasure repairing interruption occur or not is still monitored in real time, once the influence factors occur, the first state marking information of the erasure interruption condition is marked by the first state marking module in time, so that after the NOR type flash memory chip is electrified and started again, the erasure repairing scheme corresponding to the first state marking information is timely determined according to the latest recorded first state marking information until the erasure operation of the NOR type flash memory chip is completed, thereby realizing the erasure repairing of any one time as long as the erasure interruption caused by the power interruption interference occurs, timely and efficiently performing erasure repairing even if the erasure interruption occurs in the erasure repairing continuously for many times, and effectively improving the effectiveness, the reliability and the efficiency of the recovery processing of the erasure interruption condition in the flash memory chip.

Preferably, the first status marking module comprises an erasure status determining unit and a status memory erasing unit;

The erasing state determining unit is respectively and electrically connected with an erasing operation state machine in the NOR type flash memory chip and the state memory erasing unit;

The erasing state determining unit is used for receiving a state signal generated and output by the erasing operation state machine when the erasing operation is executed;

Wherein the status signal includes a start signal and an end signal of an erase operation;

The state memory erasing unit is used for setting the first state marking information stored in the nonvolatile marking information memory to be a state representing abnormal interruption of the erasing operation according to the state signal and the trigger signal.

In the scheme, based on the state signal corresponding to the erasure operation sent by the erasure operation state machine, the erasure state determining unit can acquire the state of the erasure operation, and once the erasure state monitoring module monitors that the power supply is abnormally interrupted in the erasure process, the erasure writing unit of the state memory is automatically triggered to execute the first state marking information for representing the abnormal interruption state of the erasure operation, and the two functional modules are mutually independent and associated and matched, so that the execution efficiency and the reliability of marking erasure interruption are ensured, and the control efficiency and the control precision of the whole erasure operation are further improved.

Preferably, the state memory erasing unit comprises a power supply pump and an auxiliary power supply electrically connected with the power supply pump;

The power supply pump is used for providing a first working voltage for the state memory erasing unit when the erasing operation and the writing operation are performed;

the auxiliary power supply is used for providing a second working voltage with a first set duration for the state memory erasing unit when the power is abnormally cut off.

In the scheme, in a normal state, a first working voltage is obtained based on a power supply pump when an erasing operation and a writing operation are performed, once an erasing interruption occurs, the first working voltage cannot be supported by the power supply pump, and at the moment, a certain time of power supply support is needed to be provided for a state memory erasing unit by relying on an auxiliary power supply (usually an electric storage capacitor) which stores a certain electric quantity in advance, so that the first state marking information generation, writing and other operations can be completed, and the key of realizing subsequent erasing repair is ensured.

Preferably, the erasure state determining unit includes a D flip-flop;

the clock end of the D trigger is connected with a starting signal of the erasing operation, and the reset signal end of the D trigger is controlled by a power-on signal and the ending signal of the erasing operation;

the D end of the D trigger is in a pull-up state, and the output end of the D trigger outputs the first state marking information which indicates whether power interruption occurs in the erasing operation process.

In the scheme, the D trigger is selected as the erasure state determining unit, so that the marking information of different dimensions contained in the first state marking information is respectively and independently obtained, the accuracy of the first state marking information is ensured, the control efficiency and the accuracy of the whole erasure operation are further improved, and meanwhile, the corresponding circuit also has the advantages of simple structure, small occupied space, low hardware investment cost and the like.

Preferably, the state memory erasing unit comprises a nand gate circuit and a data erasing circuit, and the data erasing circuit is electrically connected with the nand gate circuit and the mark information memory respectively;

two input ends of the NAND gate circuit are respectively and electrically connected with the output end of the erase state monitoring module and the output end of the D trigger;

The NAND gate circuit is used for triggering the data erasing circuit to write the first state mark information into the mark information memory when the output end of the erasing state monitoring module and the output end of the D trigger output high levels, or triggering the data erasing circuit to erase the history mark information in the mark information memory first and then write the first state mark information into the mark information memory;

Wherein the write operation is completed before the NOR-type flash memory chip is powered down or before a restart.

In the scheme, when erasure interruption occurs, the NAND gate circuit outputs high level based on two input end level signals, and the data erasing circuit is dynamically triggered in time to write the first state marking information, namely, based on the cooperation between the logic control circuit and the data erasing circuit, the processing efficiency of writing the first state marking information into the marking information memory is ensured, further, the stored first state marking information can be timely obtained after the NOR type flash memory chip is electrified and started, and the control efficiency of the whole erasure operation is effectively ensured.

Preferably, the auxiliary power supply comprises an electric storage capacitor, one end of the electric storage capacitor is electrically connected with the power supply pump and the data erasing circuit respectively, and the other end of the electric storage capacitor is grounded.

Preferably, the erase state monitoring module is configured to monitor voltage information of a power supply of the NOR flash memory chip, and determine that the power supply is interrupted and generate the trigger signal when the voltage information is smaller than a set voltage threshold or smaller than the set voltage threshold for a second set period of time;

In the scheme, through monitoring the voltage of the power supply in real time, when the voltage is smaller than a set value or continuously smaller than the set value, the power supply is directly determined to be interrupted, the first state mark information is triggered and generated in time and written into the nonvolatile mark information memory, the timeliness of the generation and writing of the first state mark information is ensured, and then the processing precision and timeliness of the subsequent erasing recovery operation are ensured.

And/or the number of the groups of groups,

The erasure repairing control unit is used for controlling to clear the first state marking information in the marking information memory after the erasure repairing operation is executed.

In the scheme, after the erasure repairing operation is executed, all the first state mark information recorded and stored is automatically cleared without subsequent clearing operation, so that the whole processing flow is simplified, meanwhile, only the latest first state mark information is ensured to be stored in the mark information memory, the reading efficiency of the state reading unit on the first state mark information is improved, the occurrence of information reading errors is avoided, and the subsequent erasure repairing control efficiency and accuracy are further effectively improved.

Preferably, the tag information memory is implemented by a set flash array disposed at a set position from a reference array in the NOR flash chip;

and/or the number of the groups of groups,

The set flash memory array and the reference array share the same read-write circuit;

and/or the number of the groups of groups,

The set flash memory array and the reference array do not share bit lines;

and/or the number of the groups of groups,

The set flash memory array and the reference array are in different P potential wells;

and/or the number of the groups of groups,

The set flash memory array is independently configured with corresponding data selectors;

and/or the number of the groups of groups,

The data selector includes a multiplexer;

and/or the number of the groups of groups,

The status reading unit is a reading circuit of a setting register in the NOR flash memory chip.

The invention also provides an erasure operation control method of the NOR flash memory chip, which is realized by adopting the erasure operation control system, and comprises the following steps:

Before the NOR type flash memory chip is powered down or restarted due to power supply interference or abnormal power failure which cause erasure interruption in the erasure operation process, setting first state marking information stored in a nonvolatile marking information memory as a state representing that the erasure operation is abnormally interrupted;

And after the power-on is started, acquiring the stored first state mark information, and controlling to adopt a preset erasure repairing strategy to carry out erasure repairing according to the first state mark information.

Preferably, the erase operation control method further includes:

Monitoring the power state of the NOR type flash memory chip in the erasing operation, and generating a trigger signal when the power disturbance or abnormal power failure causing the erasing interruption is monitored;

setting the first state flag information stored in the nonvolatile flag information memory to a state indicating that an abnormal interruption of an erase operation occurs based on the trigger signal.

The erase operation control method further includes:

After the physical block corresponding to the erasing operation completion mark storage unit completes the erasing operation, executing the writing operation on the erasing operation completion mark storage unit;

And when the first state marking information is a state representing that the erasing operation is abnormally interrupted, confirming the block address of the physical block with the erasing interruption according to the condition that whether the erasing operation is completed and marking the storage unit is executed with the writing operation or not, and executing erasing repair on the physical block at the block address.

Preferably, the step of controlling the erase repair using a preset erase repair policy according to the first status flag information includes:

Acquiring bit line current information of the whole flash memory array in the NOR type flash memory chip when the first state marking information is a state representing abnormal interruption of the erasing operation;

when the bit line current information represents that the bit line leakage current exists, address information corresponding to a physical block or a physical sector where the bit line leakage current occurs is obtained, and the physical block or the physical sector corresponding to the address information is erased and repaired.

Preferably, the erase operation control method further includes:

and monitoring the power state of the NOR type flash memory chip in the erase repair operation, and generating the trigger signal again when the power disturbance or abnormal power failure causing the erase interrupt is monitored.

The invention also provides a NOR type flash memory chip, which comprises the erasing operation control system.

On the basis of conforming to the common knowledge in the field, the preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the invention.

The invention has the positive progress effects that:

The invention can automatically read the first state mark information in the mark information memory once the NOR flash memory chip is powered down or restarted and then powered up again due to power supply interference or abnormal power failure causing erasure interruption in the erasure operation process, and then the erasure repairing scheme corresponding to the first state mark information is analyzed and determined according to the first state mark information so as to automatically execute erasure repairing operation by adopting the erasure repairing scheme. The whole power-on and repair process is automatically completed by the internal circuit of the chip, no external system supervision and control are needed, the external complex control process is avoided, meanwhile, the chip starting time can be saved, the erasure recovery processing efficiency of the erasure interruption condition in the NOR type flash memory chip is effectively improved under the condition that the external system supervision and control are not needed, the precision and the reliability of the erasure recovery operation are ensured, and the condition that the data is wrong after the chip is restarted due to the power interruption in the erasure operation is avoided.

Drawings

FIG. 1 is a schematic diagram of a typical erase operation of a conventional NOR flash memory, in which data is affected by interrupts at different steps.

FIG. 2 is a schematic diagram showing the bit line leakage current existing in the adjacent region of the common bit line in the NOR flash memory during the read operation.

Fig. 3 is a schematic diagram of an erase operation control system of a NOR-type flash memory chip according to embodiment 1 of the present invention.

Fig. 4 is a first configuration diagram of an erase operation control system of a NOR-type flash memory chip according to embodiment 2 of the present invention.

Fig. 5 is a second configuration diagram of an erase operation control system of a NOR-type flash memory chip according to embodiment 2 of the present invention.

Fig. 6 is a schematic diagram of a first implementation principle of the erase operation control system of the NOR-type flash memory chip according to embodiment 2 of the present invention.

Fig. 7 is a schematic diagram showing the configuration of ECMB (Erase Completion Mark Bit, erase operation completion flag bit) in the erase operation control system of the NOR-type flash memory chip according to embodiment 2 of the present invention.

Fig. 8 is a schematic diagram of a second implementation principle of the erase operation control system of the NOR-type flash memory chip according to embodiment 2 of the present invention.

Fig. 9 is a flowchart of the erase operation control method of the NOR-type flash memory chip of embodiment 3 of the present invention.

Fig. 10 is a flowchart of the erase operation control method of the NOR-type flash memory chip of embodiment 4 of the present invention.

Detailed Description

The invention is further illustrated by means of the following examples, which are not intended to limit the scope of the invention.

Example 1

As shown in fig. 3, the erase operation control system of the NOR-type flash memory chip of the present embodiment includes a first status flag block 1, a flag information memory 2, and a repair processing block 3 electrically connected in this order, wherein the flag information memory 2 may also be referred to as psi_sr (Power Supply Interruption Status Registers, power interruption status register).

The first state marking module 1 is used for setting the first state marking information stored in the nonvolatile marking information memory 2 to be a state representing that the erasing operation is abnormally interrupted before the NOR-type flash memory chip is powered down or restarted due to power supply interference or abnormal power failure which cause the erasing interruption in the erasing operation process;

The flag information memory 2, i.e. the psi_sr, is a set of nonvolatile registers for writing first state flag information indicating a state in which an abnormal interruption of an erase operation occurs when a power interruption occurs in an NOR-type flash memory chip in an erased state.

The repair processing module 3 is configured to obtain first status flag information stored in the flag information memory 2 after power-on, and control to perform erasure repair by using a preset erasure repair policy according to the first status flag information.

In the scheme, the erasure interrupt condition can be automatically judged and identified in time so as to timely mark and record and store a plurality of dimension information related to erasure interrupt, and the first state mark information is directly and automatically read and called after the NOR type flash memory chip is powered on again so as to automatically and accurately determine and start a corresponding erasure repairing scheme, thereby timely protecting and remedying the erasure interrupt condition.

It should be noted that, in this embodiment, the psi_sr is marked with the first state mark information under the condition that the psi_sr encounters a power interruption in the erase operation, and the repair processing module completes the erase repair after the power-up is instructed in the next power-up start, and then the psi_sr is erased and cleared, so that the first state mark information is generated and stored only when the power interruption is encountered in the erase operation, and only when the next power-up operation is performed, the psi_sr signal, that is, the first state mark information, is not erased for many times, thereby ensuring the reliability and stability of the operation of the NOR flash memory chip.

In the embodiment, once the first state marking information in the marking information memory is automatically read after power-down or restarting and restarting is performed due to power interference or abnormal power failure which cause erasure interruption in the process of erasure operation of the NOR type flash memory chip, the erasure repairing scheme corresponding to the first state marking information is determined according to analysis of the first state marking information, erasure repairing operation is automatically performed by adopting the erasure repairing scheme, whether the erasure operation is abnormally interrupted or not can be automatically and rapidly detected, the erasure repairing operation is automatically started if the erasure operation is abnormally interrupted, erasure recovery processing efficiency of erasure interruption conditions in the NOR type flash memory chip is effectively improved, accuracy and reliability of erasure recovery operation are guaranteed, occurrence of data errors after restarting of the chip due to power supply abnormal interruption in the erasure operation is avoided, the whole power-up and repairing flow is automatically completed by a chip internal circuit, external system supervision and control are not needed, an external complex control flow is avoided, and in addition, starting time of the chip can be saved.

Example 2

As shown in fig. 4 and 5, the erase operation control system of the NOR-type flash memory chip of the present embodiment is a further improvement of embodiment 1, specifically:

In an embodiment, the tag information memory 2 is implemented by a set flash array, which is disposed at a set position from a reference array in a NOR-type flash chip.

The flash memory array and the reference array are set to share the same read-write circuit.

Specifically, the flag information memory, i.e., the psi_sr, adopts one bit, and further can be implemented by selecting one FLASH CELL (flash unit), so as to achieve the effects of effectively saving chip area, reducing writing power consumption, and the like.

In order to simplify the design of the peripheral circuit, the PSI_SR array corresponding to the mark information memory can be selectively placed near the standard reference array (REFERENCE ARRAY, namely the reference array) in the NOR flash memory chip, so that the PSI_SR array shares the read-write circuit of the standard reference array, a special read-write circuit matched with the PSI_SR array is not required to be independently designed, the circuit arrangement structure is simplified, the arrangement space is reduced, and meanwhile, the hardware input cost is also reduced.

It should be noted that, according to the usage convention of registers and flash memory chips, the PSI_SR array is opposite to the "0" and "1" states corresponding to the erased and written states in the standard reference array REFERENCE ARRAY. In the PSI_SR array, the erased state corresponds to "0", the written state corresponds to "1", and in the normal reference array REFERENCE ARRAY, the erased state corresponds to "1", the written state corresponds to "0".

The flash memory array and the reference array are not set to share bit lines, and the standard reference array REFERENCE ARRAY does not share bit lines with the PSI_SR of the mark information memory, so that when the PSI_SR is erased, if power interruption occurs, the risk of bit line leakage current caused by possible over erasure of the PSI_SR of the mark information memory is avoided, and the stability and the safety of the whole operation of the NOR type flash memory chip are ensured.

Setting the flash memory array and the reference array to be in different P potential wells;

the flash memory array is set to independently configure corresponding data selectors, and specifically, the data selectors comprise multiplexers.

Specifically, the psi_sr array and the standard reference array REFERENCE ARRAY may be in different P-wells (TPW), and have separate word line Y-selectors (YMUX), so that the arrangement saves chip area as much as possible, simplifies circuit design, and can avoid interference to the standard reference array REFERENCE ARRAY when operating on the psi_sr.

In an embodiment, the erasure operation control system further includes an erasure state monitoring module 4 electrically connected to the first state marking module 1;

The erase state monitoring module 4 is configured to monitor a power state of the NOR-type flash memory chip during an erase operation, and generate a trigger signal and transmit the trigger signal to the first state marking module 1 when it is monitored that power disturbance or abnormal power failure causing an erase interrupt occurs;

the first status flag module 1 is configured to set first status flag information stored in the nonvolatile flag information memory 2 to a status indicating that an abnormal interruption of the erase operation occurs based on a trigger signal.

As shown in fig. 6, the erase operation control logic such as erase state monitoring, auto-write psi_sr, etc. corresponds to the erase operation control system.

In the scheme, the erasing interruption condition can be automatically monitored and identified in time, the erasing interruption interference factor causing interruption of the erasing operation is monitored in real time, the first state mark information representing abnormal interruption of the erasing operation is triggered and set in time and stored in the nonvolatile mark information memory 2, and the first state mark information in the mark information memory 2 can be automatically read once the power supply interference or abnormal power failure causing the erasing interruption of the NOR type flash memory chip occurs in the erasing operation process, so that the first state mark information in the mark information memory 2 can be automatically read after power down or restarting and restarting, and the timeliness, reliability and precision of the erasing recovery processing of the erasing interruption condition in the NOR type flash memory chip are effectively improved.

In an embodiment, the repair processing module 3 includes a status reading unit 5 and an erasure repair control unit 6 electrically connected in sequence with the tag information memory 2;

The status reading unit 5 is used for reading the first status marking information in the marking information memory 2 and sending the first status marking information to the erasure repairing control unit 6 after the NOR type flash memory chip is electrified and started;

the erasure repairing control unit 6 is configured to obtain a corresponding preset erasure repairing policy to perform erasure repairing when the first status flag information indicates that the erasure operation is abnormally interrupted.

In the scheme, the repair processing module 3 comprises two functional units, the reading function of the first state marking information and the control function of the erasure repairing operation based on the first state marking information are respectively and independently completed, the execution efficiency of the repair processing operation is guaranteed based on mutual independence and association coordination between the two functional units, the whole power-on and repair process is automatically completed by an internal circuit of a chip, no external system supervision and control are needed, and the method also belongs to the improved design requirement of the NOR type flash memory chip, and the rationality and the effectiveness of the erasure operation control scheme in the NOR type flash memory chip are guaranteed.

In addition, the status reading unit 5 can set a reading circuit of a register for the NOR-type flash memory chip, i.e. share the existing reading circuit, so as to effectively simplify the circuit design and save the chip area.

In one embodiment, the erase operation control system further includes a block erase status flag module 7.

The block erasure state flag module 7 includes a plurality of erasure operation completion flag storage units 8 corresponding to each physical block of the NOR flash memory chip one by one;

The erasing operation control system is used for controlling the erasing operation completion mark storage unit 8 to carry out erasing operation together with the corresponding physical block;

the erasing operation control system is further used for executing writing operation representing that the complete erasing operation is completed on the erasing operation completion mark storage unit 8 after the erasing operation is completed on the physical block corresponding to the erasing operation completion mark storage unit 8;

The repair processing module 3 is configured to confirm a block address of a physical block in which an erase interrupt occurs according to whether the erase operation is performed or not by the erase operation completion flag storage unit 8 when the first status flag information indicates that the erase operation is in an abnormally interrupted state, and perform erase repair on the physical block at the block address.

Specifically, ECMB is set in each physical block and combined with a single bit PSI_SR, when the chip is powered on, the unfinished erasing operation address is automatically and rapidly detected and automatic and rapid repair operation is performed.

Specifically, as shown in fig. 7, a schematic diagram of the arrangement of ECMB is shown, the erase operation of the memory array is performed in units of PB (Physical Block, which can be understood as sector), in this embodiment, one ECMB bit is set in each Physical Block PB (PB 0, PB1, &..fwdarw., PBn) for marking the completion status of the erase operation. In the erase operation, ECMB is performed Preprogram, erase, recovery together with other memory cells in the physical block PB, a ECMB write operation is added (ECMB Program) in the last step of the erase operation (after the conventional Refresh step is completed), so ECMB =0 indicates that one physical block is subjected to the complete erase operation, and ECMB =1 indicates that the erase operation is not normally completed in the physical block, so that the block address of the physical block can be obtained, and the erase repair is performed on the physical block at the block address in time.

The erasing operation control system also comprises a reading module for reading the erasing operation completion condition and sending the reading module to the repair processing module, wherein the reading module is used for reading whether the erasing operation completion mark storage unit 8 is subjected to the writing operation or not, and the reading module can directly adopt a reading circuit of the flash memory array so as to simplify the chip hardware design, reduce the chip area and reduce the input cost.

Specifically, in this scheme, each physical block of the NOR-type flash memory chip is provided with an erase operation completion flag storage unit corresponding one by one, and the erase operation completion flag storage unit performs the same erase operation in the corresponding physical block erase process, and the difference between the two operations is that after the erase operation is completed on the physical block corresponding to the erase operation completion flag storage unit, a write operation indicating that the complete erase operation has been completed is also performed on the erase operation completion flag storage unit. Therefore, by judging whether the erasing operation is completed to mark the specific condition of the writing operation of the memory unit 8, the physical block with the erasing interruption can be rapidly and accurately positioned, and the erasing interruption can be automatically repaired based on the block address of the physical block, so that the accuracy and the efficiency of the erasing recovery processing of the erasing interruption condition in the NOR type flash memory chip are ensured.

In one embodiment, the erase operation control system further includes a bit line current detection module 9;

the repair processing module 3 is used for calling the bit line current detection module 9 when the first state marking information is a state representing that the erasing operation is abnormally interrupted;

The bit line current detection module 9 is configured to obtain bit line current information (or column leakage current information) of an entire flash memory array in a NOR-type flash memory chip, obtain address information corresponding to a physical block or a physical sector in which the bit line leakage current occurs when the bit line current information indicates that the bit line leakage current (or column leakage current) exists, and invoke the repair processing module to erase and repair the physical block or the physical sector corresponding to the address information.

Specifically, as shown in fig. 8, the corresponding erase operation control system performs erase operation control logic when based on the bit line current detection module.

In the scheme, when the erasing operation in the NOR type flash memory chip is abnormally interrupted, whether the bit line current information of the whole flash memory array indicates the existence of the bit line leakage current or not is detected in time, and once the bit line leakage current exists, the address of a physical block with the occurrence of the bit line leakage current or the address of a corresponding physical sector can be automatically acquired, and the erasing repair can be executed on the corresponding physical block or the physical sector, so that the efficiency, the feasibility and the flexibility of the erasing recovery processing on the erasing interruption condition in the NOR type flash memory chip are effectively ensured. The whole power-on and repair process is automatically completed by the internal circuit of the chip, and no external system supervision and control are needed.

In an embodiment, the erase state monitoring module 4 is further configured to monitor a power state of the NOR-type flash memory chip during an erase repair operation, and to generate a trigger signal again and transmit the trigger signal to the first state marking module 1 when detecting that a power disturbance or abnormal power failure causing an erase interrupt occurs.

In the scheme, in the erasure repairing process, whether the influencing factors causing erasure repairing interruption occur or not is still monitored in real time, and once the influencing factors occur, the first state marking information of the erasure interrupting condition is timely triggered by the first state marking module 1, so that after the NOR type flash memory chip is electrified and started again, the erasure repairing scheme corresponding to the first state marking information is timely determined according to the latest recorded first state marking information until the erasure operation of the NOR type flash memory chip is completed, thereby realizing the erasure repairing of any one time as long as the erasure interrupting caused by the power interruption interference occurs, and timely and efficiently performing erasure repairing even if the erasure interrupting occurs in the erasure repairing for a plurality of times, and effectively improving the effectiveness, the reliability and the efficiency of the recovery processing of the erasure interrupting condition in the flash memory chip.

In an embodiment, the first status marking module 1 includes an erasure status determining unit 10 and a status memory erasing unit 11;

the erasure state determining unit 10 is electrically connected to an erasure operation state machine and a state memory erasing unit 11 in the NOR type flash memory chip, respectively;

The erase state determination unit 10 is configured to receive a state signal generated and output by an erase operation state machine when performing an erase operation;

the state signals comprise a start signal Erase_op_start and an end signal Erase_op_done of the erasing operation;

The state memory erasing unit 11 is configured to set first state flag information stored in the nonvolatile flag information memory 2 to a state indicating that an abnormal interruption of an erasing operation occurs, based on the state signal and the trigger signal.

In this scheme, based on the state signal corresponding to the erase operation sent by the erase operation state machine, the erase state determining unit 10 is capable of knowing the state of the erase operation, and once the erase state monitoring module 4 monitors that the power supply is abnormally interrupted in the erase process, the first state marking information indicating the state of the abnormal interruption of the erase operation is automatically triggered to be written into by the state memory erasing unit 11, and the two functional modules are mutually independent and associated and matched, so that the execution efficiency and reliability of marking erase interruption are ensured, and the control efficiency and accuracy of the whole erase operation are further improved.

In one embodiment, the state memory erasing unit 11 includes a power supply pump and an auxiliary power supply electrically connected to the power supply pump;

The power supply pump is used for providing a first working voltage for the state memory erasing unit 11 when the erasing operation and the writing operation are performed;

The auxiliary power supply is used for providing a second working voltage with a first set duration for the state memory erasing unit 11 when the abnormal power is off.

In the scheme, in a normal state, a first working voltage is obtained based on a power supply pump when an erasing operation and a writing operation are performed, and once power supply is abnormally interrupted in the erasing process, the power supply support given by the power supply pump cannot be obtained, and at the moment, an auxiliary power supply (usually an electric storage capacitor) which stores a certain electric quantity in advance is needed to provide a certain time period of power supply support for the state memory erasing unit 11 so as to ensure that the operations such as the generation and writing of first state mark information can be completed, which is a key for ensuring that the follow-up erasing and repairing are realized.

In one embodiment, the erase state determination unit 10 includes a D flip-flop;

The clock end of the D trigger is connected with a starting signal of the erasing operation, and the reset signal end of the D trigger is controlled by a power-on signal and an ending signal of the erasing operation;

the D end of the D trigger is in a pull-up state, and the output end of the D trigger outputs first state marking information which indicates whether power interruption occurs in the erasing operation process.

Specifically, as shown in fig. 5, the input signal (D) of the D flip-flop with reset is high, the Erase start signal (erase_op_start) output from the Erase Operation state machine (Erase Operation STATE MACHINE) controls the flip-flop Clock (CK), the output signal (Q) of the flip-flop is the Erase proceeding signal, and the Erase completion signal (erase_op_done) output from the Erase state machine and the power-on restart signal (POR) logically fetch or post control the reset of the flip-flop.

In the scheme, the D trigger is selected as the erasure state determining unit 10, so that the marking information of different dimensions contained in the first state marking information is respectively and independently obtained, the accuracy of the first state marking information is ensured, the control efficiency and the accuracy of the whole erasure operation are further improved, and meanwhile, the corresponding circuit also has the advantages of simple structure, small occupied space, low hardware investment cost and the like.

In an embodiment, the state memory erasing unit 11 includes a nand gate 12 and a data erasing circuit 13, and the data erasing circuit 13 is electrically connected to the nand gate 12 and the tag information memory 2, respectively;

two input ends of the NAND gate circuit 12 are respectively and electrically connected with the output end of the erasure state monitoring module 4 and the output end of the D trigger;

the NAND gate circuit 12 is used for triggering the data erasing circuit 13 to write the first state mark information into the mark information memory 2 when the output end of the erase state monitoring module 4 and the output end of the D trigger output high levels, or triggering the data erasing circuit 13 to erase the history mark information in the mark information memory 2 and then write the first state mark information into the mark information memory 2;

Wherein the write operation is completed before powering down or before restarting the NOR-type flash memory chip.

Specifically, referring to fig. 5, an erase_in_operation is outputted from the erase state determining unit 10 and inputted to the data erasing circuit 13 (or psi_sr erasing circuit), the flag information memory psi_sr is automatically written into the flag information memory psi_sr by a writing circuit in the nand gate back control data erasing circuit 13, when the nand gate output is 0, the power supply pump in the data erasing circuit 13 provides the voltage VPPX, VPPY, VPPD for the flag information memory psi_sr to perform the erase operation and the writing operation, and in order to support the writing function of the flag information memory psi_sr after power off, the power supply pump in the circuit is connected with a storage capacitor (C Drain), the selection of the size of the storage capacitor is related to the number of bits of the flag information memory psi_sr, which is enough to ensure that the writing of the flag information memory psi_sr after power off can be supported (time period level). In order to save the capacitance area and the occupied area of the PSI_SR, the PSI_SR is preferably realized by a nonvolatile Cell with one bit.

The state reading unit 5 and the erasure repairing control unit 6 which automatically operate after the chip is powered on automatically read PSI_SR signals after the chip is powered on, perform logic control according to PSI_SR of one bit, recover erasure operation which is not completed due to power interruption, and erase and clear the PSI_SR signals from the PSI_SR of the mark information memory.

In this scheme, when the erasure interruption occurs, the nand gate 12 outputs a high level based on two input end level signals, and dynamically triggers the data erasure circuit 13 to perform writing processing on the first state mark information in time, that is, based on the cooperation between the logic control circuit and the data erasure circuit 13, the processing efficiency of writing the first state mark information into the mark information memory is ensured, and further, the stored first state mark information can be timely obtained after the NOR flash memory chip is powered on, and the control efficiency of the whole erasure operation is effectively ensured.

In one embodiment, the auxiliary power supply includes a storage capacitor, one end of which is electrically connected to the power pump and the data erasing circuit 13, respectively, and the other end of which is grounded.

The auxiliary power supply can select the storage capacitor with a set specification, can also be composed of one or more storage capacitors, and can be formed by connecting the storage capacitors in series, in parallel, in partial series, in the residual parallel mode and the like when the auxiliary power supply is composed of a plurality of storage capacitors, and how the specific auxiliary power supply is designed can be designed or adjusted according to actual requirements.

In an embodiment, the erase state monitoring module 4 is configured to monitor voltage information of a power supply of the NOR-type flash memory chip, and determine that the power supply is interrupted and generate the trigger signal when the voltage information is smaller than a set voltage threshold, or smaller than the set voltage threshold for a second set period of time.

In the scheme, through monitoring the voltage of the power supply in real time, when the voltage is smaller than a set value (for example, 1.5V) or continuously smaller than the set value, the power supply is directly determined to be interrupted, the generation of the first state mark information is timely triggered and written into a nonvolatile mark information storage, the generation and the writing timeliness of the first state mark information are ensured, and then the processing precision and the timeliness of the subsequent erasing recovery operation are ensured.

In an embodiment, the erasure repairing control unit 6 is configured to control the clearing of the first state flag information in the flag information memory 2 after performing the erasure repairing operation.

In the scheme, after the erasure repairing operation is executed, all the first state mark information recorded and stored is automatically cleared without subsequent clearing operation, so that the whole processing flow is simplified, meanwhile, only the latest first state mark information is ensured to be stored in a mark information memory, the reading efficiency of the state reading unit 5 on the first state mark information is improved, the occurrence of information reading errors is avoided, and the subsequent erasure repairing control efficiency and accuracy are further effectively improved.

The implementation principle of the erase operation control system of the NOR-type flash memory chip of the present embodiment is specifically described below according to examples:

In the process that the NOR flash memory chip receives an erase command and executes erase operation by the erase operation state machine, an erase interrupt state monitoring module is adopted to monitor the change of the power supply voltage in real time, when the power supply voltage is too low, for example, lower than a preset value of 1.5V, if a first state marking module determines that the erase operation is not completed, a PSI_SR erasing module (data erasing circuit) automatically executes a PSI_SR signal (first state marking information), namely automatically executes PSI_SR writing operation, so as to ensure that PSI_SR writing is completed before the chip is powered down or restarted.

If the power interruption interference does not exist in the erasing operation process, the erasing operation is normally completed, the first state marking module cannot be accessed, the whole control flow is automatically completed by the internal circuit of the chip, and the external system supervision and control are not needed, so that the timely and efficient erasing operation control process of the NOR flash memory chip is ensured.

After the chip is powered on, the first state flag information in the flag information memory PSI_SR is automatically read.

For PSI_SR, 1 represents the written state and 0 represents the erased state. If psi_sr=0 is read, it indicates that no erase operation due to power interruption interference has not occurred before, and the chip enters a standby state to wait for further instructions. If psi_sr=1 is read, indicating that there is an incomplete erase operation before, an erase operation repair procedure is initiated. The whole process is automatically completed by the internal circuit of the chip, and no external system supervision and control are needed.

There are various alternatives for the erase operation repair procedure:

The scheme 1 comprises the steps of adopting a bit line current detection module to detect bit line current of the whole flash memory array, if bit line leakage current is found, performing complete erasure operation on a physical sector or a physical block where the bit line current detection module is located, performing erasure clearing operation on PSI_SR after an erasure operation restoration process is finished, finishing a power-on process by a chip, waiting for further instructions, and automatically finishing the whole power-on and restoration process by an internal circuit of the chip without supervision and control of an external system. The whole power-on and repair process is automatically completed by the internal circuit of the chip, and no external system supervision and control are needed.

The scheme 2 comprises the steps of automatically reading PSI_SR after a chip is powered on, if PSI_SR=0 is read, indicating that no erasing operation caused by power interruption interference does not occur before, enabling the chip to enter a standby state to wait for a further instruction, if PSI_SR=1 is read, indicating that no erasing operation is complete before, starting an erasing operation repair flow, reading ECMB of all physical blocks PB, carrying out complete erasing operation on the physical blocks if ECMB =1 is found, carrying out erasing and clearing operation on PSI_SR after the erasing operation repair flow is completed, enabling the chip to complete the power-on flow and waiting for a further instruction, and enabling the whole power-on and repair flow to be automatically completed by an internal circuit of the chip without external system supervision and control. That is, after the NOR-type flash memory chip is powered on, ECMB is read only when an abnormal interruption of the previous erase operation (psi_sr=1) is detected, thereby greatly shortening the chip power-on time, and simultaneously effectively ensuring the judgment accuracy of the occurrence of power supply disturbance or abnormal power-off causing the erase interruption, and the efficiency and reliability of the erase repair operation control.

In the embodiment, the whole power-on and repair process is automatically completed by the internal circuit of the chip, no external system supervision and control are needed, the external complex control process is avoided, meanwhile, the starting time of the chip can be saved, the erasure recovery processing efficiency of the erasure interruption condition in the NOR type flash memory chip is effectively improved under the condition that the external system supervision and control are not needed, the precision and the reliability of the erasure recovery operation are ensured, and the condition that the data is wrong after the chip is restarted due to the power interruption in the erasure operation is avoided.

Example 3

The erase operation control method of the NOR-type flash memory chip of the present embodiment is implemented using the erase operation control system of the NOR-type flash memory chip of embodiment 1 or 2.

As shown in fig. 9, the erase operation control method of the NOR-type flash memory chip of the present embodiment includes:

S101, before power supply interference or abnormal power failure causing erasure interruption occurs to a NOR flash memory chip in the erasure operation process to cause power-down or restarting, setting first state marking information stored in a nonvolatile marking information memory as a state representing the abnormal interruption of the erasure operation;

s102, after power-on starting, acquiring stored first state mark information, and controlling to adopt a preset erasure repairing strategy to carry out erasure repairing according to the first state mark information.

It should be noted that, in the embodiment, the first state flag information is generated and stored, only when the power supply is abnormally interrupted in the erase operation, there is one write operation and one erase operation when the power supply is electrified next time, and the psi_sr signal, that is, the first state flag information, cannot be erased for many times, so that the reliability and stability of the operation of the NOR flash memory chip are ensured.

Example 4

The erase operation control method of the NOR-type flash memory chip of the present embodiment is a further improvement of embodiment 3, specifically:

In an embodiment, as shown in fig. 10, step S101 includes:

S1011, monitoring the power state of the NOR flash memory chip in the erasing operation, and generating a trigger signal when the power disturbance or abnormal power failure causing the erasing interruption is monitored;

s1012, setting the first state flag information stored in the nonvolatile flag information memory to a state that characterizes an abnormal interruption of the erase operation based on the trigger signal.

In the scheme, the erasing interruption condition can be automatically monitored and identified in time, the erasing interruption interference factor causing interruption of the erasing operation is monitored in real time, the first state mark information representing abnormal interruption of the erasing operation is triggered and set in time and stored in the nonvolatile mark information memory, and the first state mark information in the mark information memory can be automatically read once the NOR type flash memory chip is powered down or restarted and is powered up again due to power supply interference or abnormal power failure causing the erasing interruption in the erasing operation process, so that the timeliness, reliability and precision of the erasing recovery processing of the erasing interruption condition in the NOR type flash memory chip are effectively improved.

In one embodiment, the erase operation control system further includes a block erase status flag module;

The erase operation control method further includes:

After the physical block corresponding to the erasing operation completion flag storage unit completes the erasing operation, executing a writing operation representing that the complete erasing operation is completed on the erasing operation completion flag storage unit;

In one embodiment, step S102 includes:

When the bit line current information represents that the bit line leakage current exists, the address information corresponding to the physical block or the physical sector where the bit line leakage current occurs is obtained, and the repair processing module is called to erase and repair the physical block or the physical sector corresponding to the address information.

In one embodiment, the erase operation control method further includes:

the power state of the NOR flash memory chip in the erase repair operation is monitored, and when the power disturbance or abnormal power failure causing the erase interrupt is monitored, a trigger signal is generated again.

It should be noted that, the implementation principle of the erase operation control method of the present embodiment is the same as that of embodiment 1 or 2, and will not be described here again.

Example 5

The NOR-type flash memory chip of the present embodiment includes the erase operation control system of embodiment 1 or 2.

The NOR-type flash memory chip in this embodiment, due to the integration of the above-mentioned erase operation control system, can automatically read the first state flag information corresponding to the last erase interrupt once the flash memory chip is restarted, and generate the erase repair scheme corresponding to the first state flag information to automatically execute the erase repair operation, thereby effectively improving the recovery processing efficiency of the erase interrupt condition in the NOR-type flash memory chip, avoiding the occurrence of the data error condition after restarting the chip due to the power interruption in the erase operation, and further effectively improving the overall product performance of the existing NOR-type flash memory chip.

While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the principles and spirit of the invention, but such changes and modifications fall within the scope of the invention.

Claims

1. An erase operation control system for a NOR flash memory chip, characterized in that the erase operation control system comprises a first state marking module, a marking information storage device and a repair processing module which are electrically connected in sequence;

The first status marking module is used to set the first status marking information stored in the non-volatile marking information memory to a state indicating that the erasing operation is abnormally interrupted before the NOR flash memory chip is powered off or restarted due to power interference or abnormal power failure that causes the erasing interruption during the erasing operation;

The repair processing module is used to obtain the first state mark information stored in the mark information storage device after power-on startup, and control the use of a preset erase repair strategy to perform erase repair according to the first state mark information;

The erasing operation control system further includes an erasing state monitoring module electrically connected to the first state marking module;

The erase state monitoring module is used to monitor the power state of the NOR flash memory chip during the erase operation, and when power interference or abnormal power failure that causes the erase interruption is detected, a trigger signal is generated and transmitted to the first state marking module;

The first status marking module is used to set the first status marking information stored in the non-volatile marking information storage to a state indicating that an abnormal interruption of an erase operation occurs based on the trigger signal;

The erase status monitoring module is also used to monitor the power status of the NOR flash memory chip during the erase repair operation, and when power interference or abnormal power failure that causes erase interruption is detected, the trigger signal is generated again and transmitted to the first status marking module.

2. The erase operation control system of the NOR flash memory chip according to claim 1, characterized in that the repair processing module comprises a state reading unit and an erase repair control unit which are electrically connected to the tag information memory in sequence;

The state reading unit is used to read the first state mark information in the mark information storage device and send it to the erase repair control unit after the NOR flash memory chip is powered on;

The erase repair control unit is used to obtain the corresponding preset erase repair strategy to perform erase repair when the first status mark information is a state indicating that an erase operation is abnormally interrupted.

3. The erase operation control system of the NOR flash memory chip according to claim 1 or 2, characterized in that the erase operation control system further comprises a block erase state marking module;

The block erase status mark module includes a plurality of erase operation completion mark storage units corresponding to each physical block of the NOR flash memory chip one by one;

The erasing operation control system is used to control the erasing operation completion mark storage unit to perform an erasing operation together with the corresponding physical block;

The erasing operation control system is further used to perform a write operation on the erasing operation completion mark storage unit after the physical block corresponding to the erasing operation completion mark storage unit completes the erasing operation;

The repair processing module is used to confirm the block address of the physical block where the erasure interruption occurs according to whether the write operation is performed on the storage unit marked by the completion of the erasure operation when the first status mark information is a state representing that the erasure operation has been abnormally interrupted, and perform erase repair on the physical block at the block address.

4. The erase operation control system of a NOR flash memory chip according to claim 1 or 2, characterized in that the erase operation control system further comprises a bit line current detection module;

The repair processing module is used to call the bit line current detection module when the first state mark information is a state indicating that an abnormal interruption of an erase operation occurs;

The bit line current detection module is used to obtain the bit line current information of the entire flash memory array in the NOR flash memory chip, and when the bit line current information indicates the existence of bit line leakage current, obtain the address information corresponding to the physical block or physical sector where the bit line leakage current occurs, and erase and repair the physical block or physical sector corresponding to the address information.

5. The erasing operation control system of a NOR flash memory chip according to claim 1 or 2, characterized in that the first state marking module comprises an erasing state determining unit and a state memory erasing unit;

The erase state determination unit is electrically connected to the erase operation state machine in the NOR flash memory chip and the state memory erase unit respectively;

The erase state determination unit is used to receive a state signal generated and output by the erase operation state machine when performing an erase operation;

Wherein, the status signal includes a start signal and an end signal of the erase operation;

The state memory erasing unit is used to set the first state flag information stored in the non-volatile flag information memory to a state indicating that an abnormal interruption of an erasing operation occurs according to the state signal and the trigger signal.

6. The erasing operation control system of a NOR flash memory chip according to claim 5, characterized in that the state memory erasing unit comprises a power pump and an auxiliary power supply electrically connected to the power pump;

The power pump is used to provide the state memory erase unit with a first operating voltage when performing erase operations and write operations;

The auxiliary power supply is used to provide the state memory erasing unit with a second operating voltage of a first set duration in the event of an abnormal power outage.

7. The erase operation control system of a NOR flash memory chip according to claim 6, wherein the erase state determination unit comprises a D flip-flop;

Wherein, the clock terminal of the D flip-flop is connected to the start signal of the erase operation, and the reset signal terminal of the D flip-flop is controlled by the power-on signal and the end signal of the erase operation;

The D end of the D flip-flop is in a pull-up state, and the output end of the D flip-flop outputs the first state mark information indicating whether a power interruption occurs during an erase operation.

8. The erasing operation control system of a NOR flash memory chip according to claim 7, characterized in that the state memory erasing unit comprises a NAND gate circuit and a data erasing circuit, and the data erasing circuit is electrically connected to the NAND gate circuit and the tag information memory respectively;

The two input ends of the NAND gate circuit are electrically connected to the output end of the erase state monitoring module and the output end of the D flip-flop respectively;

The NAND gate circuit is used to trigger the data erasing circuit to write the first state mark information into the mark information memory when the output end of the erasing state monitoring module and the output end of the D flip-flop both output a high level; or trigger the data erasing circuit to first erase the historical mark information in the mark information memory and then write the first state mark information into the mark information memory;

The write operation is completed before the NOR flash memory chip is powered off or restarted.

9. The erase operation control system of a NOR flash memory chip as described in claim 8, characterized in that the auxiliary power supply includes a storage capacitor, one end of the storage capacitor is electrically connected to the power pump and the data erase circuit respectively, and the other end of the storage capacitor is grounded.

10. The erasing operation control system according to claim 2, characterized in that the erasing state monitoring module is used to monitor the voltage information of the power supply of the NOR flash memory chip, and when the voltage information is less than a set voltage threshold, or is less than the set voltage threshold and lasts for a second set time, determine that the power supply is interrupted and generate the trigger signal;

and/or,

The erase repair control unit is used for controlling the clearing of the first state mark information in the mark information storage after performing the erase repair operation.

11. The erase operation control system according to claim 2, characterized in that the tag information memory is implemented by a setting flash memory array, and the setting flash memory array is arranged at a setting position away from a reference array in the NOR type flash memory chip;

and/or,

The setting flash memory array and the reference array share the same read-write circuit;

and/or,

The flash memory array and the reference array are set not to share bit lines;

and/or,

The flash memory array and the reference array are set to be in different P potential wells;

and/or,

The setting flash memory array independently configures the corresponding data selector;

and/or,

The data selector comprises a multiplexer;

and/or,

The state reading unit is a reading circuit of a setting register in the NOR flash memory chip.

12. A method for controlling the erasing operation of a NOR flash memory chip, characterized in that the method for controlling the erasing operation is implemented by using the erasing operation control system according to any one of claims 1 to 11, and the method for controlling the erasing operation comprises:

Before the NOR flash memory chip is powered off or restarted due to power interference or abnormal power failure that causes erasure interruption during an erasure operation, the first state flag information stored in the non-volatile flag information memory is set to a state indicating that the erasure operation is abnormally interrupted;

After power-on startup, acquiring the stored first state mark information, and controlling the use of a preset erase and repair strategy to perform erase and repair according to the first state mark information;

The erase operation control method further includes:

Monitoring the power state of the NOR flash memory chip during the erasing operation, and generating a trigger signal when power interference or abnormal power failure causing the erasing interruption is detected;

The first state flag information stored in the non-volatile flag information memory is set to a state indicating that an abnormal interruption of an erase operation occurs based on the trigger signal;

The erase operation control method further includes:

The power state of the NOR flash memory chip during the erase and repair operation is monitored, and when a power disturbance or abnormal power failure causing the interruption of the erase is detected, the trigger signal is generated again.

13. The erase operation control method of a NOR flash memory chip according to claim 12, wherein the erase operation control system further comprises a block erase state marking module;

The erase operation control method further includes:

After the physical block corresponding to the erase operation completion mark storage unit completes the erase operation, performing a write operation on the erase operation completion mark storage unit;

When the first status mark information is a state indicating that an erase operation is abnormally interrupted, the block address of the physical block where the erase interruption occurs is confirmed based on whether the erase operation completion mark storage unit is written, and erase repair is performed on the physical block at the block address.

14. The method for controlling the erasing operation of a NOR flash memory chip according to claim 12, wherein the step of controlling the use of a preset erasing repair strategy to perform erasing repair according to the first status mark information comprises:

When the first state mark information is a state indicating that an erase operation is abnormally interrupted, obtaining bit line current information of the entire flash memory array in the NOR flash memory chip;

When the bit line current information indicates the presence of a bit line leakage current, address information corresponding to a physical block or a physical sector where the bit line leakage current occurs is obtained, and the physical block or the physical sector corresponding to the address information is erased and repaired.

15. A NOR flash memory chip, characterized in that the NOR flash memory chip comprises the erase operation control system according to any one of claims 1 to 11.