CN115132907A - Chip packaging device for integrated circuits - Google Patents

Abstract

The invention discloses a chip packaging device for an integrated circuit, which comprises a circuit board, a chip and a shell, wherein the chip is arranged on one side of the circuit board, the shell is arranged on the outer surface of the chip, characterized in that the housing comprises a semiconductor heat conducting module and a heat dissipation module, the semiconductor heat conducting module comprises an upper semiconductor heat conducting unit and a lower semiconductor heat conducting unit, the upper semiconductor heat-conducting unit comprises an upper N-type semiconductor, an upper P-type semiconductor, an upper first conducting plate, an upper second conducting plate, an upper third conducting plate, an upper cold-end ceramic chip and an upper hot-end ceramic chip, the lower semiconductor heat conduction unit comprises a lower N-type semiconductor, a lower P-type semiconductor, a lower first conducting strip, a lower second conducting strip, a lower third conducting strip, a lower cold end ceramic piece and a lower hot end ceramic piece, and a heat dissipation module is arranged between the upper hot end ceramic piece and the lower hot end ceramic piece.

Description

Chip packaging device for integrated circuits

technical field

The invention relates to the technical field of chip sealing, in particular to a chip packaging device for integrated circuits.

Background technique

The chip of the integrated circuit is usually installed in the casing for packaging, so as to achieve the effect of fixing and sealing protection, and the metal casing can also increase the heat dissipation performance of the chip. As the integration of the chip becomes higher and higher, the power consumption of the chip is also increasing due to the requirements of the chip performance. The traditional packaging mainly avoids the corrosion of the chip caused by impurities in the air, and its heat dissipation capacity is limited. When the chip runs in a high power consumption state for a long time, it is easy to overheat and burn out. In addition, the use environment of chips is also increasingly complex, such as chips used in some mobile devices, long-term vibration will increase the risk of chip detachment, thereby affecting the normal operation of the device.

SUMMARY OF THE INVENTION

In order to solve the problems of insufficient chip heat dissipation performance and unstable installation in the prior art, the present invention provides a chip packaging device for an integrated circuit.

The technical scheme adopted in the present invention is:

A chip packaging device for integrated circuits, comprising a circuit board, a chip and a casing, the chip is arranged on one side of the circuit board, and the casing is arranged on the outer surface of the chip, characterized in that the casing comprises a semiconductor thermal conduction module and a heat dissipation module, the semiconductor heat conduction module includes an upper semiconductor heat conduction unit and a lower semiconductor heat conduction unit, the upper semiconductor heat conduction unit includes an upper N-type semiconductor, an upper P-type semiconductor, an upper first conductive sheet, an upper second conductive sheet, an upper The third conductive sheet, the upper cold end ceramic sheet and the upper hot end ceramic sheet, the upper first conductive sheet is arranged on the upper surface of the chip, the upper N-type semiconductor and the upper P-type semiconductor are respectively arranged on the upper first conductive sheet On both sides of the surface, the upper surface of the upper N-type semiconductor is provided with an upper second conductive sheet, the upper surface of the upper P-type semiconductor is provided with an upper third conductive sheet, and the upper cold-end ceramic sheet is provided on the upper second conductive sheet. Between a conductive sheet and the chip, the upper hot-end ceramic sheet is arranged on the upper surfaces of the upper second conductive sheet and the upper third conductive sheet, and the lower semiconductor heat-conducting unit includes a lower N-type semiconductor, a lower P-type semiconductor, a lower The first conductive sheet, the lower second conductive sheet, the lower third conductive sheet, the lower cold end ceramic sheet and the lower hot end ceramic sheet, the lower first conductive sheet is arranged on the lower surface of the chip, the lower N-type semiconductor and The lower P-type semiconductors are respectively arranged on both sides of the lower surface of the lower first conductive sheet, and the two sides of the lower N-type semiconductor and the lower P-type semiconductor respectively extend upward to the upper sides of the upper hot-end ceramic sheet. The second conductive sheet and the lower third conductive sheet are respectively arranged on the lower surface of the lower N-type semiconductor and the lower P-type semiconductor above the upper hot end ceramic sheet, and the lower cold end ceramic sheet is arranged on the lower first conductive sheet and the chip In between, the lower hot end ceramic sheet is arranged on the lower surface of the lower second conductive sheet and the lower third conductive sheet, and a heat dissipation module is arranged between the upper hot end ceramic sheet and the lower hot end ceramic sheet.

Preferably, a side of the chip corresponding to the upper N-type semiconductor has a current output terminal, a side of the chip corresponding to the upper P-type semiconductor has a current input terminal, and the current output terminals are respectively connected to the upper second conductive terminals through wires. sheet and the lower second conductive sheet, the current input ends are respectively connected to the upper third conductive sheet and the lower third conductive sheet through wires.

Preferably, the outer surfaces of the wires are all wrapped with insulating layers.

Preferably, an insulating layer is provided on the right side surface of the lower N-type semiconductor located on the left side of the chip, and an insulating layer is provided on the left side surface of the lower P-type semiconductor located on the right side portion of the chip.

Preferably, an insulating layer is filled between the upper N-type semiconductor and the upper second conductive sheet and the upper P-type semiconductor and the upper third conductive sheet, and the lower N-type semiconductor and the lower P-type semiconductor are located in the lower first The part of the lower surface of the conductive sheet is filled with an insulating and heat-insulating layer, the part of the lower N-type semiconductor on the upper surface of the lower second conductive sheet and the part of the lower second conductive sheet and the lower P-type semiconductor on the upper surface of the lower third conductive sheet An insulating and heat insulating layer is filled between it and the lower third conductive sheet.

Preferably, the heat dissipation module includes a hollow box body, and a plurality of through holes distributed at equal intervals are respectively opened on the front side wall and the rear side wall of the hollow box body.

Preferably, the outer side of the lower N-type semiconductor and the lower P-type semiconductor is provided with an inverted "U"-shaped mounting board, and the top wall of the mounting board wraps the lower N-type semiconductor and the lower P-type semiconductor. The part of the upper surface of the conductive sheet and the lower third conductive sheet, the two side walls of the mounting board respectively wrap the parts of the lower N-type semiconductor and the lower P-type semiconductor on both sides of the chip, and the bottom ends of the two side walls of the mounting board are respectively Ears for connecting with the chip are formed extending to the outer sides of the two side walls.

The beneficial effects of the present invention are:

1. The semiconductor thermal conduction module is used to conduct heat conduction, and the thermal conduction effect is better, thereby enhancing the heat dissipation capacity of the chip;

2. Through the specially designed lower N-type semiconductor and lower P-type semiconductor, the heat on the upper and lower surfaces of the chip is exported to the top, so that the same heat dissipation module can be used for heat dissipation;

3. The mounting plate is used for uniform installation and fixing. The semiconductor thermal conduction module in the mounting plate can conduct heat to the chip, and also limit the position of the chip to prevent the chip from loosening.

Description of drawings

1 is a schematic structural diagram of an embodiment of the present invention;

Reference numerals: 10, circuit board, 20, chip, 30, housing, 40, semiconductor thermal conduction module, 50, heat dissipation module, 51, hollow box, 52, through hole, 60, upper semiconductor thermal conduction unit, 61, upper N type semiconductor, 62, upper P-type semiconductor, 63, upper first conductive sheet, 64, upper second conductive sheet, 65, upper third conductive sheet, 66, upper cold end ceramic sheet, 67, upper hot end ceramic sheet, 70. Lower semiconductor heat conduction unit, 71, lower N-type semiconductor, 72, lower P-type semiconductor, 73, lower first conductive sheet, 74, lower second conductive sheet, 75, lower third conductive sheet, 76, lower cold end Ceramic sheet, 77, Lower hot end ceramic sheet, 80, Conductor, 81, Insulation layer, 90, Mounting plate, 91, Ear.

Detailed ways

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Example

As shown in FIG. 1 , a chip packaging device for an integrated circuit includes a circuit board 10 , a chip 20 and a casing 30 , the chip 20 is arranged on one side of the circuit board 10 , and the casing 30 is arranged outside the chip 20 It is characterized in that the housing 30 includes a semiconductor thermal conduction module 40 and a heat dissipation module 50, the semiconductor thermal conduction module 40 includes an upper semiconductor thermal conduction unit 60 and a lower semiconductor thermal conduction unit 70, and the upper semiconductor thermal conduction unit 60 includes an upper N-type thermal conduction unit. Semiconductor 61, upper P-type semiconductor 62, upper first conductive sheet 63, upper second conductive sheet 64, upper third conductive sheet 65, upper cold end ceramic sheet 66 and upper hot end ceramic sheet 67, the upper first conductive sheet The sheet 63 is arranged on the upper surface of the chip 20, the upper N-type semiconductor 61 and the upper P-type semiconductor 62 are respectively arranged on both sides of the upper surface of the upper first conductive sheet 63, and the upper surface of the upper N-type semiconductor 61 is provided with The upper second conductive sheet 64, the upper surface of the upper P-type semiconductor 62 is provided with an upper third conductive sheet 65, the upper cold end ceramic sheet 66 is provided between the upper first conductive sheet 63 and the chip 20, the The upper hot-end ceramic sheet 67 is disposed on the upper surfaces of the upper second conductive sheet 64 and the upper third conductive sheet 65 , and the lower semiconductor heat-conducting unit 70 includes a lower N-type semiconductor 71 , a lower P-type semiconductor 72 , and a lower first conductive sheet 73. The lower second conductive sheet 74, the lower third conductive sheet 75, the lower cold end ceramic sheet 76 and the lower hot end ceramic sheet 77, the lower first conductive sheet 73 is provided on the lower surface of the chip 20, the lower N The N-type semiconductor 71 and the lower P-type semiconductor 72 are respectively disposed on both sides of the lower surface of the lower first conductive sheet 73 , and the two sides of the lower N-type semiconductor 71 and the lower P-type semiconductor 72 respectively extend upward to the upper hot-end ceramic sheet 67 On both sides of the upper part, the lower second conductive sheet 74 and the lower third conductive sheet 75 are respectively arranged on the lower surface of the part where the lower N-type semiconductor 71 and the lower P-type semiconductor 72 are located above the upper hot-end ceramic sheet 67. The lower cold end ceramic sheet 76 is arranged between the lower first conductive sheet 73 and the chip 20, the lower hot end ceramic sheet 77 is arranged on the lower surface of the lower second conductive sheet 74 and the lower third conductive sheet 75, and the upper A heat dissipation module 50 is provided between the hot end ceramic sheet 67 and the lower hot end ceramic sheet 77 .

In order to enhance the heat dissipation capability of the chip 20 , the present embodiment utilizes the Peltier effect to dissipate heat to the chip 20 through the semiconductor thermal conduction module 40 , and the traditional heat dissipation method only dissipates heat on the upper surface of the chip 20 , while the heat on the lower surface of the chip 20 is dissipated. In this embodiment, the lower surface of the chip 20 is further dissipated by the specially designed lower semiconductor heat-conducting unit 70, so that the heat on the upper and lower surfaces of the chip 20 can be dissipated in time and effectively. The current is introduced into the upper second conductive sheet 64, and the current flows through the upper N-type semiconductor 61, the upper first conductive sheet 63, the upper P-type semiconductor 62 and the upper third conductive sheet 65 in sequence. According to the principle of the Peltier effect, the upper first conductive sheet 65. The conductive sheet 63 absorbs heat and absorbs the heat generated by the chip 20 from the upper surface through the upper cold end ceramic sheet 66 , while the upper second conductive sheet 64 and the upper third conductive sheet 65 release heat, and the upper hot end ceramic sheet 67 releases heat In order to export the heat on the lower surface of the chip 20, and simultaneously utilize the same heat dissipation module 50 to dissipate heat, the present embodiment has specially designed the lower N-type semiconductor 71 and the lower P-type semiconductor 72 of the "匚" type, and the current is introduced into the lower part. Two conductive sheets 74, the current flows through the lower N-type semiconductor 71, the lower first conductive sheet 73, the lower P-type semiconductor 72 and the lower third conductive sheet 75 in sequence. According to the principle of the Peltier effect, the lower first conductive sheet 73 absorbs heat, The heat generated by the chip 20 is absorbed from the lower surface of the lower cold end ceramic sheet 76 , while the lower second conductive sheet 74 and the lower third conductive sheet 75 release heat, and the lower hot end ceramic sheet 77 releases heat. The upper hot-end ceramic sheet 67 and the lower hot-end ceramic sheet 77 jointly dissipate heat through the heat dissipation module 50 .

In one embodiment, a side of the chip 20 corresponding to the upper N-type semiconductor 61 has a current output terminal, and a side of the chip 20 corresponding to the upper P-type semiconductor 62 has a current input terminal, and the current output terminal The upper second conductive sheet 64 and the lower second conductive sheet 74 are respectively connected by wires 80 , and the current input terminals are respectively connected to the upper third conductive sheet 65 and the lower third conductive sheet 75 by wires 80 .

The current output terminal of the chip 20 introduces the current into the upper second conductive sheet 64 and the lower second conductive sheet 74 respectively, and flows back through the upper third conductive sheet 65 and the lower third conductive sheet 75, so that the upper semiconductor heat conduction unit 60 and the lower semiconductor heat conduction unit 60 A current path is formed in the heat-conducting unit 70 to conduct heat by utilizing the Peltier effect.

In one embodiment, the outer surfaces of the wires 80 are all wrapped with insulating layers.

The insulating layer can avoid current leakage in the wires 80 and ensure that the upper semiconductor heat-conducting unit 60 and the lower semiconductor heat-conducting unit 70 work normally.

In one embodiment, the lower N-type semiconductor 71 is provided with an insulating layer on the right surface of the left portion of the chip 20 , and the lower P-type semiconductor 72 is provided with an insulating layer on the left surface of the right portion of the chip 20 .

The insulating layer can prevent the leakage of current in the lower N-type semiconductor 71 and the lower P-type semiconductor 72 , so as to ensure the normal operation of the lower semiconductor heat-conducting unit 70 .

In one embodiment, an insulating layer 81 is filled between the upper N-type semiconductor 61 and the upper second conductive sheet 64 and the upper P-type semiconductor 62 and the upper third conductive sheet 65, and the lower N-type semiconductor 71 and the portion of the lower P-type semiconductor 72 located on the lower surface of the lower first conductive sheet 73 are filled with an insulating and heat-insulating layer 81, the lower N-type semiconductor 71 located on the upper surface of the lower second conductive sheet 74 and the lower second conductive sheet 74. The insulating layer 81 is filled between the conductive sheet 74 and the portion of the lower P-type semiconductor 72 located on the upper surface of the lower third conductive sheet 75 and the lower third conductive sheet 75 .

The insulating layer 81 can effectively block the upper N-type semiconductor 61 and the upper P-type semiconductor 62 and the lower N-type semiconductor 71 and the lower P-type semiconductor 72, and can prevent the upper cold end ceramic sheet 66 and the lower cold end ceramic sheet 76 from being invalid Endothermic, the heat generated by the chip 20 can be absorbed in a concentrated manner.

In one embodiment, the heat dissipation module 50 includes a hollow box body 51 , and a plurality of through holes 52 equidistantly distributed are respectively opened on the front side wall and the rear side wall of the hollow box body 51 .

The heat generated by the upper hot-end ceramic sheet 67 and the lower hot-end ceramic sheet 77 is conducted to the outside through the hollow box 51, and the through holes 52 on the hollow box 51 allow the air inside and outside the hollow box 51 to circulate to dissipate the heat. Of course, In order to further enhance heat dissipation, a heat dissipation fan may also be provided in the hollow box 51 , or water-cooled heat dissipation may be introduced through the through holes 52 to enhance the heat dissipation capability.

In one embodiment, an inverted "U"-shaped mounting board 90 is provided on the outer sides of the lower N-type semiconductor 71 and the lower P-type semiconductor 72 , and the top wall of the mounting board 90 wraps the lower N-type semiconductor 71 and the lower part of the P-type semiconductor 72 on the upper surface of the lower second conductive sheet 74 and the lower third conductive sheet 75, the two side walls of the mounting board 90 respectively wrap the lower N-type semiconductor 71 and the lower P-type semiconductor 72 on the chip 20. On the two sides, the bottom ends of the two side walls of the mounting board 90 respectively extend to the outside of the two side walls to form ear portions 91 for connecting with the chip 20 .

The housing 30 is limited and fixed by the mounting plate 90 , and the mounting plate 90 can be fixed on the circuit board 10 by bolts through the ears 91 , so that the chip 20 is more firm and stable.

The above-mentioned embodiments only represent specific embodiments of the present invention, and the descriptions thereof are specific and detailed, but should not be construed as limiting the patent scope of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can also be made, which all belong to the protection scope of the present invention.

Claims (7)

1. A chip packaging device for an integrated circuit comprises a circuit board (10), a chip (20) and a shell (30), wherein the chip (20) is arranged on one side of the circuit board (10), the shell (30) is arranged on the outer surface of the chip (20), the chip packaging device is characterized in that the shell (30) comprises a semiconductor heat conduction module (40) and a heat dissipation module (50), the semiconductor heat conduction module (40) comprises an upper semiconductor heat conduction unit (60) and a lower semiconductor heat conduction unit (70), the upper semiconductor heat conduction unit (60) comprises an upper N-type semiconductor (61), an upper P-type semiconductor (62), an upper first conductive sheet (63), an upper second conductive sheet (64), an upper third conductive sheet (65), an upper ceramic sheet cold end (66) and an upper hot end ceramic sheet (67), the upper first conductive sheet (63) is arranged on the upper surface of the chip (20), the upper N-type semiconductor (61) and the upper P-type semiconductor (62) are respectively arranged at two sides of the upper surface of the upper first conducting plate (63), the upper surface of the upper N-type semiconductor (61) is provided with an upper second conducting plate (64), the upper surface of the upper P-type semiconductor (62) is provided with an upper third conducting plate (65), the upper cold-end ceramic plate (66) is arranged between the upper first conducting plate (63) and the chip (20), the upper hot-end ceramic plate (67) is arranged at the upper surfaces of the upper second conducting plate (64) and the upper third conducting plate (65), the lower semiconductor heat-conducting unit (70) comprises a lower N-type semiconductor (71), a lower P-type semiconductor (72), a lower first conducting plate (73), a lower second conducting plate (74), a lower third ceramic plate (75), a lower cold-end ceramic plate (76) and a lower hot-end ceramic plate (77), the lower first conducting strip (73) is arranged on the lower surface of the chip (20), the lower N-type semiconductor (71) and the lower P-type semiconductor (72) are respectively arranged on two sides of the lower surface of the lower first conducting strip (73), two sides of the lower N-type semiconductor (71) and the lower P-type semiconductor (72) respectively extend upwards to the upper parts of two sides of the upper hot-end ceramic piece (67), the lower second conducting strip (74) and the lower third conducting strip (75) are respectively arranged on the lower surfaces of the parts, above the upper hot-end ceramic piece (67), of the lower N-type semiconductor (71) and the lower P-type semiconductor (72), the lower cold-end ceramic piece (76) is arranged between the lower first conducting strip (73) and the chip (20), and the lower hot-end ceramic piece (77) is arranged on the lower surfaces of the lower second conducting strip (74) and the lower third conducting strip (75), and a heat dissipation module (50) is arranged between the upper hot end ceramic plate (67) and the lower hot end ceramic plate (77).

2. The chip packaging apparatus for integrated circuits according to claim 1, wherein a side of the chip (20) corresponding to the upper N-type semiconductor (61) has a current output terminal, a side of the chip (20) corresponding to the upper P-type semiconductor (62) has a current input terminal, the current output terminal is connected to the upper second conductive plate (64) and the lower second conductive plate (74) respectively through a wire (80), and the current input terminal is connected to the upper third conductive plate (65) and the lower third conductive plate (75) respectively through a wire (80).

3. The chip packaging arrangement for integrated circuits according to claim 2, characterized in that the outer surfaces of the wires (80) are each covered with an insulating layer.

4. The chip packaging arrangement for the integrated circuit according to claim 3, wherein a right side surface of the lower N-type semiconductor (71) at a left side portion of the chip (20) is provided with an insulating layer, and a left side surface of the lower P-type semiconductor (72) at a right side portion of the chip (20) is provided with an insulating layer.

5. The chip packaging apparatus for integrated circuits according to claim 4, wherein an insulating and heat-insulating layer (81) is filled between the upper N-type semiconductor (61) and the upper second conductive sheet (64) and the upper P-type semiconductor (62) and the upper third conductive sheet (65), an insulating and heat-insulating layer (81) is filled between the lower N-type semiconductor (71) and the lower P-type semiconductor (72) at the lower surface of the lower first conductive sheet (73), and an insulating and heat-insulating layer (81) is filled between the lower N-type semiconductor (71) at the upper surface of the lower second conductive sheet (74) and the lower P-type semiconductor (72) at the upper surface of the lower third conductive sheet (75) and the lower third conductive sheet (75).

6. The chip packaging apparatus for integrated circuits according to claim 5, wherein the heat dissipation module (50) comprises a hollow box (51), and a plurality of through holes (52) are respectively opened on a front side wall and a rear side wall of the hollow box (51) and are distributed at equal intervals.

7. The chip packaging device for the integrated circuit according to claim 5, wherein an inverted "U" shaped mounting plate (90) is disposed outside the lower N-type semiconductor (71) and the lower P-type semiconductor (72), a top wall of the mounting plate (90) wraps portions of the lower N-type semiconductor (71) and the lower P-type semiconductor (72) on upper surfaces of the lower second conductive sheet (74) and the lower third conductive sheet (75), two side walls of the mounting plate (90) wrap portions of the lower N-type semiconductor (71) and the lower P-type semiconductor (72) on two sides of the chip (20), and bottom ends of the two side walls of the mounting plate (90) extend to the outside of the two side walls to form ears (91) for connecting with the chip (20).

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