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CN115133629A - Charging control circuit, control method and lithium battery high-side driving circuit - Google Patents

Charging control circuit, control method and lithium battery high-side driving circuit Download PDF

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Publication number
CN115133629A
CN115133629A CN202211068061.2A CN202211068061A CN115133629A CN 115133629 A CN115133629 A CN 115133629A CN 202211068061 A CN202211068061 A CN 202211068061A CN 115133629 A CN115133629 A CN 115133629A
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China
Prior art keywords
mos transistor
coupled
charging
switch
source
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Granted
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CN202211068061.2A
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Chinese (zh)
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CN115133629B (en
Inventor
胡养聪
吴文贡
王轶
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Shenzhen Danyuan Semiconductor Co ltd
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Shenzhen Danyuan Semiconductor Co ltd
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Priority to CN202211068061.2A priority Critical patent/CN115133629B/en
Publication of CN115133629A publication Critical patent/CN115133629A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/007—Regulation of charging or discharging current or voltage
    • H02J7/00712—Regulation of charging or discharging current or voltage the cycle being controlled or terminated in response to electric parameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00—Secondary cells; Manufacture thereof
    • H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
    • H01M10/44—Methods for charging or discharging
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J2207/00—Indexing scheme relating to details of circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J2207/20—Charging or discharging characterised by the power electronics converter

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Electronic Switches (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)

Abstract

The invention provides a charging control circuit, a control method and a lithium battery high-side driving circuit. The charging control circuit is used for controlling the charging switch tube and comprises a first switch component and a second switch component. The first switch assembly is in a first working state based on the charging enabling signal and drives the charging switch tube to be conducted, and the second switch assembly is in the first working state based on the charging enabling signal and the state signal of the first switch assembly and drives the charging switch tube to be turned off; the input voltage signal is greater than the battery voltage signal. The charging control circuit, the charging control method and the lithium battery high-side driving circuit can be self-adaptive to different input voltages to control the on-off of the charging switch tube, can change the input voltage on line without changing the circuit structure, and simultaneously adopts current comparison and voltage clamping to control the on-off of the charging switch tube, so that the adjustable off speed is realized, the consumed current is low, and the service life of the lithium battery can be effectively prolonged.

Description

Charging control circuit, control method and lithium battery high-side driving circuit
Technical Field
The invention relates to the technical field of integrated circuits, in particular but not limited to a charging control circuit, a control method and a lithium battery high-side driving circuit.
Background
The lithium battery management driving scheme comprises a high-side driving mode and a low-side driving mode, and the high-side driving mode is grounded with an external controller MCU (microprogrammed control unit), so that isolation devices can be reduced, and the lithium battery management driving scheme is more and more popular. The high-side driver requires a voltage signal CP higher than the battery voltage BAT for driving the external high-voltage NMOS (CFET/DFET), as shown in fig. 1, where the CHG _ DRV high-side driver module is used for controlling the on/off of the charging tube CFET. When to turn on, the CHG is pulled up to the CP voltage; when to be turned off, CHG is pulled low to the BAT voltage. As shown in fig. 2, in the present high-voltage logic Control scheme, ON _ Control and OFF _ Control are used to charge and discharge the gate of the switch, all the switching tubes MNx are NMOS devices isolated from the substrate, the switching tube M0 is a high-side N-type MOS switch to be driven, the switching tube M1 is a common high-voltage NMOS, and the input voltage VHIGH is a driving power supply. The NMOS devices MN 0-MN 3 provide a bias circuit, and the switching tube M1 limits the grid charging voltage of the M0 for a source follower, so that the functions of high-side driving and controllable slew rate are realized.
The driving voltage of the N-type MOS provided in the prior art is limited by the VGS loop formed by the bias circuits MN 0-MN 3 and M1, the voltage of the driving M0 transistor is fixed and not variable (the voltage of the driving M0 transistor is VGS _ MN0+ VGS _ MN1+ VGS _ MN2+ VGS _ MN 3-VGS _ M1), and the power supply voltage (i.e. VHIGH-Source in fig. 2) is not fully utilized. When the switching tube M0 needs different driving voltages, the circuit structure needs to be changed, for example, more NMOS in diode connection form are stacked between MN1 and MN3 to realize the circuit structure. In addition, this structure requires a large current consumption.
In view of the above, it is desirable to provide a new structure or control method to solve at least some of the above problems.
Disclosure of Invention
Aiming at one or more problems in the prior art, the invention provides a charging control circuit, a control method and a lithium battery high-side driving circuit, which can be adaptive to different input voltages to control the on-off of a charging switch tube, can change the input voltage on line without changing the circuit structure, and simultaneously adopts current comparison and voltage clamping to control the on-off of the charging switch tube, thereby realizing adjustable off speed, lower consumed current and effectively prolonging the service life of the lithium battery.
The technical solution for realizing the purpose of the invention is as follows:
according to an aspect of the present invention, a charge control circuit is disclosed for controlling a charge switch tube, the charge control circuit comprising:
the first switch component is connected with the input voltage signal at the first end, the charging enabling signal at the second end, the third end is coupled with the first end of the second switch component and the charging switch tube, and the first switch component is in a first working state based on the charging enabling signal and drives the charging switch tube to be conducted;
the first end of the second switch component is coupled with the charging switch tube, the second end of the second switch component is connected with a battery voltage signal, the third end of the second switch component is connected with the internal potential end of the first switch component, and the second switch component is in a first working state and drives the charging switch tube to be turned off based on the charging enabling signal and the internal potential signal provided by the first switch component; the input voltage signal is greater than the battery voltage signal.
As an embodiment of the present invention, the first switching element and/or the second switching element are designed by back-to-back MOS transistors.
As an embodiment of the present invention, the first switch component includes a first MOS transistor and a second MOS transistor, a drain of the first MOS transistor is connected to the input voltage signal, a gate of the first MOS transistor and a gate of the second MOS transistor are both connected to a charging enable signal, a source of the first MOS transistor and a source of the second MOS transistor are connected to form a common source terminal and are coupled to a third terminal of the second switch component as an internal potential terminal, and a drain of the second MOS transistor is coupled to a first terminal of the second switch component and the charging switch tube.
As an embodiment of the present invention, the second switch component includes a third MOS transistor and a fourth MOS transistor, a drain of the third MOS transistor is coupled to the third terminal of the first switch component and the charging switch transistor, a source of the third MOS transistor is connected to a source of the fourth MOS transistor, a gate of the third MOS transistor is connected to a gate of the fourth MOS transistor to form a common gate and is coupled to a common source of the first switch component, and a drain of the fourth MOS transistor is connected to a battery voltage signal.
As an embodiment of the present invention, the charge control circuit further includes a first current source and a third current source, wherein:
the first current source is coupled between a common grid of the second switch component and a common source end of the first switch component, the common grid of the second switch component is grounded through a fifth MOS tube, a source electrode of the fifth MOS tube is grounded, a drain electrode of the fifth MOS tube is coupled with the common grid of the second switch component, and the grid is accessed to a charging enabling signal through an inverter;
the third current source is coupled between the drain of the fourth MOS transistor and the ground.
As an embodiment of the present invention, the third current source is coupled to the fourth MOS transistor through a sixth MOS transistor, wherein a source of the sixth MOS transistor is coupled to a first terminal of the third current source, a drain of the sixth MOS transistor is coupled to a drain of the fourth MOS transistor, and a gate of the sixth MOS transistor is coupled to the internal voltage source.
As an embodiment of the present invention, the charge control circuit further includes a first current source and a second resistor, wherein:
the first current source is coupled between a common grid of the second switch component and a common source end of the first switch component, the common grid of the second switch component is grounded through a fifth MOS tube, a source electrode of the fifth MOS tube is grounded, a drain electrode of the fifth MOS tube is coupled with the common grid of the second switch component, and the grid is accessed to a charging enabling signal through an inverter;
the second resistor is coupled between the drain of the fourth MOS transistor and the ground.
As an embodiment of the present invention, the second resistor is coupled to the fourth MOS transistor through a sixth MOS transistor, wherein a source of the sixth MOS transistor is coupled to the first end of the second resistor, a drain of the sixth MOS transistor is coupled to a drain of the fourth MOS transistor, and a gate of the sixth MOS transistor is coupled to the internal voltage source.
As an embodiment of the present invention, the charge control circuit further includes a second current source, the second current source is coupled between a fifth MOS transistor and ground, and a source of the fifth MOS transistor is coupled to a first end of the second current source.
As an embodiment of the present invention, the current of the second current source is much larger than the current of the first current source.
As an embodiment of the present invention, the charge control circuit further includes a clamping circuit, wherein a first terminal of the clamping circuit is coupled to a drain of the fourth MOS transistor, a second terminal of the clamping circuit is coupled to a drain of the sixth MOS transistor, a third terminal and a fourth terminal of the clamping current are respectively coupled to gates of the seventh MOS transistor and the eighth MOS transistor, a source of the seventh MOS transistor is connected to a source of the eighth MOS transistor, a drain of the seventh MOS transistor is coupled to a common gate of the second switching element, and a drain of the eighth MOS transistor is coupled to a drain of the fifth MOS transistor.
As an embodiment of the present invention, the clamp circuit includes a plurality of PMOS transistors, a gate and a drain of each PMOS transistor are connected, and a source and a drain of an adjacent PMOS transistor are connected; the grid electrode of the PMOS tube at the head end is coupled with the grid electrode of the seventh MOS tube, and the source electrode is coupled with the second end of the second switch component; the grid electrode of the PMOS tube at the tail end is coupled with the grid electrode of the eighth MOS tube, and the drain electrode of the PMOS tube is coupled with the drain electrode of the sixth MOS tube.
As an embodiment of the present invention, the clamp circuit includes a plurality of NMOS transistors, a gate and a drain of each NMOS transistor are connected, and a source and a drain of an adjacent NMOS transistor are connected; the source electrode of the NMOS tube at the head end is coupled with the drain electrode of the fourth MOS tube, and the source electrode is coupled with the grid electrode of the seventh MOS tube; and the source electrode of the NMOS tube at the tail end is coupled with the grid electrode of the eighth MOS tube and the drain electrode of the sixth MOS tube.
As an embodiment of the present invention, the charging control circuit further includes a level shift module, and the second terminal of the first switch component is connected to the charging enable signal through the level shift module.
As an embodiment of the present invention, the charging control circuit further includes a first resistor, and the third terminal of the first switch component and the first terminal of the second switch component are both coupled to the charging switch tube through the first resistor.
According to another aspect of the present invention, a lithium battery high-side driving circuit is disclosed, which includes a charging switch tube and the charging control circuit, wherein an input terminal of the charging control circuit is connected to an input voltage signal and a charging enable signal, and an output terminal of the charging control circuit is coupled to the charging switch tube.
In an embodiment of the invention, the charging switch tube is a high voltage transistor.
According to still another aspect of the present invention, a charge control method for controlling a charge switching tube is disclosed, the charge control method comprising:
acquiring a charging enable signal, an input voltage signal and a battery voltage signal;
according to the first state of the charging enabling signal, the first switch assembly is controlled to be in a first working state, so that the charging control voltage and the control voltage of the second switch assembly are increased to be equal to the input voltage signal, the external charging switch tube is started, and meanwhile, the second switch assembly is in a second working state;
and controlling the first switch assembly to be in a second working state according to the second state of the charging enabling signal, reducing the control voltage of the second switch assembly in a current comparison mode, enabling the second switch assembly to be in the first working state, reducing the charging control voltage to be equal to the voltage signal of the battery, and turning off the external charging switch tube.
In one embodiment of the present invention, when the charge enable signal is in the second state, the control voltage of the second switching element is clamped by the clamp circuit, and the second switching element is always maintained in the first operating state.
Compared with the prior art, the invention adopting the technical scheme has the following technical effects:
the invention provides a charging control circuit, a control method and a lithium battery high-side driving circuit. Meanwhile, the turn-off of the charging switch tube is controlled by adopting current comparison and voltage clamping, so that the turn-off speed is adjustable, the consumed current is low, and the service life of the lithium battery can be effectively prolonged.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description serve to explain the principles of the invention. In the drawings:
fig. 1 shows a circuit schematic of a prior art lithium battery high side drive application.
Fig. 2 shows a prior art high voltage logic control scheme.
Fig. 3 is a schematic circuit diagram of a charge control circuit according to an embodiment of the present invention.
Fig. 4 is a schematic circuit diagram of a charge control circuit according to another embodiment of the present invention.
Detailed Description
For a further understanding of the invention, reference will now be made to the preferred embodiments of the invention by way of example, and it is to be understood that the description is intended to further illustrate features and advantages of the invention, and not to limit the scope of the claims.
The description in this section is for several exemplary embodiments only, and the present invention is not limited only to the scope of the embodiments described. Combinations of different embodiments, and substitutions of features from different embodiments, or similar prior art means may be substituted for or substituted for features of the embodiments shown and described.
The term "coupled" or "connected" in this specification includes both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as a conductor, wherein the electrically conductive medium may contain parasitic inductance or parasitic capacitance, or through an intermediate circuit or component as described in the embodiments in the specification; indirect connections may also include connections through other active or passive devices that perform the same or similar function, such as connections through switches, signal amplification circuits, follower circuits, and so on. "plurality" or "plurality" means two or more.
An embodiment of the present invention discloses a charging control circuit, as shown in fig. 3, the charging control circuit is configured to control a charging switch tube CFET, a first end of the charging switch tube CFET is coupled to the charging control circuit, and a second end of the charging switch tube CFET is coupled to a lithium battery, that is, the charging switch tube CFET is disposed outside the charging control circuit, and the charging control circuit controls the charging switch tube CFET to charge the lithium battery.
In the embodiment shown in fig. 3, the charging control circuit includes a first switch component 101 and a second switch component 102, wherein a first terminal of the first switch component 101 is connected to the input voltage signal CP, a second terminal of the first switch component 101 is connected to the charging enable signal CHG _ EN, and a third terminal of the first switch component 101 is coupled to a first terminal of the second switch component 102 and the charging switch tube. That is, the first switch component 101 adjusts the driving control signal CHG and drives the charging switch tube to conduct based on the charging enable signal CHG _ EN being in the first working state. Preferably, the input voltage signal CP is an online variable voltage. The input voltage signal CP may be provided by a charge pump. In one embodiment, the first switch element 101 is turned on by the charge enable signal CHG _ EN, the driving control signal CHG for driving the charge switch tube CFET is adjusted to be equal to the input voltage signal CP, and the external charge switch tube CFET is driven to be turned on based on the driving control signal CHG. A first terminal of the second switch element 102 is coupled to the charging switch, a second terminal of the second switch element 102 is connected to the battery voltage signal BAT, and a third terminal of the second switch element 102 is connected to the internal potential terminal of the first switch element 101. That is, the second switch component 102 adjusts the driving control signal CHG and drives the charging switch tube to turn off based on the charging enable signal CHG _ EN and the internal potential VH1 of the first switch component 101 in the first working state. Preferably, the input voltage signal CP is greater than the battery voltage signal BAT, for example, the input voltage signal CP is the battery voltage signal BAT +5V or the battery voltage signal BAT + 11V. In one embodiment, the internal potential VH1 of the first switch element 101 turns on the second switch element 102, adjusts the driving control signal CHG for driving the charging switch tube CFET to be equal to the battery voltage signal BAT, and drives the external charging switch tube CFET to turn off based on the driving control signal CHG.
In a preferred embodiment, the first switch element 101 is designed with back-to-back MOS transistors to prevent ESD breakdown. Preferably, the first switch assembly 101 includes a first MOS transistor PM0 and a second MOS transistor PM 1. The drain of the first MOS transistor PM0 is connected to the input voltage signal CP, the gates of the first and second MOS transistors PM0 and PM1 are both connected to the charging enable signal CHG _ EN, the source of the first MOS transistor PM0 and the source of the second MOS transistor PM1 are connected to form a common source terminal and are coupled to the third terminal of the second switch element 102 as an internal potential terminal, and the drain of the second MOS transistor PM1 is coupled to the first terminal of the second switch element 102 and the charging switch tube. Further preferably, the first MOS transistor PM0 and the second MOS transistor PM1 are both PMOS transistors. In one embodiment, the first MOS transistor PM0 and the second MOS transistor PM1 are turned on by the charging enable signal CHG _ EN, and the charging switch CFET is turned on when the driving control signal CHG is equal to the input voltage signal CP.
In another preferred embodiment, the second switch element 102 is implemented by back-to-back MOS transistors to prevent ESD breakdown. Preferably, the second switch assembly 102 includes a third MOS transistor PM2 and a fourth MOS transistor PM 3. The drain of the third MOS transistor PM2 is coupled to the third end of the first switch component 101 and the charging switch tube, the source of the third MOS transistor PM2 is connected to the source of the fourth MOS transistor PM3, the gate of the third MOS transistor PM2 is connected to the gate of the fourth MOS transistor PM3 to form a common gate, and the common gate is coupled to the common source of the first switch component 101, so as to obtain the internal potential VH1 of the first switch component, and the drain of the fourth MOS transistor PM3 is connected to the battery voltage signal BAT. More preferably, the third MOS transistor PM2 and the fourth MOS transistor PM3 are both PMOS transistors. In one embodiment, the internal voltage VH1 of the first switch device 101 turns on the third MOS transistor PM2 and the fourth MOS transistor PM3, and when the driving control signal CHG is equal to the battery voltage signal BAT, the charging switch CFET is turned off.
In an embodiment of the present invention, as shown in fig. 3, the charge control circuit includes a first MOS transistor PM0, a second MOS transistor PM1, a third MOS transistor PM2, a fourth MOS transistor PM3, a first current source I1, and a third current source I3. The drain of the first MOS transistor PM0 is connected to the input voltage signal CP, the gates of the first and second MOS transistors PM0 and PM1 are both connected to the charging enable signal CHG _ EN, the source of the first MOS transistor PM0 and the source of the second MOS transistor PM1 are connected to form a common source terminal and are coupled to the gate of the third MOS transistor PM2 and the gate of the fourth MOS transistor PM3 as internal potential terminals, and the drain of the second MOS transistor PM1 is coupled to the drain of the third MOS transistor PM2 and the charging switch transistor CFET; the drain of the third MOS transistor PM2 is coupled to the drain of the second MOS transistor PM1 and the charge switch transistor CFET, the source of the third MOS transistor PM2 is connected to the source of the fourth MOS transistor PM3, the gate of the third MOS transistor PM2 is connected to the gate of the fourth MOS transistor PM3 to form a common gate and is coupled to the common sources of the first MOS transistor PM0 and the second MOS transistor PM1, and the drain of the fourth MOS transistor PM3 is connected to the battery voltage signal BAT. A first current source I1 is coupled between the common gate of the third MOS transistor PM2 and the fourth MOS transistor PM3 and the common source of the first MOS transistor PM0 and the second MOS transistor PM1, the common gate of the third MOS transistor PM2 and the common gate of the fourth MOS transistor PM3 are grounded through a fifth MOS transistor NM2, the source of the fifth MOS transistor NM2 is grounded, the drain of the fifth MOS transistor NM2 is coupled to the common gate of the third MOS transistor PM2 and the fourth MOS transistor PM3, and the gate of the fifth MOS transistor PM is connected to a charge enable signal CHG _ EN through an inverter; the third current source I3 is coupled between the drain of the fourth MOS transistor PM3 and ground. Therefore, the strong pull-down switch of the fifth MOS transistor NM2 is compared with the pull-up current of the first current source I1, so that the voltage VG2_ CHG of the common gate of the third MOS transistor PM2 and the fourth MOS transistor PM3 is pulled low. Further preferably, the third current source I3 is coupled to the fourth MOS transistor PM3 through a sixth MOS transistor NM3, wherein a source of the sixth MOS transistor NM3 is coupled to a first terminal of the third current source I3, a drain of the sixth MOS transistor NM3 is coupled to a drain of the fourth MOS transistor PM3, a gate of the sixth MOS transistor NM3 is coupled to the internal voltage source AVDD, and the sixth MOS transistor NM3 is constantly turned on. In a preferred embodiment, the charge control circuit further includes a second current source I2, and the second current source I2 is coupled between the common gate of the third MOS transistor PM2 and the fourth MOS transistor PM3 and the ground. Preferably, the current of the second current source I2 is much larger than the current of the first current source I1. Therefore, the current of the second current source I2 is compared with the current of the first current source I1, so that the voltage VG2_ CHG of the common gate of the third MOS transistor PM2 and the fourth MOS transistor PM3 is pulled low.
In another embodiment of the present invention, as shown in fig. 4, the charge control circuit includes a first MOS transistor PM0, a second MOS transistor PM1, a third MOS transistor PM2, a fourth MOS transistor PM3, a first current source I1, and a second resistor R0. The drain of the first MOS transistor PM0 is connected to the input voltage signal CP, the gates of the first and second MOS transistors PM0 and PM1 are both connected to the charging enable signal CHG _ EN, the source of the first MOS transistor PM0 and the source of the second MOS transistor PM1 are connected to form a common source terminal and are coupled to the gate of the third MOS transistor PM2 and the gate of the fourth MOS transistor PM3 as internal potential terminals, and the drain of the second MOS transistor PM1 is coupled to the drain of the third MOS transistor PM2 and the charging switch transistor CFET; the drain of the third MOS transistor PM2 is coupled to the drain of the second MOS transistor PM1 and the charge switch transistor CFET, the source of the third MOS transistor PM2 is connected to the source of the fourth MOS transistor PM3, the gate of the third MOS transistor PM2 is connected to the gate of the fourth MOS transistor PM3 to form a common gate and is coupled to the common sources of the first MOS transistor PM0 and the second MOS transistor PM1, and the drain of the fourth MOS transistor PM3 is connected to the battery voltage signal BAT. A first current source I1 is coupled between the common gate of the third MOS transistor PM2 and the fourth MOS transistor PM3 and the common source of the first MOS transistor PM0 and the second MOS transistor PM1, the common gate of the third MOS transistor PM2 and the common gate of the fourth MOS transistor PM3 are grounded through a fifth MOS transistor NM2, the source of the fifth MOS transistor NM2 is grounded, the drain of the fifth MOS transistor NM2 is coupled to the common gate of the third MOS transistor PM2 and the fourth MOS transistor PM3, and the gate of the fifth MOS transistor PM is connected to a charge enable signal CHG _ EN through an inverter; the second resistor R0 is coupled between the drain of the fourth MOS transistor PM3 and ground. Therefore, the strong pull-down switch of the fifth MOS transistor NM2 is compared with the pull-up current of the first current source I1, so that the voltage VG2_ CHG of the common gate of the third MOS transistor PM2 and the fourth MOS transistor PM3 is pulled low. Further preferably, the second resistor R0 is coupled to the fourth MOS transistor PM3 through a sixth MOS transistor NM3, wherein a source of the sixth MOS transistor NM3 is coupled to the first end of the second resistor R0, a drain of the sixth MOS transistor NM 3578 is coupled to the drain of the fourth MOS transistor PM3, a gate of the sixth MOS transistor NM3 is coupled to the internal voltage source AVDD, so that the sixth MOS transistor NM3 is constantly turned on, and at this time, a current flowing through the sixth MOS transistor NM3 is: (AVDD-VGS _ NM 3)/R0. In a preferred embodiment, the charge control circuit further includes a second current source I2, and the second current source I2 is coupled between the common gate of the third MOS transistor PM2 and the fourth MOS transistor PM3 and the ground. Preferably, the current of the second current source I2 is much larger than the current of the first current source I1. Therefore, the current of the second current source I2 is compared with the current of the first current source I1, so that the voltage VG2_ CHG of the common gate of the third MOS transistor PM2 and the fourth MOS transistor PM3 is pulled low.
Specifically, when the driving control signal VG1_ CHG of the first switch device 101 is logic low, the first MOS transistor PM0 and the second MOS transistor PM1 are turned on, and the driving control signal CHG and the driving control signal VG2_ CHG of the second switch device 102 are adjusted to be equal to the input voltage signal CP, that is: CHG = CP, VG2_ CHG = CP, then the external charging switch tube CFET is turned on, and the third MOS transistor PM2 and the fourth MOS transistor PM3 are turned off. At this time, the first current source I1 and the third current source I3 consume current, and the second current source I2 is turned off. When the driving control signal VG1_ CHG of the first switch element 101 is logic high, the first MOS transistor PM0 and the second MOS transistor PM1 are turned off, and since the body diode of the first MOS transistor PM0 exists, the internal potential VH1 of the first switch element 101 is: VH1= CP-Vbody _ diode, the driving control signal VG2_ CHG of the second switch element 102 is pulled down, and the first current source I1, the second current source I2 and the third current source I3 are all turned on. Since the current of the second current source I2 is much larger than the current of the first current source I1, the comparison of the two currents makes the driving control signal VG2_ CHG of the second switch device 102 pulled low, and turns on the third MOS transistor PM2 and the fourth MOS transistor PM3, and at this time, the driving control signal CHG is adjusted to be equal to the battery voltage signal BAT, and the external charging switch CFET is turned off. When the voltage VB is pulled down to ground, the second current source I2 is turned off, and only the first current source I1 and the third current source I3 consume current.
In still another embodiment of the present invention, as shown in fig. 3, the charge control circuit includes a first MOS transistor PM0, a second MOS transistor PM1, a third MOS transistor PM2, a fourth MOS transistor PM3, a first current source I1, a second current source I2, a third current source I3, and a clamp circuit 103. The drain of the first MOS transistor PM0 is connected to the input voltage signal CP, the gate of the first MOS transistor PM0 and the gate of the second MOS transistor PM1 are both connected to the charge enable signal CHG _ EN, the source of the first MOS transistor PM0 and the source of the second MOS transistor PM1 are connected to form a common source and are coupled to the gate of the third MOS transistor PM2 and the gate of the fourth MOS transistor PM3 as internal potential terminals, and the drain of the second MOS transistor PM1 is coupled to the drain of the third MOS transistor PM2 and the charge switch transistor CFET; the drain of the third MOS transistor PM2 is coupled to the drain of the second MOS transistor PM1 and the charging switch CFET, the source of the third MOS transistor PM2 is connected to the source of the fourth MOS transistor PM3, the gate of the third MOS transistor PM2 is connected to the gate of the fourth MOS transistor PM3 to form a common gate and is coupled to the common sources of the first MOS transistor PM0 and the second MOS transistor PM1, and the drain of the fourth MOS transistor PM3 is connected to the battery voltage signal BAT and is coupled to the first terminal of the clamp circuit 103. The second terminal of the clamp circuit 103 is coupled to the third current source I3 through a sixth MOS transistor NM3, wherein a source of the sixth MOS transistor NM3 is coupled to the first terminal of the third current source I3, a drain of the sixth MOS transistor NM3 is coupled to the second terminal of the clamp circuit 103, a gate of the sixth MOS transistor NM3 is coupled to the internal voltage source AVDD, and the sixth MOS transistor NM3 is constantly turned on. The third end and the fourth end of the clamp circuit 103 are respectively coupled to the gates of a seventh MOS transistor and an eighth MOS transistor, the source of the seventh MOS transistor is connected to the source of the eighth MOS transistor, the drain of the seventh MOS transistor is coupled to the common gate of the third MOS transistor PM2 and the fourth MOS transistor PM3, the drain of the eighth MOS transistor is coupled to the drain of the fifth MOS transistor NM2, the source of the fifth MOS transistor NM2 is coupled to the first end of the second current source I2, the second end of the second current source I2 is grounded, and the gate of the fifth MOS transistor 2 is connected to the charging enable signal chnm _ EN through the inverter. A first current source I1 is coupled between the common gate of the third MOS transistor PM2 and the fourth MOS transistor PM3 and the common source of the first MOS transistor PM0 and the second MOS transistor PM1, and the common gate of the third MOS transistor PM2 and the fourth MOS transistor PM3 is coupled to the drain of the seventh MOS transistor NM 1. Preferably, the current of the second current source is much larger than the current of the first current source. Preferably, the third current source I3 may be replaced by a second resistor R0. It is further preferable that, by removing the second current source I2, the source of the fifth MOS transistor NM2 is directly grounded.
In a preferred embodiment, as shown in fig. 3, the clamp circuit 103 includes a plurality of PMOS transistors PM4 to PM7, gates and drains of the PMOS transistors PM4 to PM7 are connected, a drain of the PM4 is connected to a source of the PM5, a drain of the PM5 is connected to a source of the PM6, and a drain of the PM6 is connected to a source of the PM 7; the grid electrode of the PMOS tube PM4 at the head end is coupled with the grid electrode of the seventh MOS tube NM1, the voltage of the grid electrode of the PMOS tube PM4 is recorded as Vclamp1, the Vclamp1 is about BAT-1.2V, and the source electrode of the PMOS tube PM4 is coupled with the drain electrode of the fourth MOS tube and the battery voltage BAT; the grid electrode of the PMOS pipe PM7 at the tail end is coupled with the grid electrode of the eighth MOS pipe, the drain electrode of the PMOS pipe PM7 is coupled with the drain electrode of the sixth MOS pipe, the voltage of the grid electrode of the PMOS pipe PM7 is recorded as Vclamp2, and the Vclamp2 is about BAT-5.8V.
In another preferred embodiment, as shown in fig. 4, the clamp circuit 103 includes a plurality of NMOS transistors NM4 to NM7, gates and drains of the NMOS transistors NM4 to NM7 are connected, a source of the NM4 is connected to a drain of the NM5, a source of the NM5 is connected to a drain of the NM6, and a source of the NM6 is connected to a drain of the NM 7; the drain of the first NMOS transistor NM4 is coupled to the drain of the fourth MOS transistor PM3, and the source is coupled to the gate of the seventh MOS transistor NM 1; the source of the NMOS transistor NM7 at the end is coupled to the gate of the eighth MOS transistor PM8 and the drain of the sixth MOS transistor NM 3.
When the driving control signal VG1_ CHG of the first switch element 101 is logic low, the first MOS transistor PM0 and the second MOS transistor PM1 are turned on, and the driving control signal CHG and the driving control signal VG2_ CHG of the second switch element 102 are adjusted to be equal to the input voltage signal CP, so that the external charging switch tube CFET is turned on, and the third MOS transistor PM2 and the fourth MOS transistor PM3 are turned off. At this time, the first current source I1 and the third current source I3 consume current, and the second current source I2 is turned off. When the driving control signal VG1_ CHG of the first switch component 101 is logic high, the first MOS transistor PM0 and the second MOS transistor PM1 are turned off, and at this time, the first current source I1, the second current source I2 and the third current source I3 are all turned on. Since the current of the second current source I2 is much larger than the current of the first current source I1, the driving control signal VG2_ CHG of the second switching element 102 is pulled down to VM = Vclamp2+ VSG _ PM8 by the two-current comparison. Then, a VGS ring formed by the clamping circuit 103, the seventh switching transistor NM1 and the eighth switching transistor PM8 clamps the driving control signal VG2 — CHG of the second switching element 102 to be lower than the battery voltage signal BAT by about 3 × Vsg, so that the third MOS transistor PM2 and the fourth MOS transistor PM3 are ensured to be turned on, and at this time, the driving control signal CHG is adjusted to be equal to the battery voltage signal BAT, and the external charging switching transistor CFET is turned off. When the voltage VB is pulled down to ground, the second current source I2 is turned off, and only the first current source I1 and the third current source I3 consume current.
In an embodiment, the charging control circuit may further include a level shift module 104, as shown in fig. 3, a second terminal of the first switch element 101 is connected to the charging enable signal CHG _ EN through the level shift module 104, that is, a first terminal of the level shift module 104 is coupled to the gate of the first MOS transistor PM0 and the gate of the second MOS transistor PM1, and a second terminal of the level shift module 104 is connected to the charging enable signal CHG _ EN. The level shift module 104 is configured to generate a level shift and a corresponding clamp voltage, so as to implement a function of converting the charging enable signal CHG _ EN from low to high. When the charge enable signal CHG _ EN is at a high level, the driving control signal VG1_ CHG of the first switch element 101 output by the level shifter module 104 is at a logic low level; when the charge enable signal CHG _ EN is at a low level, the driving control signal VG1_ CHG of the first switch element 101 output by the level shifter module 104 is at a logic high.
In an embodiment, the charge control circuit may further include a first resistor (not shown in the drawings), the drain of the second MOS transistor PM1 and the drain of the third MOS transistor PM2 are both coupled to the charge switch transistor CFET through the first resistor, and the driving control signal CHG generated by the charge control circuit is output through the first resistor to implement current limiting and adjust oscillation caused by parasitic inductance and parasitic capacitance.
The invention further discloses a lithium battery high-side driving circuit, which comprises a charging switch tube CFET and the charging control circuit, wherein the input end of the charging control circuit is connected with an input voltage signal CP and a charging enable signal CHG _ EN, and the output end of the charging control circuit is coupled with the charging switch tube.
In an embodiment, the charge switch tube CFET is a high voltage transistor.
The invention further discloses a charging control method, which is used for controlling a charging switch tube and comprises the following steps:
obtaining a charge enable signal, an input voltage signal and a battery voltage signal;
according to the first state of the charging enabling signal, the first switch assembly is controlled to be in a first working state, so that the charging control voltage and the control voltage of the second switch assembly are increased to be equal to the input voltage signal, the external charging switch tube is started, and meanwhile, the second switch assembly is in a second working state;
and controlling the first switch assembly to be in a second working state according to the second state of the charging enable signal, reducing the control voltage of the second switch assembly by a current comparison method, enabling the second switch assembly to be in the first working state, reducing the charging control voltage to be equal to the voltage signal of the battery, and turning off the external charging switch tube.
In one embodiment, when the charge enable signal is in the second state, the control voltage of the second switching element is clamped by the clamping circuit, so that the second switching element is always kept in the first working state.
Those skilled in the art should understand that the logic controls such as "high" and "low", "set" and "reset", "and gate" and "or gate", "non-inverting input" and "inverting input" in the logic controls referred to in the specification or the drawings may be exchanged or changed, and the subsequent logic controls may be adjusted to achieve the same functions or purposes as the above-mentioned embodiments.
The description and applications of the invention herein are illustrative and are not intended to limit the scope of the invention to the embodiments described above. The descriptions related to the effects or advantages in the specification may not be reflected in practical experimental examples due to uncertainty of specific condition parameters or influence of other factors, and the descriptions related to the effects or advantages are not used for limiting the scope of the invention. Variations and modifications of the embodiments disclosed herein are possible, and alternative and equivalent various components of the embodiments will be apparent to those skilled in the art. It will be clear to those skilled in the art that the present invention may be embodied in other forms, structures, arrangements, proportions, and with other components, materials, and parts, without departing from the spirit or essential characteristics thereof. Other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the invention.

Claims (19)

1. A charging control circuit for controlling a charging switch tube, the charging control circuit comprising:
the first switch component is connected with the input voltage signal at the first end, the charging enabling signal at the second end, the third end is coupled with the first end of the second switch component and the charging switch tube, and the first switch component is in a first working state based on the charging enabling signal and drives the charging switch tube to be conducted;
the first end of the second switch component is coupled with the charging switch tube, the second end of the second switch component is connected with a battery voltage signal, the third end of the second switch component is connected with the internal potential end of the first switch component, and the second switch component is in a first working state and drives the charging switch tube to be turned off based on the charging enabling signal and the internal potential signal provided by the first switch component; the input voltage signal is greater than the battery voltage signal.
2. The charge control circuit according to claim 1, wherein the first switch element and/or the second switch element are designed with back-to-back MOS transistors.
3. The charge control circuit according to claim 2, wherein the first switching element includes a first MOS transistor and a second MOS transistor, a drain of the first MOS transistor is connected to the input voltage signal, a gate of the first MOS transistor and a gate of the second MOS transistor are both connected to the charge enable signal, a source of the first MOS transistor and a source of the second MOS transistor are connected to form a common source terminal and are coupled to the third terminal of the second switching element as an internal potential terminal, and a drain of the second MOS transistor is coupled to the first terminal of the second switching element and the charge switching transistor.
4. The charging control circuit of claim 3, wherein the second switch component comprises a third MOS transistor and a fourth MOS transistor, a drain of the third MOS transistor is coupled to the third terminal of the first switch component and the charging switch transistor, a source of the third MOS transistor is connected to a source of the fourth MOS transistor, a gate of the third MOS transistor is connected to a gate of the fourth MOS transistor to form a common gate and is coupled to the common source terminal of the first switch component, and a drain of the fourth MOS transistor is connected to the battery voltage signal.
5. The charge control circuit of claim 4, further comprising a first current source and a third current source, wherein:
the first current source is coupled between a common grid of the second switch component and a common source end of the first switch component, the common grid of the second switch component is grounded through a fifth MOS tube, a source electrode of the fifth MOS tube is grounded, a drain electrode of the fifth MOS tube is coupled with the common grid of the second switch component, and the grid is accessed to a charging enabling signal through a phase inverter;
the third current source is coupled between the drain of the fourth MOS transistor and the ground.
6. The charge control circuit of claim 5, wherein the third current source is coupled to the fourth MOS transistor through a sixth MOS transistor, wherein a source of the sixth MOS transistor is coupled to the first terminal of the third current source, a drain of the sixth MOS transistor is coupled to the drain of the fourth MOS transistor, and a gate of the sixth MOS transistor is coupled to the internal voltage source.
7. The charge control circuit of claim 4, further comprising a first current source and a second resistor, wherein:
the first current source is coupled between a common grid of the second switch component and a common source end of the first switch component, the common grid of the second switch component is grounded through a fifth MOS tube, a source electrode of the fifth MOS tube is grounded, a drain electrode of the fifth MOS tube is coupled with the common grid of the second switch component, and the grid is accessed to a charging enabling signal through an inverter;
the second resistor is coupled between the drain of the fourth MOS transistor and the ground.
8. The charge control circuit of claim 7, wherein the second resistor is coupled to a fourth MOS transistor through a sixth MOS transistor, wherein a source of the sixth MOS transistor is coupled to a first terminal of the second resistor, a drain of the sixth MOS transistor is coupled to a drain of the fourth MOS transistor, and a gate of the sixth MOS transistor is coupled to the internal voltage source.
9. The charge control circuit according to any of claims 5-8, further comprising a second current source coupled between a fifth MOS transistor and ground, wherein a source of the fifth MOS transistor is coupled to a first terminal of the second current source.
10. The charge control circuit of claim 9, wherein the current of the second current source is substantially greater than the current of the first current source.
11. The charging control circuit of claim 9, further comprising a clamping circuit, wherein a first terminal of the clamping circuit is coupled to a drain of the fourth MOS transistor, a second terminal of the clamping circuit is coupled to a drain of the sixth MOS transistor, a third terminal and a fourth terminal of the clamping current are coupled to gates of the seventh MOS transistor and the eighth MOS transistor, respectively, a source of the seventh MOS transistor is connected to a source of the eighth MOS transistor, a drain of the seventh MOS transistor is coupled to the common gate of the second switching element, and a drain of the eighth MOS transistor is coupled to a drain of the fifth MOS transistor.
12. The charge control circuit according to claim 11, wherein the clamp circuit comprises a plurality of PMOS transistors, a gate and a drain of each PMOS transistor being connected, and a source and a drain of an adjacent PMOS transistor being connected; the grid electrode of the PMOS tube at the head end is coupled with the grid electrode of the seventh MOS tube, and the source electrode is coupled with the second end of the second switch component; the grid electrode of the PMOS tube at the tail end is coupled with the grid electrode of the eighth MOS tube, and the drain electrode of the PMOS tube is coupled with the drain electrode of the sixth MOS tube.
13. The charge control circuit of claim 11, wherein the clamp circuit comprises a plurality of NMOS transistors, a gate and a drain of each NMOS transistor are connected, and a source and a drain of an adjacent NMOS transistor are connected; the source electrode of the NMOS tube at the head end is coupled with the drain electrode of the fourth MOS tube, and the source electrode is coupled with the grid electrode of the seventh MOS tube; and the source electrode of the NMOS tube at the tail end is coupled with the grid electrode of the eighth MOS tube and the drain electrode of the sixth MOS tube.
14. The charging control circuit of claim 1, further comprising a level shifting module, wherein the second terminal of the first switch component is coupled to the charging enable signal through the level shifting module.
15. The charge control circuit of claim 1, further comprising a first resistor, wherein the third terminal of the first switch element and the first terminal of the second switch element are both coupled to the charge switch tube via the first resistor.
16. A lithium battery high-side driving circuit, comprising a charging switch tube and a charging control circuit as claimed in any one of claims 1 to 15, wherein the input terminal of the charging control circuit is connected to an input voltage signal and a charging enable signal, and the output terminal of the charging control circuit is coupled to the charging switch tube.
17. The lithium battery high-side driving circuit as claimed in claim 16, wherein the charging switch tube is a high-voltage transistor.
18. A charging control method is used for controlling a charging switch tube, and is characterized by comprising the following steps:
acquiring a charging enable signal, an input voltage signal and a battery voltage signal;
according to the first state of the charging enabling signal, the first switch assembly is controlled to be in a first working state, so that the charging control voltage and the control voltage of the second switch assembly are increased to be equal to the input voltage signal, the external charging switch tube is started, and meanwhile, the second switch assembly is in a second working state;
and controlling the first switch assembly to be in a second working state according to the second state of the charging enable signal, reducing the control voltage of the second switch assembly in a current comparison mode, enabling the second switch assembly to be in the first working state, reducing the charging control voltage to be equal to the voltage signal of the battery, and turning off the external charging switch tube.
19. The charge control method according to claim 18, wherein when the charge enable signal is in the second state, the control voltage of the second switching element is clamped by the clamp circuit, so that the second switching element is always kept in the first operating state.
CN202211068061.2A 2022-09-02 2022-09-02 Charging control circuit, control method and lithium battery high-side driving circuit Active CN115133629B (en)

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