CN115188320B

CN115188320B - Driving circuit, display driving chip, display device and electronic device

Info

Publication number: CN115188320B
Application number: CN202210821620.6A
Authority: CN
Inventors: 胡龙山
Original assignee: Chipone Technology Beijing Co Ltd
Current assignee: Chipone Technology Beijing Co Ltd
Priority date: 2022-07-12
Filing date: 2022-07-12
Publication date: 2025-07-22
Anticipated expiration: 2042-07-12
Also published as: CN115188320A; KR20240025643A; KR102795978B1; US20240265858A1; EP4387095A1; EP4387095A4; WO2024012453A1

Abstract

The driving circuit comprises a first stage circuit, a second stage circuit and an auxiliary circuit, wherein the first stage circuit is used for receiving a first input signal and a second input signal and amplifying the first input signal and the second input signal to obtain a first output signal and a second output signal which are output to the second stage circuit, the second stage circuit is used for outputting a third output signal to drive a load according to the first output signal and the second output signal, the second stage circuit is connected with the first stage circuit through a Miller capacitor, and the auxiliary circuit is connected with the first stage circuit and the second stage circuit and used for reducing output impedance of the first stage circuit. The driving circuit is used as a Miller compensation driving circuit, and can meet the requirements of connection with any load capacitance and smooth transient response.

Description

Driving circuit, display driving chip, display device and electronic device

Technical Field

The disclosure relates to the field of integrated circuits, and in particular relates to a driving circuit, a display driving chip, a display device and an electronic device.

Background

An operational amplifier is a circuit unit with a very high amplification factor. It is widely used in the integrated circuit field, so that the design needs to consider the problems possibly occurring in different application scenes. A common problem is that the load capacitance of the operational amplifier is uncertain. For example, when an operational amplifier is used in a driving circuit for driving an LED display, many LEDs can be driven, and the number of LEDs is determined by a user, so that when designing the operational amplifier, it is required to consider that the load capacitance of the operational amplifier can be approximately any value, and meanwhile, in some application scenarios, the operational amplifier can be used as a gain amplifier. The gain amplifier requires that the output and input have a certain amplification, and therefore another problem is that the transient response of the operational amplifier (the process of the output changing to a steady state when the input changes) should be smooth, i.e. the value of the output voltage does not overshoot, which typically requires a phase margin of more than 60 °. This is a very difficult thing for a miller-compensated op amp.

Therefore, designing a miller-compensated driving circuit that can meet the above requirements is a research focus in the art.

Disclosure of Invention

In view of this, the present disclosure proposes a driving circuit, a display driving chip, a display device, and an electronic device, which can meet the requirements of connecting arbitrary load capacitance and having smooth transient response as a miller-compensated driving circuit.

According to one aspect of the disclosure, a driving circuit is provided, and the driving circuit comprises a first stage circuit, a second stage circuit and an auxiliary circuit, wherein the first stage circuit is used for receiving a first input signal and a second input signal, amplifying the first input signal and the second input signal to obtain a first output signal and a second output signal, outputting the first output signal and the second output signal to the second stage circuit, outputting a third output signal to drive a load according to the first output signal and the second output signal, the second stage circuit is further connected with the first stage circuit through a miller capacitor, and the auxiliary circuit is connected with the first stage circuit and the second stage circuit and used for reducing output impedance of the first stage circuit.

In one possible implementation manner, the auxiliary circuit includes a first resistor and a second resistor, the first output signal is output by a first end of the first stage circuit, the second output signal is output by a second end of the first stage circuit, the first resistor is connected between a power supply voltage and the first end of the first stage circuit, and the second resistor is connected between the second end of the first stage circuit and ground.

In one possible implementation, the auxiliary circuit further includes a first transistor and a second transistor, the first transistor and the first resistor are connected in series between a power supply voltage and a first end of the first stage circuit, a current flowing through the first resistor also flows through a first pole and a second pole of the first transistor, a gate of the first transistor is connected to one of the first pole and the second pole of the first transistor far from the power supply voltage, the first transistor is used for reducing the current flowing through the first resistor, the second transistor and the second resistor are connected in series between a second end of the first stage circuit and ground, the current flowing through the second resistor also flows through the first pole and the second pole of the second transistor, and a gate of the second transistor is connected to one of the first pole and the second pole far from ground.

In one possible implementation manner, the auxiliary circuit further includes a third transistor and a fourth transistor, the third transistor and the first transistor, the first resistor being connected in series between a power supply voltage and a first end of the first stage circuit, a current flowing through the first resistor also flowing through a first pole and a second pole of the third transistor, a gate of the third transistor receiving a first bias signal; the third transistor is used for controlling the maximum value of the current flowing through the first resistor to be smaller than the current value of the tail current of the first stage circuit, the fourth transistor, the second transistor and the second resistor are connected in series between the second end of the first stage circuit and ground, the current flowing through the second resistor also flows through the first pole and the second pole of the fourth transistor, the grid electrode of the fourth transistor receives a second bias signal, and the fourth transistor is used for controlling the maximum value of the current flowing through the second resistor to be smaller than the current value of the tail current of the first stage circuit.

In one possible implementation, the first bias signal causes the third transistor to operate in a linear region, the first output signal decreases, the current flowing through the first resistor increases, the first output signal decreases to cause the third transistor to operate in a saturated region, the current flowing through the first resistor reaches a maximum value, the second bias signal causes the fourth transistor to operate in a linear region, the second output signal increases, the current flowing through the second resistor increases, and the second output signal increases to cause the fourth transistor to operate in a saturated region, the current flowing through the second resistor reaches a maximum value.

In one possible implementation manner, the second stage circuit includes a fifth transistor and a sixth transistor, a first pole of the fifth transistor is connected to a power supply voltage, a second pole is used as a first end of the second stage circuit, the third output signal is output, a gate is used as a second end of the second stage circuit, the first output signal is received, a first pole of the sixth transistor is connected to a second pole of the fifth transistor, a second pole of the sixth transistor is connected to ground, a gate is used as a third end of the second stage circuit, the second output signal is received, polarities of the fifth transistor and the sixth transistor are different, polarities of the fifth transistor and the first transistor are the same, and polarities of the sixth transistor and the second transistor are the same.

According to another aspect of the present disclosure, there is provided a display driving chip including a plurality of display units and at least one driving circuit described above, the plurality of display units being connected to a third terminal of a second stage circuit of the driving circuit.

According to another aspect of the present disclosure, there is provided a display device including the above display driving chip.

In one possible implementation, the display unit includes a display panel including at least one of a liquid crystal display panel, a micro light emitting diode display panel, a mini light emitting diode display panel, a quantum dot light emitting diode display panel, an organic light emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel, and a small-pitch display panel.

According to another aspect of the present disclosure, there is provided an electronic device including the display device described above.

According to the driving circuit, a first input signal and a second input signal are received through a first stage circuit and amplified, a first output signal and a second output signal are obtained and output to the second stage circuit, amplification function can be achieved, bias is provided for the second stage circuit, a third output signal is output through the second stage circuit according to the first output signal and the second output signal, a load can be driven, the second stage circuit is further connected with the first stage circuit through a Miller capacitor, therefore the driving circuit of the embodiment of the disclosure is a Miller compensation driving circuit, the auxiliary circuit is connected with the first stage circuit and the second stage circuit, output impedance of the first stage circuit is reduced, the minimum value of phase margin of the driving circuit is increased in the process of load capacitor change, transient response smoothness is achieved, and the driving circuit capable of realizing Miller compensation meets the requirements of being connected with any load capacitor and transient response smoothness.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features and aspects of the present disclosure and together with the description, serve to explain the principles of the disclosure.

Fig. 1 shows an exemplary structure diagram of a prior art two-stage operational amplifier.

Fig. 2 illustrates an exemplary structural diagram of a driving circuit according to an embodiment of the present disclosure.

Fig. 3 shows an exemplary schematic configuration of the first stage circuit 210 according to an embodiment of the present disclosure.

Fig. 4 shows an exemplary block diagram of the second stage circuit 220 according to an embodiment of the present application.

Fig. 5 illustrates an exemplary block diagram of auxiliary circuit 230 according to an embodiment of the present disclosure.

Fig. 6 illustrates another exemplary block diagram of auxiliary circuit 230 according to an embodiment of the present disclosure.

Fig. 7 illustrates another exemplary block diagram of an auxiliary circuit 230 according to an embodiment of the present disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

In addition, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.

As shown in fig. 1, the amplifier may be divided into an input stage circuit for providing a large voltage gain and an output stage circuit for providing a large current driving capability for a driving circuit. A miller capacitance Cm is connected between the input end and the output end of the output stage circuit in a bridging mode and is used for realizing phase compensation of the pole of the operational amplifier. Where VN and VP are input signals of the two-stage operational amplifier, OUT is an output signal of the two-stage operational amplifier, VB is a bias voltage, AVDD is a power supply voltage, CL is a load capacitance, and Cm is a Miller capacitance.

When designing an operational amplifier, a specific value of the load capacitance CL in practical use of the operational amplifier cannot be determined in advance. The operational amplifier may be designed with the load capacitance in mind and approximately at any value. In some scenarios the op-amp is used as a gain amplifier, so the op-amp design also takes into account transient response smoothing, i.e. no overshoot of the output signal (typically requiring a phase margin of more than 60 °). This is a very difficult thing for prior art mueller capacitance compensated op-amps.

In order to solve the technical problem, the disclosure provides a driving circuit, a display driving chip, a display device and an electronic device, wherein the driving circuit is used as a miller compensation driving circuit, and can meet the requirements of connecting any load capacitance and having smooth transient response.

As shown in fig. 2, in one possible implementation, the drive circuit includes a first stage circuit 210, a second stage circuit 220 and an auxiliary circuit 230,

The first stage circuit 210 is configured to receive and amplify a first input signal Vin1 and a second input signal Vin2, obtain a first output signal Vout1 and a second output signal Vout2, and output the first output signal Vout1 and the second output signal Vout2 to the second stage circuit 220.

The first stage circuit 210 of the disclosed embodiment may be a voltage gain amplifying circuit implemented based on the prior art. Fig. 3 shows an exemplary schematic configuration of the first stage circuit 210 according to an embodiment of the present disclosure. The circuit 210 includes a differential input unit, a tail current source and a voltage amplifying unit, the differential input unit includes P-type transistors T1 and T2, gates of the transistors T1 and T2 are connected to differential input signals (a first input signal Vin1 and a second input signal Vin 2), sources of the transistors T1 and T2 are connected to ground through the tail current source, drains of the transistors T1 and T2 are connected to the voltage amplifying unit, so as to perform signal amplifying processing through a current mirror structure formed by the transistors in the voltage amplifying unit, and provide bias voltages (a first output signal Vout1 and a second output signal Vout 2) to the second stage circuit 220. The tail current source may be implemented by a P-type transistor T3, where a gate of the transistor T3 may receive a control signal for controlling an output of the tail current I3, a source may be connected to ground, and a drain may be connected to a first pole of the transistors T1, T2. VDD denotes a power supply voltage.

It will be appreciated by those skilled in the art that the configuration of fig. 3 is only one example of the first stage circuit 210, and the first stage circuit 210 may also include more structures that are available in the prior art, as long as amplification of the first input signal Vin1 and the second input signal Vin2 can be achieved, and the first output signal Vout1 and the second output signal Vout2 are output to provide a bias for the second stage circuit, and the specific configuration of the first stage circuit 210 is not limited in this disclosure.

The second stage circuit 220 is configured to output a third output signal Vout3 to drive a load CL according to the first output signal Vout1 and the second output signal Vout2, and the second stage circuit 220 is further connected to the first stage circuit 210 through miller capacitors C1 and C2.

The second stage 220 may be implemented based on prior art techniques. Fig. 4 shows an exemplary block diagram of the second stage circuit 220 according to an embodiment of the present application. As shown in fig. 4, the circuit 220 may include transistors T5 and T6 with different polarities, for example, the transistor T5 is a PMOS transistor and the transistor T6 is an NMOS transistor, a first electrode (source) of the transistor T5 is connected to the power voltage, a gate receives the first output signal Vout1, a first electrode (source) of the transistor T6 is connected to the ground, and a gate receives the second output signal Vout2. The second stage (drain) of the transistor T5 and the second stage (drain) of the transistor T6 are connected and serve as a third terminal of the second stage circuit 220, which is further connected to the load CL, i.e. the third output signal Vout3 is available as a signal provided to the load CL. The second stage (drain) of the transistor T5 and the second stage (drain) of the transistor T6 are further connected to the first stage circuit 210 through miller capacitors C1 and C2, respectively, so as to implement phase compensation of the circuit poles, and a specific compensation manner thereof may be implemented based on the prior art, which is not described herein again.

An auxiliary circuit 230 (including 230a and 230 b) is coupled to the first stage circuit 210 and the second stage circuit 220 for reducing the output impedance of the first stage circuit 210.

The output impedance of the first stage 210 is related to the phase margin of the driving circuit, and the relationship between the output impedance and the phase margin is such that the smaller the output impedance of the first stage 210, the larger the minimum value of the phase margin of the driving circuit is during the change of the load capacitance CL. And when the phase margin is greater than 60%, the transient response of the driving circuit is considered to be smooth, so that the output impedance of the first stage circuit 210 is reduced by the auxiliary circuit 230, and the transient response of the driving circuit can be optimized.

The auxiliary circuit 230 in the embodiments of the present disclosure has various structures. Several exemplary configurations of auxiliary circuits 230 and their advantages are described below in connection with fig. 5-7, respectively.

As shown in fig. 5, in one possible implementation, the auxiliary circuit 230 includes a first resistor R1 and a second resistor R2, the first output signal Vout1 is output by the first end a1 of the first stage circuit 210, the second output signal Vout2 is output by the second end a2 of the first stage circuit 210, the first resistor R1 is connected between the power supply voltage VDD and the first end a1 of the first stage circuit 210, and the second resistor R2 is connected between the second end a2 of the first stage circuit 210 and ground.

For example, as can be seen from fig. 3 and 4, the first stage circuit 210 has two output terminals a1 and a2, so that when designing the auxiliary circuit 230, it is necessary to consider reducing the output impedance of the two output terminals a1 and a2, respectively. In the simplest manner, the two output terminals a1 and a2 are connected to resistors, respectively, that is, as shown in fig. 5, the first resistor R1 is connected between the first terminal a1 of the first stage circuit 210 and the power supply voltage VDD, and the second resistor R2 is connected between the second terminal a2 of the first stage circuit 210 and the ground GND. The auxiliary circuit 230 (including 230a and 230 b) may include a first resistor R1 and a second resistor R2. The embodiment of the present disclosure does not limit the resistance values of the first resistor R1 and the second resistor R2. In this case, the auxiliary circuit 230 is relatively simple in structure, easy to implement and low in cost.

However, in the circuit shown in fig. 5, due to the presence of the first resistor R1 and the second resistor R2 in the auxiliary circuit 230 (including 230a and 230 b), current flows through the first resistor R1 and the second resistor R2. The gate-source voltage of the transistor T5 is related to the threshold voltage thereof, the source voltage is the power supply voltage VDD, and therefore the gate voltage of the transistor T5 is related to the threshold voltage thereof, and the current I1 flowing through the first resistor R1 should be equal to the ratio of the difference between the power supply voltage VDD and the gate voltage of the transistor T5 to the resistance of the first resistor R1, so the current I1 flowing through the first resistor R1 can be considered as a reference to the threshold voltage of the transistor T5. Similarly, the current I2 flowing through the second resistor R2 can be considered to be based on the threshold voltage of the transistor T6. The transistor T5 and the transistor T6 are two transistors with different polarities, so that the threshold voltages of the two transistors may be inconsistent, which may cause the current I1 flowing through the first resistor R1 and the current I2 flowing through the second resistor R2 to be unequal, and when the difference value of the two currents is larger, a larger offset voltage may be introduced, thereby reducing the stability of the driving circuit.

Accordingly, the present disclosure proposes another design of the auxiliary circuit 230. Fig. 6 illustrates another exemplary block diagram of auxiliary circuit 230 according to an embodiment of the present disclosure.

As shown in fig. 6, in one possible implementation, the auxiliary circuit 230 further includes a first transistor M1 and a second transistor M2,

The first transistor M1 and the first resistor R1 are connected in series between the power supply voltage VDD and the first end a1 of the first stage circuit 210, and the current I1 flowing through the first resistor also flows through the first pole M11 and the second pole M12 of the first transistor M1, wherein the grid electrode M13 of the first transistor M1 is connected with one of the first pole M11 and the second pole M12 of the first transistor M1, which is far away from the power supply voltage VDD;

The second transistor M2 and the second resistor R2 are connected in series between the second terminal a2 of the first stage circuit 120 and the ground, the current I2 flowing through the second resistor R2 also flows through the first pole M21 and the second pole M22 of the second transistor M2, the gate M13 of the second transistor M2 is connected to one of the first pole M21 and the second pole M22 of the second transistor M2, which is far from the ground, and the second transistor M2 is used for reducing the current I2 flowing through the second resistor R2.

In the example of fig. 6, the first transistor M1 may be a P-type transistor, the first pole M11 of the first transistor M1 may be a drain electrode, the first resistor R1 may be connected, the second pole M12 may be a source electrode, the power supply voltage VDD may be connected, one far from the power supply voltage VDD may be the first pole M11, the first resistor may be further connected to the first end a1 of the first stage circuit, the second transistor M1 may be an N-type transistor, the first pole M21 of the second transistor M2 may be a source electrode, the second pole M22 may be a drain electrode, the second resistor R2 may be connected, the one far from the ground may be the second pole M22, and the second resistor may be further connected to the second end a2 of the first stage circuit. Those skilled in the art will appreciate that the first and second transistors may also be transistors of other polarities, as this disclosure is not limited in this regard.

It will be appreciated that, in addition to the connection manner shown in fig. 6, the first resistor may be connected to the power supply voltage, the first transistor may be connected to the first end a1 of the first stage circuit, the second resistor may be connected to the ground, and the second transistor may be connected to the second end a2 of the first stage circuit, so long as the connection manner that the first transistor M1 and the first resistor R1 are connected in series between the power supply voltage VDD and the first end a1 of the first stage circuit 210, and the connection manner that the second transistor M2 and the second resistor R2 are connected in series between the second end a2 of the first stage circuit 120 and the ground is not limited in this disclosure.

The principle of the auxiliary circuit shown in fig. 6 to reduce the current flowing through the first resistor and the current flowing through the second resistor will be described below in connection with the construction of the second stage circuit.

In one possible implementation, the second stage circuit includes a fifth transistor T5 and a sixth transistor T6,

The first pole of the fifth transistor T5 is connected to the power voltage VDD, the second pole is used as the first terminal b1 of the second stage circuit 220, the third output signal is output, the gate is used as the second terminal b2 of the second stage circuit 220, and the first output signal Vout1 is received;

The first pole of the sixth transistor T6 is connected with the second pole a2 of the fifth transistor T5, the second pole is connected with the ground, the grid electrode is used as the third terminal of the second stage circuit, and the second output signal Vout2 is received;

The polarities of the fifth transistor T5 and the sixth transistor T6 are different, the polarities of the fifth transistor T5 and the first transistor M1 are the same, and the polarities of the sixth transistor T6 and the second transistor M2 are the same.

For example, the fifth transistor is the transistor T5 described above, the sixth transistor is the transistor T6 described above, the fifth transistor T5 and the sixth transistor T6 are transistors with different polarities, the polarities of the fifth transistor T5 and the first transistor M1 may be the same, the polarities of the sixth transistor T6 and the second transistor M2 may be the same, for example, the fifth transistor T5 and the first transistor M1 may be P-type transistors, and the sixth transistor T6 and the second transistor M2 may be N-type transistors in the embodiment of the disclosure.

When the first transistor M1 is a P-type transistor as shown in fig. 6, the threshold voltage of the first transistor M1 is the same as that of the fifth transistor T5 (the threshold voltages of the transistors with the same polarity are the same), one of the first electrode M11 and the second electrode M12 (the second electrode M12 in the example of fig. 6) close to the power supply voltage VDD is regarded as a cathode of the diode, the other electrode (the first electrode M11 in the example of fig. 6) is regarded as an anode of the diode, that is, the first transistor M1 is regarded as a diode and is reversely connected in the circuit, and the first transistor M1 is connected in series with the first resistor R1, so that in this case, the current I1 flowing through the first resistor R1 is very small, and in the same way, the second transistor M2 is regarded as a diode as being connected in the manner shown in fig. 6, when the second transistor M2 is an N-type transistor, the threshold voltage of the same as that of the sixth transistor M6 (the threshold voltages of the same polarity are the transistor) is also the second electrode M2 is regarded as a cathode of the diode, and the second electrode M2 is regarded as a reverse current flowing through the second electrode M2 is also connected in series with the circuit, that is regarded as a reverse resistor M2, and is different from the second electrode 2. Since the current I1 flowing through the first resistor R1 and the current I2 flowing through the second resistor R2 are small, even if I1 and I2 are not equal, the difference therebetween is not large, and in this case, the offset voltage of the driving circuit can be reduced to be low, thereby improving the stability of the driving circuit.

However, the circuit shown in fig. 6 is more suitable for a driving circuit with large quiescent current, and if the application scenario requires a driving circuit with micro power consumption, the tail current I3 in the first stage circuit needs to be designed to be smaller, and the circuit in fig. 6 may cause the voltage conversion rate (slew rate) of the driving circuit to be smaller. The reason is that when the driving circuit changes the voltage, if the output voltage (the third output signal Vout 3) is to be made high, it is necessary to make the value of the first output signal Vout1 low (or make the value of the second output signal Vout2 high), in the circuit of fig. 6, the tail current I3 is mirrored completely to pull the first output signal Vout1 low (or pull the second output signal Vout2 high), but when the first output signal Vout1 is pulled low (or the second output signal Vout2 is pulled high), the current I1 flowing through the first resistor R1 (or the current I2 flowing through the second resistor R2) is increased, and when the current I1 flowing through the first resistor (or the current I2 flowing through the second resistor R2) is increased as much as the tail current I3, the first output signal Vout2 is not pulled down (or the second output signal Vout2 is not pulled high) any more, which finally results in a reduced voltage conversion rate of the driving circuit.

Thus, the present disclosure proposes another design approach of the auxiliary circuit. Fig. 7 illustrates another exemplary block diagram of an auxiliary circuit 230 according to an embodiment of the present disclosure.

As shown in fig. 7, in one possible implementation, the auxiliary circuit 230 further includes a third transistor M3 and a fourth transistor M4,

The third transistor M3, the first transistor M1 and the first resistor R1 are connected in series between the power supply voltage VDD and the first end a1 of the first stage circuit 210, and the current flowing through the first resistor R1 also flows through the first pole M31 and the second pole M32 of the third transistor M3, and the gate M33 of the third transistor M3 receives the first bias signal VBP;

The fourth transistor M4 and the second transistor, the second resistor R2 are connected in series between the second end a2 of the first stage 210 and the ground, the current I2 flowing through the second resistor R2 also flows through the first pole M41 and the second pole M42 of the fourth transistor M4, the gate of the fourth transistor M4 receives the second bias signal VBN, and the maximum value of the current I2 flowing through the fourth transistor M4 for controlling the second resistor R2 is smaller than the current value of the tail current I3 of the first stage 210.

In the example of fig. 7, the first transistor M1 may be a P-type transistor, the first pole M11 of the first transistor M1 may be a drain electrode connected to the first resistor R1, the second pole M12 may be a source electrode connected to the first pole M31 of the third transistor M3, the third transistor M3 may be a P-type transistor, the first pole M31 of the third transistor M3 may be a drain electrode, the second pole M32 may be a source electrode connected to the power supply voltage VDD. The second transistor M1 may be an N-type transistor, the first pole M21 of the second transistor M2 may be a source electrode, the second pole M42 connected to the fourth transistor M4 may be a drain electrode, and the second resistor R2 may be connected, the fourth transistor M4 may be an N-type transistor, the first pole M41 of the fourth transistor M4 may be a source electrode, and the second pole M42 may be a drain electrode. Those skilled in the art will appreciate that the first transistor, the second transistor, the third transistor, and the fourth transistor may also be transistors of other polarities, as this disclosure is not limited in this regard.

It is understood that, in addition to the connection manner shown in fig. 7, the first resistor may be connected in series between the first transistor and the third transistor, the second resistor may be connected in series between the fourth transistor and the second transistor, etc., so long as the connection manner that the third transistor M3 and the first transistor M1, the first resistor R1 are connected in series between the power supply voltage VDD and the first terminal a1 of the first stage circuit 210, and the connection manner that the fourth transistor M4 and the second transistor, the second resistor R2 are connected in series between the second terminal a2 of the first stage circuit 210 and the ground is satisfied, the specific connection manner of the third transistor M3 and the first transistor M1, the first resistor R1, and the specific connection manner of the fourth transistor M4 and the second transistor, the second resistor R2 are not limited in this disclosure.

An exemplary manner in which the third transistor M3 and the fourth transistor M4 control the current I1 flowing through the first resistor R1 and the current I2 flowing through the second resistor R2 is described below in connection with fig. 7.

In one possible implementation, the first bias signal VBP causes the third transistor M3 to operate in the linear region, the first output signal Vout1 decreases, and the current I1 flowing through the first resistor R1 increases;

the first output signal Vout1 decreases to a level at which the current I1 flowing through the first resistor R1 reaches a maximum value when the third transistor M3 is operated in the saturation region;

The second bias signal VBN causes the fourth transistor M4 to operate in the linear region, the second output signal Vout2 increases, and the current I2 flowing through the second resistor R2 increases;

the second output signal Vout2 rises to make the fourth transistor M4 operate in the saturation region, and the current I2 flowing through the second resistor R2 reaches a maximum value.

For example, the first bias signal VBP and the second bias signal VBN may be set to fixed values, generated by a bias circuit (not shown) capable of stably outputting a bias voltage according to the related art, and supplied to the auxiliary circuit 230 (including 230a and 230 b). In a normal state, the third transistor M3 and the fourth transistor M4 are respectively pressed into the deep linear region by the first bias signal VBP and the second bias signal VBN, at this time, the current I1 flowing through the first resistor R1 and the current I2 flowing through the second resistor R2 are very small, so that no offset voltage is introduced into the driving circuit, when the driving circuit needs to perform voltage conversion, the voltage value of the first output signal Vout1 is taken as an example, the voltage value of the first output signal Vout1 is reduced, the current I1 flowing through the first resistor R1 is increased, but when the voltage value of the first output signal Vout1 is reduced to a certain value, the third transistor M3 enters the saturation region, at this time, the current I1 flowing through the first resistor R1 is not increased any more, that is, at this time, the current I1 flowing through the first resistor R1 reaches a maximum value, and as long as the maximum value is smaller than the tail current I3 of the first stage circuit 210, the voltage value of the first output signal Vout1 can be continuously reduced, so that the voltage conversion rate of the driving circuit is not reduced.

Similarly, taking the second output signal Vout2 as an example, the voltage value of the second output signal Vout2 increases, but when the voltage value of the second output signal Vout2 increases to a certain value, the fourth transistor M4 enters the saturation region, and the current I2 flowing through the second resistor R2 does not increase any more, that is, the current I2 flowing through the second resistor R2 reaches the maximum value, and as long as the maximum value is smaller than the tail current I3 of the first stage circuit 210, the voltage value of the second output signal Vout2 can continue to decrease, so that the problem of decreasing the voltage conversion rate of the driving circuit is not introduced.

It will be appreciated by those skilled in the art that the configuration of fig. 5-7 is merely an example of the auxiliary circuit 230, and that the auxiliary circuit 230 may include more configurations, so long as the reduction of the output impedance of the first stage circuit 210 can be achieved, and the specific configuration of the auxiliary circuit 230 is not limited by the present disclosure.

The present disclosure further provides a display driving chip, which includes a plurality of display units and at least one driving circuit described above, where the plurality of display units are connected to a third end of the second stage circuit 220 of the driving circuit. The third terminal of the second stage circuit 220 may be a terminal of the second stage circuit 220 connected to a load, that is, a terminal of the third output signal Vout 3. The plurality of display units are the loads described above, and the capacitance values thereof are the load capacitances of the driving circuit.

The present disclosure also provides a display device including the above display driving chip. The display driving chip according to the embodiment of the invention can be formed into a general driving chip and can be suitable for display panels with different subpixel arrangements, so that the design cost and the manufacturing cost can be reduced.

The disclosure also provides an electronic device comprising the display device.

Exemplary electronic devices in this embodiment include, but are not limited to, desktop computers, televisions, mobile devices with large-sized screens, such as cell phones, tablet computers, and other common electronic devices that require multiple chips to be cascaded to achieve driving.

The electronic device may also be, by way of example, a User Equipment (UE), a Mobile device, a User terminal, a handheld device, a computing device, or a vehicle-mounted device, etc., and some examples of terminals are a display, a Smart Phone or portable device, a Mobile Phone, a tablet, a laptop, a palmtop, a Mobile internet device (Mobile Internetdevice, MID), a wearable device, a Virtual Reality (VR) device, an augmented Reality (Augmentedreality, AR) device, a wireless terminal in industrial control (Industrial Control), a wireless terminal in unmanned (SELFDRIVING), a wireless terminal in teleoperation (Remote medical Surgery), a wireless terminal in Smart grid (SMART GRID), a wireless terminal in transportation security (Transportation Safety), a wireless terminal in Smart city (SMART CITY), a wireless terminal in Smart Home (rt Home), a wireless terminal in the internet of vehicles, etc. For example, the server may be a local server or a cloud server.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the technical improvements in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A driving circuit, characterized in that it comprises a first-stage circuit, a second-stage circuit and an auxiliary circuit,

The first stage circuit is used to receive and amplify a first input signal and a second input signal, obtain a first output signal and a second output signal, and output the signals to the second stage circuit;

The second stage circuit is used to output a third output signal to drive a load according to the first output signal and the second output signal; the second stage circuit is also connected to the first stage circuit via a Miller capacitor;

The auxiliary circuit is connected to the first stage circuit and the second stage circuit, and is used to reduce the output impedance of the first stage circuit;

The auxiliary circuit includes a first resistor and a second resistor, the first output signal is output from the first end of the first stage circuit, the second output signal is output from the second end of the first stage circuit, the first resistor is connected between the power supply voltage and the first end of the first stage circuit; the second resistor is connected between the second end of the first stage circuit and the ground;

The auxiliary circuit also includes a first transistor and a second transistor, the first transistor and the first resistor are connected in series between the power supply voltage and the first end of the first-level circuit, and the current flowing through the first resistor also flows through the first electrode and the second electrode of the first transistor; the gate of the first transistor is connected to the one of the first electrode and the second electrode of the first transistor that is far away from the power supply voltage; the first transistor is used to reduce the current flowing through the first resistor; the second transistor and the second resistor are connected in series between the second end of the first-level circuit and the ground, and the current flowing through the second resistor also flows through the first electrode and the second electrode of the second transistor; the gate of the second transistor is connected to the one of the first electrode and the second electrode of the second transistor that is far away from the ground; the second transistor is used to reduce the current flowing through the second resistor.

2. The driving circuit according to claim 1, characterized in that the auxiliary circuit further comprises a third transistor and a fourth transistor,

The third transistor, the first transistor and the first resistor are connected in series between a power supply voltage and a first end of the first stage circuit, the current flowing through the first resistor also flows through a first electrode and a second electrode of the third transistor, and the gate of the third transistor receives a first bias signal; the third transistor is used to control the maximum value of the current flowing through the first resistor to be less than the current value of the tail current of the first stage circuit;

The fourth transistor, the second transistor and the second resistor are connected in series between the second end of the first-stage circuit and the ground, the current flowing through the second resistor also flows through the first electrode and the second electrode of the fourth transistor, and the gate of the fourth transistor receives a second bias signal; the fourth transistor is used to control the maximum value of the current flowing through the second resistor to be less than the current value of the tail current of the first-stage circuit.

3. The driving circuit according to claim 2, characterized in that:

When the first bias signal causes the third transistor to operate in a linear region, the first output signal decreases and the current flowing through the first resistor increases;

When the first output signal decreases to make the third transistor work in a saturation region, the current flowing through the first resistor reaches a maximum value;

When the second bias signal causes the fourth transistor to operate in a linear region, the second output signal increases, and the current flowing through the second resistor increases;

When the second output signal increases to make the fourth transistor operate in a saturation region, the current flowing through the second resistor reaches a maximum value.

4. The driving circuit according to any one of claims 1 to 3, characterized in that the second stage circuit comprises a fifth transistor and a sixth transistor,

The first electrode of the fifth transistor is connected to the power supply voltage, the second electrode serves as the first end of the second stage circuit to output the third output signal, and the gate serves as the second end of the second stage circuit to receive the first output signal;

The first electrode of the sixth transistor is connected to the second electrode of the fifth transistor, the second electrode is connected to the ground, and the gate serves as the third terminal of the second stage circuit to receive the second output signal;

The fifth transistor and the sixth transistor have different polarities, the fifth transistor and the first transistor have the same polarity, and the sixth transistor and the second transistor have the same polarity.

5. A display driver chip, characterized in that it comprises a plurality of display units and at least one driving circuit according to any one of claims 1 to 4, wherein the plurality of display units are connected to the third end of the second-stage circuit of the driving circuit.

6. A display device, comprising the display driver chip according to claim 5.

7. The display device according to claim 6 is characterized in that the display unit includes a display panel, and the display panel includes at least one of a liquid crystal display panel, a micro light emitting diode display panel, a light emitting diode display panel, a mini light emitting diode display panel, a quantum dot light emitting diode display panel, an organic light emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel and a small pitch display panel.

8. An electronic device, characterized by comprising the display device according to claim 6 or 7.