CN115188407B - Memory device - Google Patents

Abstract

The invention provides a memory, which is used for transmitting a data input signal of a preset mode to a comparator when calibration is started, applying different DFE bias currents to any one of a first DFE part, a second DFE part, a third DFE part and a fourth DFE part for a plurality of times, obtaining the width of a corresponding data eye window when each application is performed, comparing the widths of the data eye windows to obtain the data eye window with the largest width, setting the DFE bias current corresponding to the data eye window with the largest width as the optimal DFE bias current, and setting the optimal DFE bias current applied to the DFE part through automatic calibration, thereby maximally restraining adverse effects of a post mark on a subsequent pulse signal and reducing possibility of false judgment.

Description

Memory device

Technical Field

The present invention relates to a memory.

Background

As for memories, the read-write function can be divided into read-only memories (ROMs) and random-access memories (RAMs). The content stored in the read-only memory is a semiconductor memory which can only be read and written, while the random read-write memory is a memory which can be read and written. In addition, the random access memory can be further classified into SRAM (static) and DRAM (dynamic). The SRAM comprises SDR SRAM, DDR SRAM, QDR SRAM, ZBT SRAM and the like, and the DRAM comprises SDRAM, DDR DRAM and RDRAM.

DRAM is a clock synchronous memory that operates with reference to a clock signal from a processor. The command signal for defining the action and the address signal for designating the memory cell are transmitted in parallel and synchronized with the rising edge of the clock. In DDR data transfer, a DQ Strobe (DQs) signal is used as a reference instead of a clock, and data transfer is performed through a DQ bus. The command and address signals are synchronized to only the rising edge of the clock, while the data signals are synchronized to the rising and falling edges of the DQS. Clock, command signals, address signals are input to the DRAM unidirectionally from the processor, while DQS and DQ are bi-directional, input to the DRAM upon writing and output from the DRAM upon reading.

Disclosure of Invention

In general, the controller and the memory (DRAM in fig. 1) need to be connected by an interconnect. As shown in fig. 1, the pulse signal sent by the controller is a rectangular pulse, and the pulse response of the receiving end of the DRAM is a waveform shown in the lower part of fig. 1 due to the middle interconnection, that is, a post mark (fig. 1 corresponds to a DFE with 4 taps, and if the DFE is with 1 tap), such as T1, T2, T3, and T4, appears on the right side of the main mark T0, and if the post mark is with 1 tap, only one T1 is provided, the post mark (post-cursor) may have an adverse effect on the subsequent pulse signal, and may cause erroneous judgment. In the present invention, DFE is an abbreviation for decision feedback equalizer (Decision Feedback Equalizer).

The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a memory which transmits a data input signal of a predetermined pattern to a comparator at the time of starting calibration, applies different DFE bias currents to any one of a first DFE section, a second DFE section, a third DFE section, and a fourth DFE section a plurality of times, obtains a width of a data eye corresponding to each application, compares the widths of the data eye to obtain a data eye having a maximum width, and sets the DFE bias current corresponding to the data eye having the maximum width as an optimal DFE bias current, thereby enabling the optimal DFE bias current applied to the DFE section to be set by automatic calibration, and minimizing adverse effects of a post-symbol on a subsequent pulse signal, thereby reducing the possibility of erroneous judgment.

A memory according to a first aspect of the present invention includes an input reception unit including a comparator that compares an input data input signal with a reference voltage signal and outputs a data output signal to the first DFE portion, the second DFE portion, the third DFE portion, the fourth DFE portion, and a calibration unit, and that divides a data clock signal into a first data clock signal, a second data clock signal, a third data clock signal, and a fourth data clock signal, a first amplifier, a second amplifier, a third amplifier, and a fourth amplifier, the comparator compares an input data input signal with a reference voltage signal and outputs a data output signal to the first DFE portion, the second DFE portion, the third DFE portion, the fourth DFE portion, and the input reception unit divides a data clock signal into a first data clock signal, a second data clock signal, a third data clock signal, and a fourth data clock signal, the first DFE portion corrects the data output signal based on the data output signal and a fourth data output signal outputted from the fourth amplifier, and outputs a first corrected data output signal to the first amplifier, the second DFE portion corrects the data output signal and the data output signal based on the first data clock signal and the second data clock signal and the fourth data clock signal, and the data clock signal and the first DFE portion corrects the data output signal and the data clock signal, the third DFE section corrects the data output signal based on the data output signal and the second data output partial signal output from the second amplifier and outputs a third corrected data output signal to the third amplifier, the third amplifier amplifies the third corrected data output signal based on a third data clock partial signal and outputs a third data output partial signal to the fourth DFE section and the memory cell, the fourth DFE section corrects the data output signal based on the data output signal and the third data output partial signal output from the third amplifier and outputs a fourth corrected data output signal to the fourth amplifier, the fourth amplifier amplifies the fourth corrected data output signal based on a fourth data clock division signal and outputs the fourth data output division signal to the first DFE section and the memory unit, the calibration unit transmits a data input signal of a predetermined pattern to the comparator when calibration is started, and applies different DFE bias currents to any one of the first DFE section, the second DFE section, the third DFE section, and the fourth DFE section a plurality of times, obtains a width of a data eye window corresponding to each application, compares widths of the respective data eye windows to obtain a data eye window having a maximum width, and sets a DFE bias current corresponding to the data eye window having the maximum width as an optimal DFE bias current.

In the memory according to the first aspect of the present invention, the first data output partial signal, the second data output partial signal, the third data output partial signal, and the fourth data output partial signal are preferably each in a phase of 0 °, 90 °, 180 °, and 270 °.

In the memory according to the first aspect of the present invention, the third aspect of the present invention preferably applies a DFE bias current to the first DFE portion 4 times different from each other.

In the memory according to the third aspect of the present invention, the magnitude of the DFE bias current applied is preferably automatically increased by the operation of the counter.

Preferably, in the memory according to the first aspect of the present invention,

When calibration is started, the data input signal of a preset mode is sent to the comparator repeatedly for a plurality of times, the delay of the data clock signal is increased every time of repetition, and the optimal DFE bias current at each time of repetition is obtained according to the data clock signal after the delay of each time of repetition.

In the memory according to the first aspect of the present invention, the first DFE section, the second DFE section, the third DFE section, and the fourth DFE section are preferably 1-tap DFEs.

Effects of the invention

According to the memory of the present invention, at the time of starting calibration, a data input signal of a predetermined pattern is transmitted to the comparator, different DFE bias currents are applied to any one of the first DFE section, the second DFE section, the third DFE section, and the fourth DFE section a plurality of times, the widths of the data eye windows corresponding to each application are obtained, the widths of the data eye windows are compared to obtain the data eye window having the largest width, and the DFE bias current corresponding to the data eye window having the largest width is set as the optimum DFE bias current, so that the optimum DFE bias current applied to the DFE section can be set by automatic calibration, the adverse effect of the post-label on the subsequent pulse signal can be suppressed to the maximum, and the possibility of erroneous judgment can be reduced.

Drawings

Fig. 1 is a schematic diagram showing a case where a post-symbol is generated in an impulse response of a receiving end of a DRAM due to the existence of an interconnection between a controller and the DRAM.

Fig. 2A is a circuit diagram showing an input receiving unit in a memory according to an embodiment of the present invention, and fig. 2B is a circuit diagram showing one example of specific configurations of the comparator 101 and the DFE section 201 in the input receiving unit in the memory according to the embodiment of the present invention.

Fig. 3 is a schematic diagram showing an example in which the data eye width is increased by applying a bias current to the DFE section in the memory according to the embodiment of the present invention.

Fig. 4 is a circuit diagram and a signal timing chart showing an example of finding the data eye width in the memory according to the embodiment of the present invention, in which the occurrence of the continuous signal 14 times, i.e., 1111 indicates that the data eye window check specifying the offset is completed, shifting the data to the register, resetting the counter for the next offset.

Fig. 5 shows an example of a timing chart of each signal pulse when calibration is performed in the memory according to the embodiment of the present invention.

Fig. 6 is a schematic diagram showing a case where a counter is reset when an abnormal waveform occurs in a pulse waveform in the memory according to the embodiment of the present invention.

Fig. 7 is a signal timing chart and a circuit diagram showing a reset of a counter when an abnormal waveform occurs in a pulse waveform in the memory according to the embodiment of the present invention.

Fig. 8 is a schematic diagram showing generation of bias0_cal/bias1_cal/bias2_cal/bias3_cal by a counter and a decoder at the time of calibration in a memory according to an embodiment of the present invention.

FIG. 9 is a schematic diagram showing the generation of BIS0_WR/BIS1_WR/BIS2_WR/BIS3_WR at calibration time according to the comparison of the data eye windows from BIS0_CNT < N:0 >/BIS1_CNT < N:0 >/BIS2_CNT < N:0> in the memory according to embodiments of the present invention.

Fig. 10 is a schematic diagram showing a basic structure of a memory having a calibration function according to an embodiment of the present invention.

Description of the reference numerals

101. Comparator with a comparator circuit

201. First DFE section

202. Second DFE section

203. Third DFE section

204. Fourth DFE section

301. First amplifier

302. Second amplifier

303. Third amplifier

304. Fourth amplifier

1011. First transistor

1012. Second transistor

2011. Third transistor

2012. Fourth transistor

10. Input receiving unit

11. Calibration unit

12. Memory cell

Detailed Description

The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. The dimensions and relative dimensions of layers and regions may be exaggerated in the figures for clarity.

Spatially relative terms, such as "under," "below," "lower," "over," "upper," and the like, may be used herein for convenience of description to describe one element or feature's relationship to another element or feature as illustrated. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "under" or "beneath" other elements or features would then be oriented "over" the other elements or features.

Unless otherwise defined, terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention pertains. The terms are to be understood to have meanings consistent with the context of the relevant art and are not to be construed as idealized or overly formal unless expressly so defined herein.

Fig. 10 is a schematic diagram showing a basic structure of a memory having a calibration function according to an embodiment of the present invention.

The memory of the present application comprises an input receiving unit 10, a storage unit 12 and a calibration unit 11. The memory of the present application is described below as a DRAM, but the type thereof is not particularly limited as long as it has the calibration function described in the present application.

Fig. 2A is a circuit diagram showing an input receiving unit in a memory according to an embodiment of the present invention, and fig. 2B is a circuit diagram showing one example of specific configurations of the comparator 101 and the DFE section 201 in the input receiving unit in the memory according to the embodiment of the present invention.

The input reception unit includes a comparator 101, a first DFE section 201, a second DFE section 202, a third DFE section 203, a fourth DFE section 204, a first amplifier 301, a second amplifier 302, a third amplifier 303, and a fourth amplifier 304, the comparator 101 compares an input data input signal dq_in with a reference voltage signal VREFDQ and outputs a data output signal to the first DFE section 201, the second DFE section 202, the third DFE section 203, and the fourth DFE section 204, and the input reception unit divides the data clock signal DQs into a first data clock division signal dqs_0, a second data clock division signal dqs_90, a third data clock division signal dqs_180, and a fourth data clock division signal dqs_270.

The first DFE section 201 corrects the data output signal according to the data output signal and the fourth data output sub-signal dq_270 output from the fourth amplifier 304, and outputs the first corrected data output signal to the first amplifier 301, and the first amplifier 301 amplifies the first corrected data output signal according to the first data clock sub-signal dqs_0 and outputs the first data output sub-signal dq_0 to the second DFE section 202 and the memory cell.

The second DFE section 202 corrects the data output signal according to the data output signal and the first data output sub-signal dq_0 outputted from the first amplifier 301, and outputs the second corrected data output signal to the second amplifier 302, and the second amplifier 302 amplifies the second corrected data output signal according to the second data clock sub-signal dqs_90 and outputs the second data output sub-signal dq_90 to the third DFE section 203 and the memory cell.

The third DFE section 203 corrects the data output signal according to the data output signal and the second data output sub-signal dq_90 output from the second amplifier 302, and outputs the third corrected data output signal to the third amplifier 303, and the third amplifier 303 amplifies the third corrected data output signal according to the third data clock sub-signal dqs_180 and outputs the third data output sub-signal dq_180 to the fourth DFE section 204 and the memory cell.

The fourth DFE section 204 corrects the data output signal according to the data output signal and the third data output sub-signal dq_180 outputted from the third amplifier 303, and outputs the fourth corrected data output signal to the fourth amplifier 304, and the fourth amplifier 304 amplifies the fourth corrected data output signal according to the fourth data clock sub-signal dqs_270 and outputs the fourth data output sub-signal dq_270 to the first DFE section 201 and the memory cell.

In the example of fig. 2A, the phases of the first data output sub-signal dq_0, the second data output sub-signal dq_90, the third data output sub-signal dq_180, and the fourth data output sub-signal dq_270 are 0 °, 90 °, 180 °, and 270 °, respectively.

As an example of the comparator, the specific structure of the comparator 101 is shown in fig. 2B, and includes a first transistor 1011, a second transistor 1012, a first resistor 1013, and a second resistor 1014.

As an example of the DFE section, the specific structure of the first DFE section 201 includes, as shown in fig. 2B, a third transistor 2011, a fourth transistor 2012, and a bias current applying terminal, an output signal DQON from the comparator 101 is input to the source of the third transistor 2011, an output signal DQOP from the comparator 101 is input to the source of the fourth transistor 2012, dq_n in a fourth data output partial signal dq_270 from the fourth amplifier 304 is input to the gate of the third transistor 2011, dq_p in a fourth data output partial signal dq_270 from the fourth amplifier 304 is input to the gate of the fourth transistor 2012, and the drains of the third transistor 2011 and the fourth transistor 2012 are connected to the bias current applying terminal. The specific structures of the second DFE section 202, the third DFE section 203, and the fourth DFE section 204 are similar to those of the first DFE section 201.

At the time of starting calibration, the calibration unit transmits a data input signal dq_in IN a predetermined pattern to the comparator 101, applies different DFE BIAS currents (BIAS <3:0 >) to any one of the first DFE section 201, the second DFE section 202, the third DFE section 203, and the fourth DFE section 204 (first DFE section 201 IN fig. 2B) a plurality of times, obtains the widths of the data eye windows corresponding to each application, compares the widths of the data eye windows to obtain the data eye window having the largest width, and sets the DFE BIAS current corresponding to the data eye window having the largest width as the optimal DFE BIAS current.

Table 1 below shows an example of a DFE offset calibration code automatically generated by a counter at the time of calibration and a bias current level corresponding to the DFE offset calibration code.

< Table 1>

In the example of table 1, when the counter value CNT <1:0> is 00, the DFE BIAS calibration code BIAS 0_cal=1, BIAS 1_cal=0, BIAS 2_cal=0, BIAS 3_cal=0, BIAS setting BIAS <3:0> is 0001, and the applied BIAS current is 1 times the BIAS current, i.e. BIAS current×1. When the counter value CNT <1:0> is 01, the DFE BIAS calibration code BIAS 0_cal=0, BIAS 1_cal=1, BIAS 2_cal=0, BIAS 3_cal=0, and BIAS setting BIAS <3:0> is 0011, and the BIAS current applied is 2 times the BIAS current, i.e., BIAS current x 2. When the counter value CNT <1:0> is 10, the DFE BIAS calibration code BIAS 0_cal=0, BIAS 1_cal=0, BIAS 2_cal=1, BIAS 3_cal=0, and BIAS setting BIAS <3:0> is 0111, and the BIAS current applied is 3 times the BIAS current, i.e. BIAS current×3. When the counter value CNT <1:0> is 11, the DFE BIAS calibration code BIAS 0_cal=0, BIAS 1_cal=0, BIAS 2_cal=0, BIAS 3_cal=1, BIAS setting BIAS <3:0> is 1111, and the applied BIAS current is 4 times the BIAS current, i.e. BIAS current x 4.

Table 2 below shows an example of the DFE bias code corresponding to the optimum bias current obtained by calibration, which is applied to the bias current application terminal of the DFE section during the writing operation.

< Table 2>

In the example of table 1, when the optimum BIAS current obtained by calibration is 1 times the BIAS current, i.e., BIAS current x1, the corresponding DFE BIAS codes BIAS 0_wr=1, BIAS 1_wr=0, BIAS 2_wr=0, BIAS 3_wr=0, and BIAS setting BIAS <3:0> is 0001. When the optimum BIAS current obtained by calibration is 2 times of BIAS current, namely BIAS current multiplied by 2, the corresponding DFE BIAS codes BIAS 0_wr=0, BIAS 1_wr=1, BIAS 2_wr=0, BIAS 3_wr=0, and BIAS setting BIAS <3:0> is 0011. When the optimum BIAS current obtained by calibration is 3 times of BIAS current, namely BIAS current multiplied by 3, the corresponding DFE BIAS codes BIAS 0_wr=0, BIAS 1_wr=0, BIAS 2_wr=1, BIAS 3_wr=0, and BIAS setting BIAS <3:0> is 0111. When the optimum BIAS current obtained by calibration is 4 times of BIAS current, namely BIAS current multiplied by 4, the corresponding DFE BIAS codes BIAS 0_wr=0, BIAS 1_wr=0, BIAS 2_wr=0, BIAS 3_wr=1, and BIAS setting BIAS <3:0> is 1111.

Fig. 2B, table 1, and table 2 show examples in which the first DFE section 201 is applied with the DFE bias currents of 4 times, that is, the bias current x 1, the bias current x 2, the bias current x 3, and the bias current x 4, but the present invention is not limited to this. For example, the DFE bias current may be applied to other DFE sections, and the number of times the DFE bias current is applied is not limited to 4.

Fig. 3 is a schematic diagram showing an example in which the data eye width is increased by applying a bias current to the DFE section in the memory according to the embodiment of the present invention.

As shown in fig. 3, the dashed line represents an idealized pulse shape assuming that the noise of the impulse response described above is absent. The second solid line on the right side of the broken line is a noise waveform of an impulse response generated on the memory receiving end side due to an interconnection between the controller and the memory, and by applying a bias current to the DFE section, the second solid line can be moved leftward to become the first solid line on the right side of the broken line, i.e., the width of the data eye can be increased. At this time, if the bias current is too small, it is not possible to get as close to the broken line as possible, and if the bias current is too large, it is necessary to find the optimum magnitude of the bias current so that the noise waveform of the impulse response matches the broken line as much as possible.

Fig. 4 is a circuit diagram and a signal timing chart showing an example of finding the data eye width in the memory according to the embodiment of the present invention. Fig. 5 shows an example of a timing chart of each signal pulse when calibration is performed in the memory according to the embodiment of the present invention.

First, the controller sends successive DQ data "1111" to the memory to initialize calibration. Then, the controller transmits DQ data "0101" to the memory, and applies BIAS currents x 1, x 2, x 3, and x 4, which are different DFE BIAS currents, to the first DFE section 201 by the operation of the counter, and obtains the widths of the data eye windows corresponding to each application as BIAS0_cnt < N:0>, BIAS1_cnt < N:0>, BIAS2_cnt < N:0>, and BIAS3_cnt < N:0>.

Then, in the example of fig. 5, the controller transmits DQ data "0101" again to the memory, and repeats the above-described operation (10T is the length of one DQ signal) after increasing the delay of 1T of the DQs. The number of repetitions of the controller sending DQ data "0101" to memory depends on the resolution of the calibration, for example 10 repetitions in the example of fig. 5. Further, the number of repetitions of the present invention is not limited thereto.

In fig. 4, the occurrence of the continuous signal 14 times, i.e., 1111 indicates that the data eye window check for the specified offset is completed, the data is shifted to the register, and the counter is reset for the next offset.

Fig. 6 is a schematic diagram showing a case where a counter is reset when an abnormal waveform occurs in a pulse waveform in the memory according to the embodiment of the present invention.

The noise waveform of the impulse response generated at the memory receiving end side due to the interconnection between the controller and the memory may sometimes generate a small high level and a small low level in a period of time which should be high level (i.e., higher than the horizontal line in fig. 6, i.e., reference voltage VREFDQ), i.e., may be erroneously determined as "101" for a signal which should be "1", as shown by the solid line in fig. 6, so that the signal of "1" is counted more once. Since the data eye window is defined by consecutive data higher than VREFDQ, a small high level and a small low level in fig. 6 are undesirable data. Thus, when a small low level shown in fig. 6 appears in the noise waveform of the impulse response generated at the memory receiving side, the counter is reset. The reset of the counter can be realized by the signal timing diagram and the circuit schematic shown in fig. 7.

Fig. 7 is a signal timing chart and a circuit diagram showing a reset of a counter when an abnormal waveform occurs in a pulse waveform in the memory according to the embodiment of the present invention.

In the example of fig. 7, when a small low level is detected in the signal of dq_270 at the memory receiving end side, det_l becomes a falling edge, and at this time, the counter reset signal cnt_r becomes a high level, and the counter is reset so that measurement of the width of the data eye window is stopped.

Fig. 8 is a schematic diagram showing generation of bias0_cal/bias1_cal/bias2_cal/bias3_cal by a counter and a decoder at the time of calibration in a memory according to an embodiment of the present invention.

As shown in fig. 8, CNT <1:0> i.e. "00", "01", "10", "11" is generated by the action of the counter at the time of calibration, and then bias0_cal/bias1_cal/bias2_cal/bias3_cal corresponding to CNT <1:0> shown in table 1 is generated by the decoder, thereby obtaining DFE BIAS setting BIAS <3:0> shown in table 1 used at the time of calibration.

FIG. 9 is a schematic diagram showing the generation of BIS0_WR/BIS1_WR/BIS2_WR/BIS3_WR at calibration time according to the comparison of the data eye windows from BIS0_CNT < N:0 >/BIS1_CNT < N:0 >/BIS2_CNT < N:0> in the memory according to embodiments of the present invention.

In fig. 9, bias0_cnt < N:0>, bias1_cnt < N:0>, bias2_cnt < N:0>, and bias3_cnt < N:0> represent the widths of the respective data eye windows corresponding to the respective DFE BIAS currents applied thereto, and by comparing the widths of the respective data eye windows, a data eye window having the largest width is obtained, and the DFE BIAS current corresponding to the data eye window having the largest width is set as the optimum DFE BIAS current, so that DFE BIAS codes bias0_wr, bias1_wr, bias2_wr, and bias3_wr corresponding to the optimum DFE BIAS current applied to the BIAS current application terminal of the DFE section during the writing operation can be obtained.

According to the memory according to the embodiment of the present invention, at the time of starting calibration, a data input signal of a predetermined pattern is transmitted to the comparator, different DFE bias currents are applied to any one of the first DFE section, the second DFE section, the third DFE section, and the fourth DFE section a plurality of times, the width of the data eye window corresponding to each application is obtained, the widths of the data eye windows are compared to obtain the data eye window having the largest width, and the DFE bias current corresponding to the data eye window having the largest width is set as the optimum DFE bias current, so that the optimum DFE bias current applied to the DFE section can be set by automatic calibration, thereby minimizing adverse effects of the aftermarks on the subsequent pulse signals, and reducing the possibility of erroneous judgment.

The present invention has been described in detail, but the above embodiments are merely examples of all embodiments, and the present invention is not limited thereto. The present invention can freely combine the embodiments, change any component of the embodiments, or omit any component of the embodiments within the scope of the present invention.

Industrial applicability

The memory with the calibration function can be applied to various types of memories such as SDR SRAM, DDR SRAM, QDR SRAM and ZBT SRAM, DRAM including SDRAM, DDR DRAM and RDRAM, ROM and the like.

Claims (6)

1. A memory comprises an input receiving unit, a storage unit and a calibration unit,

The input receiving unit includes a comparator, a first DFE section, a second DFE section, a third DFE section, a fourth DFE section, a first amplifier, a second amplifier, a third amplifier, and a fourth amplifier, the comparator compares the inputted data input signal with a reference voltage signal and outputs a data output signal to the first, second, third, and fourth DFE sections, and the input receiving unit divides a data clock signal into first, second, third, and fourth data clock sub-signals,

The first DFE section corrects the data output signal based on the data output signal and a fourth data output sub-signal output from the fourth amplifier and outputs a first corrected data output signal to the first amplifier, the first amplifier amplifies the first corrected data output signal based on a first data clock sub-signal and outputs a first data output sub-signal to the second DFE section and the memory cell,

The second DFE section corrects the data output signal based on the data output signal and the first data output partial signal output from the first amplifier and outputs a second corrected data output signal to the second amplifier, the second amplifier amplifies the second corrected data output signal based on a second data clock partial signal and outputs a second data output partial signal to the third DFE section and the memory cell,

The third DFE section corrects the data output signal based on the data output signal and the second data output partial signal output from the second amplifier and outputs a third corrected data output signal to the third amplifier, the third amplifier amplifies the third corrected data output signal based on a third data clock partial signal and outputs a third data output partial signal to the fourth DFE section and the memory cell,

The fourth DFE section corrects the data output signal based on the data output signal and the third data output partial signal output from the third amplifier and outputs a fourth corrected data output signal to the fourth amplifier, the fourth amplifier amplifies the fourth corrected data output signal based on a fourth data clock partial signal and outputs the fourth data output partial signal to the first DFE section and the memory cell,

The calibration unit transmits a data input signal of a predetermined pattern to the comparator when the calibration is started, applies different DFE bias currents to any one of the first DFE section, the second DFE section, the third DFE section, and the fourth DFE section a plurality of times, obtains the widths of the data eye windows corresponding to each application, compares the widths of the data eye windows to obtain a data eye window having a maximum width, and sets the DFE bias current corresponding to the data eye window having the maximum width as an optimal DFE bias current.

2. The memory of claim 1, wherein,

The phases of the first data output sub-signal, the second data output sub-signal, the third data output sub-signal and the fourth data output sub-signal are respectively 0 degrees, 90 degrees, 180 degrees and 270 degrees.

3. The memory of claim 1, wherein,

For the first DFE section, 4 different DFE bias currents are applied.

4. The memory of claim 3, wherein,

The magnitude of the applied DFE bias current is automatically stepped up by the action of the counter.

5. The memory of claim 1, wherein,

When calibration is started, the data input signal of a preset mode is sent to the comparator repeatedly for a plurality of times, the delay of the data clock signal is increased every time of repetition, and the optimal DFE bias current at each time of repetition is obtained according to the data clock signal after the delay of each time of repetition.

6. The memory of claim 1, wherein,

The first DFE section, the second DFE section, the third DFE section, and the fourth DFE section are all 1-tap DFEs.