CN115188740A - On-chip low-leakage interconnected signal line system and addressable test array circuit - Google Patents

Abstract

The invention discloses an on-chip low-leakage interconnected signal line system and an addressable test array circuit for solving the problem of interconnected signal line leakage. The on-chip low-leakage interconnected signal line system includes interconnected signal lines that can be configured to have equal voltages and a signal protection path, wherein the signal protection path includes: a first shielding layer and a second shielding layer, the first shielding layer and the second shielding layer shield the interconnecting signal lines in the vertical projection direction of the chip, and the interconnecting signal lines are located in the first shielding layer. layer and the second shielding layer; the first shielding wall and the second shielding wall, the first shielding wall and the second shielding wall are respectively connected to the first shielding layer and the second shielding layer, and the interconnecting signal lines are located between the first shielding wall and the second shielding layer. between the second shielding wall.

Description

On-chip low-leakage interconnected signal line system and addressable test array circuit

technical field

The invention belongs to the technical field of semiconductor testing, and particularly relates to an on-chip low-leakage interconnection signal line system and an addressable testing array circuit using the same.

Background technique

During semiconductor development, it is often necessary to test process maturity and semiconductor device performance using semiconductor test structures. Referring to FIG. 1 , in the existing test structure, each port of the device under test is directly connected to a chip pad (Pad) through an on-chip metal wire, and the instrument contacts the pad through a probe to perform measurement.

Usually the size of the pad is about 60μm×60μm, a device to be tested needs 2 to 4 pads to pass the test, and the size of a device to be tested is usually within 3μm^2, so most of the area of the test structure is occupied by the pad, the area Utilization is low. In addition, when testing different devices under test, the probe needs to be moved to the Pad of other test structures for measurement; generally speaking, the time of the probe movement process is much longer than the measurement time, resulting in a low time utilization efficiency in the test process. .

In order to solve the above problems, it is proposed to selectively communicate with a specific device under test, so that the test terminals of multiple devices under test can share the Pad, so as to improve the area of the test structure and the utilization rate of the test process time; however, in such a case In the structure, there may be challenges of leakage of interconnected signal lines.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide an on-chip low leakage interconnection signal line system, which is used to solve the problem of interconnection signal line leakage.

In order to achieve the above object, the present invention provides an on-chip low-leakage interconnected signal line system, which is applied on the chip and includes interconnected signal lines and signal protection paths that can be configured to have equal voltages, wherein the signal protection paths include:

A first shielding layer and a second shielding layer, the first shielding layer and the second shielding layer shield the interconnecting signal lines in the vertical projection direction of the chip, and the interconnecting signal lines are located between the first shielding layer and the second shielding layer. between the second shielding layer;

A first shielding wall and a second shielding wall, the first shielding wall and the second shielding wall are connected to the first shielding layer and the second shielding layer, respectively, and the interconnecting signal lines are located between the first shielding wall and the second shielding wall. between two shielding walls.

In one embodiment, the first shielding layer includes a metal layer in the on-chip interconnect layer.

In one embodiment, the second shielding layer includes a substrate isolation well of the chip or a gate layer of the chip; or,

The second shielding layer includes a metal layer in the on-chip interconnect layer.

In one embodiment, the first shielding wall and the second shielding wall respectively comprise a via filling medium in the on-chip inner dielectric layer; or,

The first shielding wall and the second shielding wall respectively comprise a via-filling medium in the inner-layer dielectric layer on the chip, and a via-filling medium and a metal layer in the interconnection layer; or,

The first shielding wall and the second shielding wall respectively include through-hole filling dielectric and metal layers in the two interconnect layers on the chip.

The present application also provides an addressable test array circuit for testing multiple devices under test, including:

test signal line;

a signal protection path, which can be configured to be equal to the voltage on the test signal line;

a plurality of switches that can be opened and closed by addressable control, the plurality of switches are respectively connected to the test signal line and the corresponding device under test; wherein,

The signal protection path includes:

a first shielding layer and a second shielding layer, the first shielding layer and the second shielding layer shield the interconnecting signal lines in the vertical projection direction of the test array circuit, and the interconnecting signal lines are located on the first shielding between the layer and the second shielding layer;

A first shielding wall and a second shielding wall, the first shielding wall and the second shielding wall are connected to the first shielding layer and the second shielding layer, respectively, and the interconnecting signal lines are located between the first shielding wall and the second shielding wall. between two shielding walls.

In one embodiment, the first shield layer includes a metal layer in an interconnect layer on the test array circuit.

In one embodiment, the second shielding layer includes a substrate isolation well or a gate layer of the test array circuit; or,

The second shield layer includes a metal layer in an interconnect layer on the test array circuit.

In one embodiment, the first shielding wall and the second shielding wall respectively comprise a through-hole filling medium in the inner dielectric layer on the test array circuit; or,

The first shielding wall and the second shielding wall respectively comprise a through hole filling medium in the inner dielectric layer on the test array circuit, and a through hole filling medium and a metal layer in the interconnection layer; or,

The first shielding wall and the second shielding wall respectively comprise a through-hole filling medium and a metal layer in the two interconnection layers on the test array circuit.

In one embodiment, the switch includes a MOS transistor, and the vertical projection of the gate of the MOS transistor on the active region thereof is annular.

In an embodiment, the MOS transistors include at least two, and the at least two MOS transistors are arranged in a common gate; and/or,

The test signal line is connected to the low-leakage active region of the MOS transistor, wherein the low-leakage active region is a part of the active region in the vertical projection of the gate of the MOS transistor on the active region.

In one embodiment, the test signal line includes a drain voltage signal line for measuring the current of the device under test, and/or,

The test signal line includes a drain sensing signal line for measuring the voltage of the device under test.

Compared with the prior art, in the on-chip low-leakage interconnection signal line system of the present application, the signal protection path and the interconnection signal line can be configured with the same voltage, and in terms of process structure, the signal protection path passes through the first shielding layer, the second shielding layer and the second shielding layer. The coordinated arrangement of the shielding layer, the first shielding wall and the second shielding wall can “encircle” the interconnected signal lines, so that there is almost no voltage difference between the interconnected signal lines and the signal protection path in the extending direction, thereby suppressing the interconnection signal Leakage that may be generated by the line;

In another aspect, in the on-chip low-leakage interconnection signal line system of the present application, the signal protection path can be constructed by using the existing semiconductor structure in the application scenario, and the implementation cost is low.

Description of drawings

1 is a schematic diagram of a semiconductor test structure in the prior art;

2 is a schematic diagram of an application scenario of an on-chip low-leakage interconnection signal line system of the present application;

3 is a schematic structural diagram of an on-chip low-leakage interconnection signal line system according to an embodiment of the present application;

4 is a schematic structural diagram of an on-chip low-leakage interconnection signal line system according to another embodiment of the present application;

5 to 9 are schematic diagrams of application scenarios of the on-chip low-leakage interconnection signal line system in various embodiments of the present application;

10 is a schematic structural diagram of an addressable test array according to an embodiment of the present application;

11 is a schematic structural diagram of the cooperation of signal protection paths and test signal lines in an addressable test array circuit according to an embodiment of the present application;

12 is a schematic diagram of a gate-all-around structure of a MOS transistor in an addressable test array circuit according to an embodiment of the present application.

Detailed ways

The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific embodiments.

Unless expressly stated otherwise, throughout the specification and claims, the term "comprising" or its conjugations such as "comprising" or "comprising" and the like will be understood to include the stated elements or components, and Other elements or other components are not excluded.

Referring to FIG. 3 , a specific embodiment of the on-chip low-leakage interconnection signal line system 100 of the present application is introduced. In this embodiment, the low-leakage interconnected signal line system 100 includes interconnected signal lines 11 and signal protection paths 12 .

The low-leakage interconnection signal line system 100 provided by the present application can be applied to various chips, especially, for example, the types of chips that are sensitive to leakage. The signal protection path 12 and the interconnection signal line 11 can be configured to have the same voltage, and, in terms of process structure, the signal protection path 12 is arranged “around” the interconnection signal line 11, so that the interconnection signal line 11 and the signal protection path in its extending direction There is almost no voltage difference between the 12, thereby suppressing the possible leakage of the interconnected signal lines 11.

In one embodiment, the signal protection via 12 may replicate the voltage on the interconnected signal line 11 through a voltage follower buffer, or the interconnected signal line 11 and the signal protection via 12 may be respectively connected to equal-voltage pads.

The signal protection via 12 includes a first shielding layer 121 , a second shielding layer 122 , a first shielding wall 123 , and a second shielding wall 124 . The first shielding layer 121 and the second shielding layer 122 shield the interconnection signal line 11 in the vertical projection direction of the chip, and the interconnection signal line 11 is located between the first shielding layer 121 and the second shielding layer 122; at the same time, the first shielding wall 123 and the second shielding wall 124 are respectively connected to the first shielding layer 121 and the second shielding layer 122 , and the interconnecting signal line 11 is located between the first shielding wall 123 and the second shielding wall 124 .

In the above process structure, the first shielding layer 121 , the second shielding layer 122 , the first shielding wall 123 , and the second shielding wall 124 form a shielding structure surrounding the interconnecting signal line 11 on the peripheral side where the interconnecting signal line 11 extends . In addition, it should be noted that the first shielding layer 121, the second shielding layer 122, the first shielding wall 123, and the second shielding wall 124 are not limited to be completely continuous in structure. In some embodiments, the signal protection path 12 composed of the first shielding layer 121 , the second shielding layer 122 , the first shielding wall 123 , and the second shielding wall 124 may only be required to be able to protect the interconnecting signals to a certain extent or part. It is sufficient that the line 11 has a leakage suppressing effect. This will be explained in detail in the following examples.

Referring to FIG. 2 , a typical chip to which the on-chip low-leakage interconnection signal line system 100 of the present application is applied may include a plurality of semiconductor devices, such as field effect transistors (FETs). Structurally, the part related to the signal protection path 12 in the various embodiments of the present application may mainly include the substrate isolation well and gate layer of the chip, the inner layer dielectric layer (ILD), the interconnect layer, and the through hole filling on the chip. medium, etc.

It can be understood that the substrate isolation wells and gate layers here may be isolation wells and gates corresponding to a plurality of semiconductor devices in the chip. The chip interconnection layer refers to a functional layer formed on the semiconductor device region in the back end of line (BEOL) process of chip fabrication and used to connect the semiconductor device and external circuits. Generally, multiple interconnect layers can be fabricated on the chip, and each interconnect layer further includes a dielectric layer and a metal layer. The metal layer is used to connect the gates, sources or drains of different devices, and the dielectric layer is used to Isolate metal layers between different interconnect layers. The interconnection layer includes vias penetrating the dielectric layers, and the vias are filled with a conductive via-filling medium, so as to electrically connect metal layers in different interconnection layers. The inner dielectric layer refers to the dielectric layer between the first interconnect layer closest to the substrate and the substrate. Similarly, the interlayer dielectric layer also includes through holes penetrating the same, and is also filled with the through hole filling medium, so as to electrically connect the semiconductor device on the chip and the metal layer in the interconnection layer.

Exemplarily, the material of the above substrate may be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi) or carbide (SiC), or may be silicon on insulator (SOI), germanium on insulator ( GOI), or other materials, such as III-V compounds such as gallium arsenide. The gate layer may contain doped polysilicon or high-k metal. The dielectric layer in the interconnect layer can be silicon oxide, silicon nitride, silicon carbide, silicon oxynitride and other dielectric materials, as well as black diamond, carbon-containing low-k dielectric materials, hydrogen silsesquioxane (HSQ) , methylsilsesquioxane (MSQ) and other Low-K materials; the metal layer material in the interconnection layer may be copper (Cu). Via fill dielectrics may be tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), their alloys and/or or their multiple layers. The inner dielectric layer may be phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), fluorine doped silicate glass (FSG), Ethyl orthosilicate (TEOS), etc.

The specific process structure of the low-leakage interconnection signal line system in each embodiment of the present application is described in detail below.

Example 1

Referring to FIG. 5 , the first shielding layer 121A is the metal layer in the interconnect layer 30A on the chip, the second shielding layer 122A is the substrate isolation well of the chip, and the first shielding wall 123A and the second shielding wall 124A are the inner layers on the chip The vias in the dielectric layer 20A are filled with a dielectric.

The inner-layer dielectric layer 20A may include a plurality of continuously arranged through holes, that is, a certain distance may exist between adjacent through-hole filling dielectrics. In addition, the first shielding layer 121A and the second shielding layer 122A may also be provided with corresponding interconnection structures according to the requirements of chip design. In this way, the signal protection path is constructed by using the existing semiconductor structure in the chip manufacturing process, and the implementation cost is low.

It can be seen that the signal protection via can be used to prevent leakage of the interconnecting signal lines 11A arranged in the on-chip inner dielectric layer 20A, and the interconnecting signal lines 11A can be arranged using gate layer materials.

Example 2

6 , the first shielding layer 121B is a metal layer in the on-chip interconnection layer 32B, the second shielding layer 122B is the gate layer of the chip, and the first shielding wall 123B and the second shielding wall 124B include on-chip inner interlayers. Via-fill dielectric 21B in electrical layer 20B, and via-fill dielectric 311B and metal layer 312B in interconnect layer 31B.

It can be seen that the signal protection via substantially includes the semiconductor structures in the inner dielectric layer 20B and the at least two interconnect layers 31B and 32B. The difference from Embodiment 1 is that in Embodiment 2, the gate layer of the chip is used as the second shielding layer 122B, and the signal protection via can be used to prevent the interconnection signal lines 11B arranged in the interconnection layer 31B on the chip from being damaged. leakage, and the interconnection signal line 11B may be routed using the material of the metal layer 312B in the interconnection layer 31B.

Example 3

7, the first shielding layer 121C is a metal layer in the interconnect layer 32C on the chip, the second shielding layer 122C is the substrate isolation well of the chip, and the first shielding wall 123C and the second shielding wall 124C include on-chip inner layers Via-fill dielectric 21C in dielectric layer 20C, and via-fill dielectric 311C and metal layer 312C in interconnect layer 31C.

It can be seen that the signal protection via also includes the semiconductor structures in the inner dielectric layer 20C and the at least two interconnect layers 31C and 32C. The difference from Embodiment 2 is that in Embodiment 3, the substrate isolation well of the chip is used as the second shield layer 122C, and the interconnection signal line 11C can use the material of the metal layer 312C or the material of the gate layer in the interconnection layer 31C layout.

Example 4

8, the first shielding layer 121D and the second shielding layer 122D are metal layers in the two non-adjacent interconnect layers 33D and 31D on the chip, and the first shielding wall 123D and the second shielding wall 124D include two interconnects The vias in layers 31D, 32D fill the dielectric and metal layers. Specifically, it can be considered that the first shielding wall 123D and the second shielding wall 124D include the via-filling medium 311D in the interconnection layer 31D, and the via-filling medium 321D and the metal layer 322D in the interconnection layer 32D.

It can be seen that, at this time, the signal protection path essentially includes the semiconductor structures in the three continuous interconnect layers 31D, 32D, and 33D. In such an embodiment, the interconnection signal line 11D may be routed using the material of the metal layer 322D in the interconnection layer 32D.

It can be understood that, in an alternative manner similar to this embodiment, signal protection paths may also be constructed by semiconductor structures in four or more continuous interconnect layers, so that interconnect signal lines may use non-top/non-bottom layers. Metal layer material placement in interconnect layers.

Example 5

9 , the first shielding layer 121E is a metal layer in the interconnect layer 33E on the chip, the second shielding layer 122E is the substrate isolation well of the chip, and the first shielding wall 123E and the second shielding wall 124E are the inner layers on the chip The via-fill dielectric 21E in the dielectric layer 20E, and the via-fill dielectrics 311E, 321E and the metal layers 312E, 322E in the two interconnect layers 31E, 32E.

It can be seen that, at this time, the signal protection path substantially includes the inner dielectric layer 20E and the semiconductor structures in the three interconnection layers 31E, 32E, and 33E. In such an embodiment, the interconnection signal line 11E may be arranged using the material of the metal layer 312E in the interconnection layer 31E, the material of the metal layer 322E in the interconnection layer 32E, or the material of the gate layer.

In the above Embodiments 1 to 5, except that the second shielding layer in Embodiment 4 is a metal layer, the second shielding layers in other illustrated embodiments are all substrate isolation wells or gate layers, that is, Signal protection vias can be constructed with only one metal layer in the interconnect layer. In this way, in some application scenarios with fewer interconnect layers, there is no need to additionally set more metal layers for constructing signal protection paths, and the process cost is lower.

Referring to FIG. 3 and FIG. 4 again, in the embodiment in which the substrate isolation well is used as the second shielding layer 122, the vertical projection of the interconnection signal line 11 on the chip substrate may be an isolation trench located on or not located on the isolation well (STI). Wherein, when the vertical projection of the interconnecting signal line 11 on the chip substrate is located in the isolation trench on the isolation well (as shown in FIG. 3 ), it can have less leakage and facilitate the drawing of the process layout. It can be understood that, in the process structures shown in the foregoing Embodiments 1 to 5, the positional relationship between the isolation trenches in the isolation wells and the interconnecting signal lines may be based on the needs of different layout designs, and optionally refer to FIG. 3 or FIG. The manner shown in 4 will not be repeated here.

Referring to FIG. 10, an embodiment of the addressable test array circuit 200 of the present application is introduced. In this embodiment, the addressable test array circuit 200 includes test signal lines 21 , signal protection paths 22 and switches 23 .

The addressable test array circuit 200 can be used for testing a plurality of devices under test. Generally, each switch 23 corresponds to one device under test. It should be noted that, depending on the device under test, the number of test ports corresponding to each device under test may also be different. The term "each switch 23 corresponds to one device under test" here means that the switch 23 only corresponds to control Connect the device under test or a port of the device under test.

Taking the device under test as an example with a gate (G), a source (S), a drain (D), and a well (B), the gates, sources, and wells of multiple devices under test can be connected in a common On the pad (Pad), the drain that cannot be reused is connected to another Pad through a plurality of switches 23 . The test array can control whether the switch 23 is connected to the drain of the device under test through the shift register, and at the same time, the test array only selects one device under test for testing.

In a specific circuit, the output end of the row-column switching circuit is connected to the input end of the device under test. In the addressing circuit, the output signals of the row address decoder and the column address decoder are determined. The row address decoder and the column address decoder share the clock signal CK, and the combined signal of the two is transmitted to the switch circuit to determine the corresponding position. On-off of the DUT switch 23 .

For circuits that determine specific row and column switches, multi-level transmission gates can be used. That is: the output end of the transmission gate of the higher level is connected to the input end of the transmission gate of the lower level connected to it, and the output end of the transmission gate of the lowest level is connected to the input end of the last device under test, so as to determine the specific The switch 23 of the position device under test is turned on and off.

The test signal line 21 can be used to measure the current and/or voltage of each port of the device under test, and the above-mentioned multiple switches 23 are respectively connected to the test signal line 21 and the corresponding device under test to control the test signal line 21 and the device under test. on and off between. Taking the measurement of the current and voltage of the drain of the device under test as an example, a corresponding voltage can be applied to the drain of the device under test and the switch 23 connected to the drain thereof is closed. At this time, at an appropriate position on the test signal line 21 Corresponding current and voltage can be measured.

In the embodiment of the addressable test array circuit 200 of the present application, the test signal line 21 may be regarded as a type of interconnection signal line. That is, in this embodiment, the solution of the on-chip low-leakage interconnection signal line system in the above-mentioned embodiment is substantially applied, and the possible leakage of the test signal line 21 is prevented through the signal protection path 22, thereby ensuring the addressable test array circuit 200. The test accuracy of the device under test, especially when the device under test is turned off, will improve the test accuracy more obviously.

Referring to FIG. 11 , the signal protection via 22 includes a first shielding layer 221 , a second shielding layer 222 , a first shielding wall 223 and a second shielding wall 224 . The first shielding layer 221 and the second shielding layer 222 shield the test signal line 21 in the vertical projection direction of the test array circuit 200, and the interconnecting signal line is located between the first shielding layer 221 and the second shielding layer 222; at the same time, The first shielding wall 223 and the second shielding wall 224 are respectively connected to the first shielding layer 221 and the second shielding layer 222 , and the test signal line 21 is located between the first shielding wall 223 and the second shielding wall 224 .

Similarly, the constituent parts of the signal protection path 22 here are not necessarily limited to be completely continuous. As shown in FIG. 11 , the test signal line 21 can be connected to a set area on the substrate isolation well through a conductive medium, which may cause “missing” on the second shielding layer 222; or, the first shielding wall 223 and The formation of the second shield 224 includes a through-hole filling medium, and the through-hole filling medium located in the plurality of through holes also has a corresponding "gap" in structure. However, these indicated "missing" and "gap" will not cause the failure of the signal protection path 22 to the leakage prevention function of the test signal line 21 .

The addressable test array circuit 200 of the present application may also include a plurality of semiconductor devices fabricated on a substrate, such as field effect transistors. Therefore, in terms of structure, the signal protection path 22 here can also be constructed by using a substrate isolation well, a gate layer, an inner dielectric layer on the chip, an interconnection layer, a through hole filling medium, and the like.

As a whole, the first shielding layer 221 may include a metal layer in an interconnection layer on the test array circuit. The second shielding layer 222 may include a substrate isolation well of the test array circuit, a gate layer, or a metal layer in an interconnect layer. The first shielding wall 223 and the second shielding wall 224 may respectively include a through-hole filling medium in the inner-layer dielectric layer on the test array circuit, or may include a through-hole filling medium in the inner-layer dielectric layer on the test array circuit, and the through-hole filling medium and metal layer in the interconnection layer, or the through-hole filling medium and metal layer in the two interconnection layers on the test array circuit.

In a specific embodiment, the process structure of the signal protection path 22 may refer to Embodiment 1 to Embodiment 5 in the above-mentioned low-leakage interconnection signal line system, which will not be repeated here.

In this embodiment, the signal protection path 22 may also replicate the voltage on the test signal line 21 through a voltage follower buffer, or the test signal line 21 and the signal protection path 22 may be respectively connected to equal-voltage pads.

In this embodiment, the switch 23 may be constructed by using a MOS transistor. In a conventional MOS tube, ideally, when the gate is not energized, it is difficult for the source signal to pass through the non-conductive inversion layer to the drain region, and the drain D and source S are not conductive; and if When a voltage is applied between the gate and the substrate, the charges in the inversion layer will accumulate in a large amount under the insulating oxide layer under the gate, forming a channel, making the source and drain conduct, and the current can be smoothly transferred from the source to the drain. However, due to the commonly used single-gate or double-gate structure, leakage current will accumulate at the edge of the gate even when no turn-on voltage is applied to the gate, which ultimately affects the measurement results of the device under test.

Referring to FIG. 12 , in this embodiment, the vertical projection of the gate of the MOS transistor in the switch 23 on the active region thereof is a ring shape (ring gate). That is, the gate edge of the MOS transistor is "eliminated", thereby avoiding the possibility of leakage current accumulation.

In this embodiment, each switch 23 includes at least two MOS transistors, and the two MOS transistors are arranged in a common gate. Referring to FIG. 10 , it is taken as an example that the switch 23 includes a first MOS transistor 231 and a second MOS transistor 232 , wherein the second MOS transistor 232 is connected to the high-resistance voltage measurement loop.

The settings of the first MOS transistor 231 and the second MOS transistor 232 are respectively used for switching control of the measurement loops of the current and voltage of the device under test. Correspondingly, the above-mentioned test signal line 21 may include two: a drain voltage signal line 211 and a drain sensing signal line 212 , the drain of the first MOS transistor 231 is connected to the drain voltage signal line 211 , and the second MOS transistor 232 The drain is connected to the drain sensing signal line 212, the sources of the first MOS transistor 231 and the second MOS transistor 232 are connected to the device under test, and the first MOS transistor 231 and the second MOS transistor 232 are arranged in common gate. In this way, the first MOS transistor 231 and the second MOS transistor 232 can be controlled to be turned on or off at the same time by the same gate voltage control signal, so that the device under test is respectively performed on the drain voltage signal line 211 and the drain sensing signal line 212 Corresponding port current and voltage measurements.

The "high-resistance voltage measurement loop" mentioned here means that the resistance of the measurement loop can be set to be extremely high, so that during measurement, the current on it can approach zero. Since the switch 23 may flow a mA level current in the ON state, and due to the inherent on-resistance of the switch 23, the mA level current will cause significant voltage transfer loss, and eventually lead to errors in the leakage current measurement results. By configuring the voltage measurement of the drain sensing signal line 212 to be performed in the high-voltage resistance measurement loop, the interference of the resistance of the addressable test array circuit 200 itself can be excluded, and the voltage on the drain voltage signal line 211 does not affect the high-resistance voltage. The voltage on the loop is measured, so the voltage of the device under test can be accurately measured at the voltage measurement end of the drain sensing signal line 212 .

The realization of the high-resistance voltage measurement loop can take various forms, for example, a resistor with a very high resistance value can be connected in series with the loop, or, a high-resistance voltmeter can be configured directly at the voltage measurement end of the drain sensing signal line 212 to measure the voltage. Measurement. It can be seen that the "high-resistance voltage measurement loop" can have high-resistance characteristics itself, or cooperate with an external high-resistance measuring instrument to achieve high-resistance measurement.

Continuing to refer to FIG. 10 , the switch 23 may further include a third MOS transistor 233 . The drain of the third MOS transistor 233 is connected to the signal protection path 22 . The well voltage is configured to be equal to the voltage on the signal protection path 22, and the source of the third MOS transistor 233 is also connected to the device under test. By loading a voltage control signal on the gate of the third MOS transistor 233 to control its turn-on and turn-off, the switch 23 can be made to have the characteristic of "low leakage".

Specifically, for the switch 23 , when a first voltage control signal is applied to the gate of the first MOS transistor 231 to turn on the first MOS transistor 231 , and a third voltage is applied to the gate of the third MOS transistor 233 . When the control signal is applied to turn off the third MOS transistor 233, the switch 23 is turned on; When the gate of the transistor 233 is loaded with the third voltage control signal to turn off the third MOS transistor 233, the switch 23 is turned on.

In such a switch 23, leakage may include: ① when the switch 23 is open, the inherent drain leakage of the first MOS transistor 231; ② when the switch 23 is closed, the leakage current from the drain to the well of the first MOS transistor 231.

Specifically, when the switch 23 is turned on, the inherent drain leakage of the first MOS transistor 231 includes: drain-to-well leakage, drain-to-source leakage, and well-to-source leakage. At this time, since the third MOS transistor 233 is in an on state, and the well voltage of the first MOS transistor 231 is equal to the voltage on the drain voltage signal line 211, the drain voltage, well voltage, and source voltage of the first MOS transistor 231 The electrode voltages are pulled to be equal, thereby effectively eliminating the inherent source leakage of the first MOS transistor 231 at this time. Similarly, for the leakage current from the drain of the first MOS transistor 231 to the well when the switch 23 is closed, at this time, since the well voltage of the first MOS transistor 231 is pulled to be equal to the drain voltage, its drain to the well The leakage current can also be effectively eliminated.

Similarly, the third MOS transistor 233 may also have a ring-shaped gate, which will not be repeated here.

In this embodiment, the test signal line 21 may be a low-leakage active region connected to the MOS transistor in the switch 23 , wherein the low-leakage active region is a portion of the MOS transistor gate in the vertical projection of the active region that has source area. When the test signal line 21 is connected to the switch 23 , by connecting to the low-leakage active region of the MOS transistor in the switch 23 , the possible leakage of the test signal line 21 at the switch 23 can be further eliminated.

Specifically, since the first MOS transistor 231 and the second MOS transistor 232 are respectively used for switching control of the measurement loop of the current and voltage of the device under test, the low leakage current that can connect the drain voltage signal line 211 to the first MOS transistor 231 has The source region and the drain sensing signal line 212 are connected to the low-leakage active region of the second MOS transistor.

It should be noted that, due to the fact that it involves the field of precise measurement, in the various embodiments/embodiments of the present application, the "equal" defined in a functionally limited manner does not take into account the unavoidable factors such as the characteristics of each device in the circuit and the transmission loss of the circuit. influences. Taking "the signal protection path is configured to be equal to the voltage on the test signal line" as an example, the voltage transmission loss on the above test signal line is not considered at this time. The actual purpose of this setting is to make the voltage on the signal protection path infinite. close to the actual voltage at the measurement terminal of the current device under test; therefore, in the embodiment where a high-impedance voltage measurement loop is provided, the signal protection path can be better set to replicate the voltage on the voltage-sensing signal line with almost no voltage transfer loss .

The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. These descriptions are not intended to limit the invention to the precise form disclosed, and obviously many changes and modifications are possible in light of the above teachings. The exemplary embodiments were chosen and described for the purpose of explaining certain principles of the invention and their practical applications, to thereby enable others skilled in the art to make and utilize various exemplary embodiments and various different aspects of the invention. Choose and change. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims (11)

1. An on-chip low-leakage interconnected signal line system, applied on a chip, is characterized in that, comprising interconnected signal lines and signal protection paths that can be configured as equal voltages, wherein the signal protection paths include: A first shielding layer and a second shielding layer, the first shielding layer and the second shielding layer shield the interconnecting signal lines in the vertical projection direction of the chip, and the interconnecting signal lines are located between the first shielding layer and the second shielding layer. between the second shielding layer; A first shielding wall and a second shielding wall, the first shielding wall and the second shielding wall are connected to the first shielding layer and the second shielding layer, respectively, and the interconnecting signal lines are located between the first shielding wall and the second shielding wall. between two shielding walls. 2 . The on-chip low-leakage interconnection signal line system according to claim 1 , wherein the first shielding layer comprises a metal layer in the on-chip interconnection layer. 3 . 3. The on-chip low-leakage interconnection signal line system according to claim 1, wherein the second shielding layer comprises a substrate isolation well of the chip or a gate layer of the chip; or, The second shielding layer includes a metal layer in the on-chip interconnect layer. 4 . The on-chip low-leakage interconnection signal line system according to claim 1 , wherein the first shielding wall and the second shielding wall respectively comprise a through-hole filling medium in an inner dielectric layer on the chip; 5 . or, The first shielding wall and the second shielding wall respectively comprise a via-filling medium in the inner-layer dielectric layer on the chip, and a via-filling medium and a metal layer in the interconnection layer; or, The first shielding wall and the second shielding wall respectively include through-hole filling dielectric and metal layers in the two interconnect layers on the chip. 5. An addressable test array circuit for testing a plurality of devices under test, characterized in that, comprising: test signal line; a signal protection path, which can be configured to be equal to the voltage on the test signal line; a plurality of switches that can be opened and closed by addressable control, the plurality of switches are respectively connected to the test signal line and the corresponding device under test; wherein, The signal protection path includes: a first shielding layer and a second shielding layer, the first shielding layer and the second shielding layer shield the interconnecting signal lines in the vertical projection direction of the test array circuit, and the interconnecting signal lines are located on the first shielding between the layer and the second shielding layer; A first shielding wall and a second shielding wall, the first shielding wall and the second shielding wall are connected to the first shielding layer and the second shielding layer, respectively, and the interconnecting signal lines are located between the first shielding wall and the second shielding wall. between two shielding walls. 6. The addressable test array circuit of claim 5, wherein the first shield layer comprises a metal layer in an interconnect layer on the test array circuit. 7. The addressable test array circuit according to claim 5, wherein the second shielding layer comprises a substrate isolation well or a gate layer of the test array circuit; or, The second shield layer includes a metal layer in an interconnect layer on the test array circuit. 8 . The addressable test array circuit according to claim 5 , wherein the first shielding wall and the second shielding wall respectively comprise a via filling medium in an inner dielectric layer on the test array circuit. 9 . ;or, The first shielding wall and the second shielding wall respectively comprise a through hole filling medium in the inner dielectric layer on the test array circuit, and a through hole filling medium and a metal layer in the interconnection layer; or, The first shielding wall and the second shielding wall respectively comprise a through-hole filling medium and a metal layer in the two interconnection layers on the test array circuit. 9 . The addressable test array circuit according to claim 5 , wherein the switch comprises a MOS transistor, and the vertical projection of the gate of the MOS transistor on the active region of the MOS transistor is annular. 10 . . 10. The addressable test array circuit according to claim 9, wherein the MOS transistors comprise at least two, and the at least two MOS transistors are arranged in a common gate; and/or, The test signal line is connected to the low-leakage active region of the MOS transistor, wherein the low-leakage active region is a part of the active region in the vertical projection of the gate of the MOS transistor on the active region. 11. The addressable test array circuit according to any one of claims 5 to 8, wherein the test signal line comprises a drain voltage signal line for measuring the current of the device under test, and/or, The test signal line includes a drain sensing signal line for measuring the voltage of the device under test.

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