CN115188766B - AND gate structure and manufacturing method of AND gate structure - Google Patents

Abstract

The embodiment of the present invention provides an AND gate structure and a manufacturing method of the AND gate structure, wherein the AND gate structure includes: a substrate, a source and a drain that are separated from each other and are located in the substrate, the drain is used as an output, and the source is used to connect to a power source; a first gate and a second gate that are located in the substrate and spaced apart, the first gate and the second gate are both located between the source and the drain, and the first gate is located between the second gate and the source, the first gate is used as a first input, and the second gate is used as a second input; a gate dielectric layer, the gate dielectric layer is located in the substrate and is in contact with the first gate and the second gate, and the gate dielectric layer is also located between the first gate and the second gate; wherein, based on the voltage of the first input and the voltage of the second input, the substrate below the gate dielectric layer is suitable for forming a conductive channel, and the conductive channel connects the source and the drain. The embodiment of the present invention can reduce the size of the AND gate structure.

Description

AND gate structure and manufacturing method of AND gate structure

Technical Field

The embodiments of the present invention relate to the semiconductor field, and in particular to an AND gate structure and a method for manufacturing the AND gate structure.

Background technique

AND gate is a logic gate that implements logical AND in digital logic. The output is high only when all inputs are high; if at least one of the inputs is low, the output is low; its expression is Y=AB.

Since the AND gate is a basic logic gate, the AND gate structure is usually used to produce integrated circuits in the semiconductor field. Currently, the AND gate structure is usually manufactured using CMOS (Complementary Symmetric Metal Oxide Semiconductor) transistors.

However, the size of the current AND gate structure needs to be further reduced.

Summary of the invention

The embodiment of the present invention provides an AND gate structure and a manufacturing method of the AND gate structure, so as to reduce the size of the AND gate structure.

To solve the above problems, an embodiment of the present invention provides an AND gate structure, including: a substrate, a source and a drain that are separated from each other and located in the substrate, the drain serves as an output, and the source is used to connect to a power supply; a first gate and a second gate that are located in the substrate and are spaced apart, the first gate and the second gate are both located between the source and the drain, and the first gate is located between the second gate and the source, the first gate serves as a first input, and the second gate serves as a second input; a gate dielectric layer, the gate dielectric layer is located in the substrate and in contact with the first gate and the second gate, and the gate dielectric layer is also located between the first gate and the second gate; wherein, based on the voltage of the first input and the voltage of the second input, the substrate below the gate dielectric layer is suitable for forming a conductive channel, and the conductive channel connects the source and the drain.

In addition, it also includes: a resistor structure, one end of which is connected to the drain, and the other end of which is connected to the ground; the resistance of the resistor structure is greater than the sum of the resistances of the source, the conductive channel and the drain.

In addition, the resistor structure is located inside or on the substrate.

In addition, the resistance of the resistance structure is between 2 and 100 times the sum of the resistances of the source, the conductive channel and the drain.

In addition, the voltage of the first input is a high level, the voltage of the second input is a high level, and the voltage of the output is a high level; or, the voltage of the first input is a low level, the voltage of the second input is a high level, and the voltage of the output is a low level; or, the voltage of the first input is a high level, the voltage of the second input is a low level, and the voltage of the output is a low level; or, the voltage of the first input is a low level, the voltage of the second input is a low level, and the voltage of the output is a low level.

In addition, the voltage of the first input is at a high level, the voltage of the second input is at a high level, and the voltage of the first input and the voltage of the second input are greater than or equal to the voltage of the power supply.

In addition, the gate dielectric layer is also located between the first gate and the source, the gate dielectric layer is also located between the second gate and the drain, and the gate dielectric layer is also located on the lower surface of the first gate and the lower surface of the second gate.

In addition, the thickness of the gate dielectric layer between the first gate and the source is equal to the thickness of the gate dielectric layer between the second gate and the drain.

In addition, in a direction perpendicular to the upper surface of the substrate, the thickness of the first gate is equal to the thickness of the second gate; and in an arrangement direction of the first gate and the second gate, the width of the first gate is equal to the width of the second gate.

In addition, the depth of the source electrode in the substrate is equal to the depth of the drain electrode in the substrate.

In addition, in a direction perpendicular to the upper surface of the substrate, the ratio of the thickness of the first gate to the depth of the source in the substrate is 2:1 to 10:1; the ratio of the thickness of the second gate to the depth of the drain in the substrate is 2:1 to 10:1.

In addition, the gate dielectric layer between the first gate and the second gate has a thickness of 1 nm to 3 nm.

An embodiment of the present invention also provides a method for manufacturing an AND gate structure, comprising: providing a substrate, forming a source and a drain separated from each other in the substrate; forming a groove in the substrate, wherein the groove is also located between the source and the drain; forming a gate dielectric layer, a first gate and a second gate filling the groove; the first gate and the second gate are spaced apart, and the first gate is located between the second gate and the source; the gate dielectric layer is located on the sidewall and bottom of the groove, and is also located between the first gate and the second gate.

In addition, the method further includes: forming a resistor structure connected to the drain, wherein the resistance of the resistor structure is greater than the sum of the resistances of the source, the conductive channel and the drain.

In addition, the steps of forming a gate dielectric layer, a first gate, and a second gate filling the groove include: forming an initial gate dielectric layer filling the groove; forming a first groove and a second groove spaced apart in the initial gate dielectric layer, the first groove being located between the source and the second groove; the remaining initial gate dielectric layer serving as the gate dielectric layer; forming the first gate filling the first groove, and forming the second gate filling the second groove.

Compared with the prior art, the technical solution provided by the embodiment of the present invention has the following advantages:

In the embodiment of the present invention, the AND gate structure is composed of a transistor having a first gate and a second gate. Compared with six transistors, the size of a double-gate transistor is smaller. In addition, since the first gate and the second gate are both located in the substrate, the space utilization rate of the substrate can be further improved.

In addition, the AND gate structure also includes: a resistor structure, one end of the resistor structure is connected to the drain, and the other end of the resistor structure is connected to the ground; the resistance of the resistor structure is greater than the resistance of the drain. In this way, the drain can be prevented from being in a floating state, thereby preventing the drain from outputting an uncertain signal when affected by the hysteresis effect. The grounding of the resistor structure can also pull the output to a low level when at least one input has a low level, thereby improving the accuracy of the output signal.

BRIEF DESCRIPTION OF THE DRAWINGS

One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

FIG1 is an equivalent circuit diagram of an AND gate structure;

FIG2 is a schematic diagram of an AND gate structure provided by an embodiment of the present invention;

FIG3 is an equivalent circuit diagram of FIG2 ;

4 to 8 are schematic structural diagrams corresponding to the steps in a method for manufacturing a door structure provided by another embodiment of the present invention;

9 to 12 are schematic structural diagrams corresponding to the steps in a method for manufacturing a door structure provided in yet another embodiment of the present invention.

Detailed ways

As known from the background art, the size of the AND gate structure needs to be further reduced.

FIG1 is an equivalent circuit diagram of an AND gate structure. Referring to FIG1 , MOS transistors are currently commonly used to manufacture the AND gate structure. However, the AND gate structure requires a total of six MOS transistors, and the six MOS transistors occupy a large area, so the size of the AND gate structure is large.

To solve the above problems, an embodiment of the present invention provides an AND gate structure, including: a source and a drain located in a substrate, the drain serving as an output, and the source serving as a power source; a first gate and a second gate located in the substrate and spaced apart, the first gate and the second gate both being located between the source and the drain, the first gate serving as a first input, and the second gate serving as a second input; a gate dielectric layer in contact with the first gate and the second gate; wherein, based on the voltage of the first input and the voltage of the second input, the substrate under the gate dielectric layer is suitable for forming a conductive channel, and the conductive channel connects the source and the drain. That is, the AND gate structure is composed of a transistor with two gates, and the size of the AND gate structure of this embodiment is smaller than that of six transistors. In addition, since the first gate and the second gate are both located in the substrate, the space utilization rate of the substrate can be further improved.

In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the embodiments of the present invention, many technical details are provided to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can be implemented.

An embodiment of the present invention provides an AND gate structure. FIG. 2 is a schematic diagram of the AND gate structure provided by this embodiment, and FIG. 3 is an equivalent circuit diagram of FIG. 2 . 2-3 , the AND gate structure includes: a substrate 10, a source 111 and a drain 112 which are separated from each other and are located in the substrate 10, the drain 112 is used as an output, and the source 111 is used to connect to a power source; a first gate 121 and a second gate 122 which are located in the substrate 10 and are spaced apart, the first gate 121 and the second gate 122 are both located between the source 111 and the drain 112, and the first gate 121 is located between the second gate 122 and the source 111, the first gate 121 is used as a first input, and the second gate 122 is used as a second input; a gate dielectric layer 13, the gate dielectric layer 13 is located in the substrate 10, and is in contact with the first gate 121 and the second gate 122, and the gate dielectric layer 13 is also located between the first gate 121 and the second gate 122; wherein, based on the voltage of the first input and the voltage of the second input, the substrate 10 below the gate dielectric layer 13 is suitable for forming a conductive channel 16, and the conductive channel 16 connects the source 111 and the drain 112.

The first gate 121 , the second gate 122 , the source 111 and the drain 112 form a double-gate transistor, and the double-gate transistor can be used to form an AND gate structure. Compared with the AND gate structure with six transistors, the AND gate structure of this embodiment has a smaller size.

The following will provide a detailed description with reference to the accompanying drawings.

2 , the substrate 10 is made of semiconductor material, such as silicon, germanium, silicon-on-insulator, III-V semiconductor, etc. In this embodiment, the substrate 10 also has P-type doping ions, such as boron.

The source 111 is connected to a power source, and further, the power source voltage is 0.8V to 3V.

The drain 112 serves as the output of the AND gate circuit, and its output value is determined by the two inputs.

The source 111 and the drain 112 are located in the substrate 10. The material of the source 111 and the drain 112 is the same as that of the substrate 10 and has doped ions. In this embodiment, the source 111 and the drain 112 have N-type doped ions, such as phosphorus. It can be understood that in other embodiments, the substrate may also have N-type doped ions, and correspondingly, the source and the drain have P-type doped ions.

In this embodiment, the depth of the source electrode 111 in the substrate 10 is equal to the depth of the drain electrode 112 in the substrate 10. Further, in the direction perpendicular to the upper surface of the substrate 10, the ratio of the thickness of the first gate electrode 121 to the depth of the source electrode 111 in the substrate 10 is 2:1 to 10:1; the ratio of the thickness of the second gate electrode 122 to the depth of the drain electrode 112 in the substrate 10 is 2:1 to 10:1. In this way, the first gate electrode 121 and the source electrode 111 can have a smaller facing area to reduce the parasitic capacitance of the two; similarly, the second gate electrode 122 and the drain electrode 112 can have a smaller facing area to reduce the parasitic capacitance of the two.

The first gate 121 and the second gate 122 are both located in the substrate 10. Compared with being located on the substrate 10, the first gate 121 and the second gate 122 are located in the substrate 10 to improve the space utilization of the substrate 10. In addition, compared with six transistors, the size of a transistor with dual gates is smaller.

In a direction perpendicular to the upper surface of the substrate 10, the thickness of the first gate 121 is equal to the thickness of the second gate 122; and in the arrangement direction of the first gate 121 and the second gate 122, the width of the first gate 121 is equal to the width of the second gate 122. When the width and thickness of the first gate 121 and the second gate 122 are the same, the electrical properties of the two are close, thereby improving the performance of the AND gate structure. In other embodiments, the thickness of the first gate may not be equal to the thickness of the second gate, and the width of the first gate may not be equal to the width of the second gate.

The material of the first gate 121 is a low-resistance metal, such as tungsten, molybdenum, tantalum, titanium nitride, polysilicon, silicide, gold or silver, etc. The material of the second gate 122 is a low-resistance metal, such as tungsten, molybdenum, tantalum, titanium nitride, polysilicon, silicide, gold or silver, etc. In this embodiment, the material of the first gate 121 is the same as the material of the second gate 122.

In this embodiment, the gate dielectric layer 13 is also located between the first gate 121 and the source 111, the gate dielectric layer 13 is also located between the second gate 122 and the drain 112, and the gate dielectric layer 13 is also located on the lower surface of the first gate 121 and the lower surface of the second gate 122. That is, the gate dielectric layer 13 is used to isolate the first gate 121 from the source 111 and the substrate 10, and is also used to isolate the second gate 122 from the drain 112 and the substrate 10, and is also used to isolate the first gate 121 from the second gate 122.

Furthermore, the thickness of the gate dielectric layer 13 between the first gate 121 and the source 111 is equal to the thickness of the gate dielectric layer 13 between the second gate 122 and the drain 112, thereby making the threshold voltages of the first gate 121 and the second gate 122 equal, thereby facilitating the control of the AND gate structure.

The thickness of the gate dielectric layer 13 between the first gate 121 and the second gate 122 is 1 nm to 3 nm. When the thickness of the gate dielectric layer 13 is within the above range, the isolation effect between the first gate 121 and the second gate 122 can be improved to avoid leakage or short circuit between the two.

The working principle of the AND gate structure will be described in detail below.

2 and 3 , the source 111 is connected to a power supply voltage, the first gate 121 is used as a first input, the second gate 122 is used as a second input, and the drain 112 is used as an output.

When the voltage of the first input is high and the voltage of the second input is high, the electrons in the substrate 10 gather under the entire gate dielectric layer 13; after the power supply voltage is applied to the source 111, the electrons move from the source 111 to the drain 112, forming a conductive channel 16, and the conductive channel 16 connects the source 111 and the drain 112. At this time, the voltage output by the drain 112 is high, that is, signal 1.

It should be noted that the high level referred to in this embodiment is only relative to the low level and is not limited to its specific size. For example, it is not limited to a specific voltage or a power supply voltage. Secondly, it is not limited to the voltages of all high levels referred to in this embodiment being equal. As long as the relative voltage is higher, it can be called a high voltage.

When the voltage of the first input is at a low level and the voltage of the second input is at a high level, the electrons in the substrate 10 are only gathered under the gate dielectric layer 13 corresponding to the second gate 122, and no electrons are gathered under the gate dielectric layer 13 corresponding to the first gate 121; after the power supply voltage is applied to the source 111, the electrons cannot move from the source 111 to the drain 112, that is, the conductive channel 16 cannot be formed. At this time, the voltage output by the drain 112 is a low level, that is, a signal 0.

It should be noted that the concept of low level in this embodiment is similar to the concept of full high level, which is only a relative concept. The low level in this embodiment is not limited to a specific value, nor is it limited to being equal.

When the voltage of the first input is high and the voltage of the second input is low, the electrons in the substrate 10 are only gathered under the gate dielectric layer 13 corresponding to the first gate 121, and no electrons are gathered under the gate dielectric layer 13 corresponding to the second gate 122; after the power supply voltage is applied to the source 111, the conductive channel 16 cannot be formed. At this time, the voltage output by the drain 112 is low, that is, the signal 0.

When the voltage of the first input is low and the voltage of the second input is low, the electrons in the substrate 10 cannot gather under the gate dielectric layer 13; after the power supply voltage is applied to the source 111, the conductive channel 16 cannot be formed. At this time, the voltage output by the drain 112 is low, that is, signal 0. From the above analysis, it can be seen that only when the first input and the second input are both high, a high level can be output.

Furthermore, when a high-level output is to be achieved, the voltage of the first input is a high level, the voltage of the second input is a high level, and in some embodiments, the voltage of the first input and the voltage of the second input are greater than or equal to the voltage of the power supply. It is understandable that when the voltage at one end of the power supply is transmitted from the source 111 to the drain 112, there will be a certain loss, so that the voltage output by the drain 112 is slightly reduced; when the voltage of the first input and the voltage of the second input are greater than or equal to the voltage of the power supply, the voltage loss can be compensated, thereby improving the accuracy of the output signal.

In this embodiment, when the output signal is 1, the voltage of the first input is 0.8V to 3V, and the voltage of the second input is 0.8V to 3V. When the output signal is 0, the voltage of the first input is 0V-0.2V, and the voltage of the second input is 0.8V to 3V; or, the voltage of the first input is 0.8V to 3V, and the voltage of the second input is 0V-0.2V; or, the voltage of the first input is 0V-0.2V, and the voltage of the second input is 0V-0.2V.

In addition, the AND gate structure in this embodiment also includes: a resistor structure, one end of the resistor structure is connected to the drain 112, and the other end of the resistor structure is connected to the ground; the resistance of the resistor structure is greater than the sum of the resistances of the source 111, the conductive channel 16 and the drain 112. The main reason is that if the drain 112 is not grounded through the resistor structure, the drain 112 may be in a floating state; when the input of the first gate 121 and/or the second gate 122 is a low level, the floating drain 112 may be affected by the hysteresis effect and output an uncertain signal. Therefore, the grounding of the resistor structure can pull down the level, thereby outputting a signal of 0.

When the inputs of the first gate 121 and the second gate 122 are at a high level, current flows through the conductive channel; since the drain 112 is connected in series with the resistor structure, and the resistance of the resistor structure is greater than the sum of the resistances of the source 111, the conductive channel 16, and the drain 112, the voltage division of the resistor structure is greater than the sum of the voltage division of the source 111, the conductive channel 16, and the drain 112, that is, the end of the resistor structure connected to the drain 112 has a larger voltage, and further, the end of the drain 112 output is at a high level. Therefore, in this embodiment, by grounding the drain 112 and the resistor structure, the accuracy of the output signal can be further improved.

The resistance of the resistance structure and the resistance of the drain 112 are between 2 and 100 times the sum of the resistances of the source 111, the conductive channel 16 and the drain 112. It can be understood that when the input of the first gate 121 and the second gate 122 is at a high level, the greater the difference between the resistance of the resistance structure and the sum of the resistances of the source 111, the conductive channel 16 and the drain 112, the greater the voltage division of the resistance structure, that is, the greater the output voltage of the end where the drain 112 is connected to the resistance structure; therefore, when the difference between the resistance of the drain 112 and the resistance structure is maintained within the above-mentioned larger range, the accuracy of the output signal can be further improved, and at the same time, the chip area can be kept from being too large.

Furthermore, in this embodiment, the resistor structure is located inside the substrate 10, thereby improving the utilization rate of the space of the substrate 10. In other embodiments, the resistor structure may also be located on the substrate.

In summary, in this embodiment, the AND gate structure is composed of a transistor with a double gate, and compared with the AND gate structure with six transistors, the size of the AND gate structure of this embodiment is smaller. In addition, one end of the resistor structure is connected to the drain 112, and the other end is grounded, which can improve the accuracy of the output signal of the AND gate structure.

Another embodiment of the present invention provides a method for manufacturing an AND gate structure, and Figures 4 to 8 are schematic diagrams of structures corresponding to the steps in the method for manufacturing an AND gate structure provided in this embodiment.

4 , a substrate 20 is provided, and a source electrode 211 and a drain electrode 212 separated from each other are formed in the substrate 20 .

The substrate 20 is a semiconductor material, such as silicon, germanium, silicon-on-insulator, III-V semiconductor, etc. In this embodiment, the substrate 20 also has P-type doping ions, such as boron.

In this embodiment, the source 211 and the drain 212 are formed by ion implantation. In this embodiment, the doping ions of the source 211 and the drain 212 are N-type, such as phosphorus. In other embodiments, the substrate may also have N-type doping ions, and correspondingly, the source and the drain may have P-type doping ions.

It is worth noting that, in this embodiment, the source 211 and the drain 212 are formed before the first gate and the second gate. In other embodiments, the first gate and the second gate may also be formed before the source 211 and the drain 212.

A trench 24 is formed in the substrate 20, and the trench 24 is also located between the source 211 and the drain 212. The sidewall of the trench 24 is also in contact with the sidewalls of the source 211 and the drain 212. In this embodiment, the trench 24 is formed by dry etching.

5 to 8 , a gate dielectric layer 23, a first gate 221, and a second gate 222 are formed to fill the trench 24. The first gate 221 and the second gate 222 are spaced apart, and the first gate 221 is located between the second gate 222 and the source 211; the gate dielectric layer 23 is located on the sidewall and bottom of the trench 24, and is also located between the first gate 221 and the second gate 222. For the description of the materials of the gate dielectric layer 23, the first gate 221, and the second gate 222, please refer to the previous embodiment, which will not be repeated here.

Specifically, the steps of forming the gate dielectric layer 23 filling the trench 24, the first gate 221 and the second gate 222 include:

5 , an initial gate dielectric layer 231 is formed to fill the trench 24. In this embodiment, a chemical vapor deposition process is used to form the initial gate dielectric layer 231. The chemical vapor deposition process has a relatively fast deposition rate and can improve production efficiency.

6 , a first groove 251 and a second groove 252 are formed in the initial gate dielectric layer 231 , and the first groove 251 is located between the source 211 and the second groove 252 . The remaining initial gate dielectric layer 231 serves as the gate dielectric layer 23 .

In this embodiment, the first groove 251 and the second groove 252 are formed by dry etching. The depth of the first groove 251 in the substrate 20 is the same as the depth of the second groove 252 in the substrate 20. In the arrangement direction of the first groove 251 and the second groove 252, the width of the first groove 251 and the second groove 252 is the same.

In this embodiment, the thickness of the gate dielectric layer 23 in contact with the source electrode 211 is equal to the thickness of the gate dielectric layer 23 in contact with the drain electrode 212 .

7 , the first gate 221 filling the first groove 251 (see FIG. 6 ) is formed, and the second gate 222 filling the second groove 252 (see FIG. 6 ) is formed.

In this embodiment, the first gate 221 and the second gate 222 are formed by physical vapor deposition. Specifically, an initial gate layer is formed to fill the first groove 251 and the second groove 252, and the initial gate layer is also located on the upper surface of the substrate 20; the initial gate layer is back-etched to form the first gate 221 located in the first groove 251 and the second gate 222 located in the second groove 252. The top surfaces of the first gate 221 and the second gate 222 are lower than the top surface of the substrate 20.

8 , a capping gate layer 232 is formed on the upper surfaces of the first gate 221 and the second gate 222. The capping gate layer 232 is used to protect the first gate 221 and the second gate 222 from being oxidized.

In this embodiment, the method further includes: forming a resistor structure (not shown) connected to the drain 212 , and the resistance of the resistor structure is greater than the resistance of the drain.

The resistor structure is used to be connected to the ground terminal. It is understandable that if the drain 212 is not grounded through the resistor structure, the drain 212 is in a suspended state. When the input of the first gate and/or the second gate is at a low level, the drain 212 in the suspended state is likely to be affected by the time lag effect and output an uncertain signal. Therefore, the resistor structure is grounded, which can pull down the level, thereby outputting a signal of 0, thereby improving the accuracy of the signal output.

In this embodiment, a resistor structure is formed inside the substrate 20, which can improve the space utilization of the substrate 20 and is conducive to further reducing the size of the gate structure. Specifically, a third groove and a fourth groove are formed in the substrate 20, and the third groove is in contact with the drain 212; a contact structure filling the third groove and a resistor structure filling the fourth groove are formed. The contact structure electrically connects the resistor structure to the drain. In other embodiments, a resistor structure can also be formed on the substrate. Specifically, an initial resistor structure can be formed first, and the initial resistor structure can be patterned to form a resistor structure.

In summary, since the gate dielectric layer 23, the first gate 221 and the second gate 222 are formed in the substrate 20 in this embodiment, and the first gate 221 and the second gate 222 are both located between the source 211 and the drain 212, compared with the AND gate structure of six transistors, the buried dual-gate transistor formed in this embodiment can reduce the size of the AND gate structure. In addition, the first gate 221 and the second gate 222 are formed by filling the first groove 251 and the second groove 252 by physical vapor deposition, which can reduce the damage of etching to the first gate 221 and the second gate 222, thereby improving the yield of the semiconductor structure.

Another embodiment of the present invention provides a method for manufacturing an AND gate structure. This embodiment is substantially the same as the previous embodiment, and the main difference is that the method for forming the gate dielectric layer, the first gate and the second gate in this embodiment is different. For the parts that are the same or similar to the previous embodiment, please refer to the previous embodiment, and no further description is given here. Figures 9 to 12 are schematic diagrams of the structures corresponding to the steps in the method for manufacturing the semiconductor structure provided in this embodiment. The following will be described in detail with reference to the accompanying drawings.

9 , a substrate 30 is provided, and a source electrode 311 and a drain electrode 312 separated from each other are formed in the substrate 30 .

A trench 34 is formed in the substrate 30 , and the trench 34 is also located between the source 311 and the drain 312 .

9 to 12, a gate dielectric layer 33, a first gate 321, and a second gate 322 are formed to fill the trench 34. The first gate 321 and the second gate 322 are spaced apart, and the first gate 321 is located between the second gate 322 and the source 311. The gate dielectric layer 33 is located on the sidewall and bottom of the trench 34, and is also located between the first gate 321 and the second gate 322. For the description of the materials of the gate dielectric layer 33, the first gate 321, and the second gate 322, please refer to the aforementioned embodiment, which will not be repeated here.

Specifically, the steps of forming the gate dielectric layer 33 filling the trench 34, the first gate 321 and the second gate 322 include:

9 , an edge gate dielectric layer 331 is formed on the sidewall and bottom of the trench 34 . In this embodiment, the thickness of the edge gate dielectric layer 331 in contact with the source 311 is equal to the thickness of the edge gate dielectric layer 331 in contact with the drain 312 .

In this embodiment, the edge gate dielectric layer 331 is formed by an atomic layer deposition process. The atomic layer deposition process can improve the uniformity of the thickness of the edge gate dielectric layer 331. In other embodiments, the edge gate dielectric layer can also be formed by a chemical vapor deposition process.

10 , an initial gate layer 32 is formed on the edge gate dielectric layer 331 , and the initial gate layer 32 completely fills the trench 34 (see FIG. 9 ). In this embodiment, the initial gate layer 32 is formed by physical vapor deposition.

11 , a portion of the initial gate layer 32 (see FIG. 10 ) is removed to form a groove 35 penetrating the initial gate layer 32 , and a first gate 321 and a second gate 322 located at both sides of the groove 35 .

In this embodiment, dry etching is used to form the groove 35 . In addition, dry etching is also used to reduce the height of the first gate 321 and the second gate 322 , so that the top surfaces of the first gate 321 and the second gate 322 are lower than the top surface of the substrate 30 .

12 , an intermediate gate dielectric layer 332 is formed to fill the groove 35 (see FIG. 11 ), and the intermediate gate dielectric layer 332 also covers the top surfaces of the first gate 321 and the second gate 322 . The intermediate gate dielectric layer 332 and the edge gate dielectric layer 331 constitute the gate dielectric layer 33 .

In summary, compared with forming an initial gate dielectric layer that fills the trench 34 , forming the edge gate dielectric layer 331 at the bottom and sidewall of the trench 34 can reduce deposition time, thereby improving production efficiency.

It can be understood by those skilled in the art that the above-mentioned embodiments are specific examples for realizing the present invention, and in practical applications, various changes can be made to them in form and details without departing from the spirit and scope of the present invention. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention shall be based on the scope defined in the claims.

Claims (15)

1. An and gate structure comprising:

The substrate is positioned in the substrate, and the source electrode and the drain electrode are mutually separated, the drain electrode is used as output, and the source electrode is used for connecting a power supply;

The first grid electrode and the second grid electrode are arranged in the substrate at intervals, the first grid electrode and the second grid electrode are both arranged between the source electrode and the drain electrode, the first grid electrode is arranged between the second grid electrode and the source electrode, the first grid electrode is used as a first input, and the second grid electrode is used as a second input;

The gate dielectric layer is positioned in the substrate, is in contact with the first grid electrode and the second grid electrode, and is also positioned between the first grid electrode and the second grid electrode; the substrate under the gate dielectric layer is suitable for forming a conductive channel based on the voltage of the first input and the voltage of the second input, and the conductive channel connects the source electrode and the drain electrode.

2. The and gate structure of claim 1, further comprising: one end of the resistor structure is connected with the drain electrode, and the other end of the resistor structure is connected with the ground end; the resistance of the resistive structure is greater than the sum of the resistances of the source, the conductive channel, and the drain.

3. The and gate structure of claim 2, wherein the resistive structure is located within or on the substrate.

4. The and gate structure of claim 2, wherein the resistance of said resistive structure is between 2-100 times the sum of the resistances of said source, said conductive path and said drain.

5. The and gate structure of claim 2, wherein the voltage of the first input is high, the voltage of the second input is high, and the voltage of the output is high;

or the voltage of the first input is low level, the voltage of the second input is high level, and the voltage of the output is low level;

Or the voltage of the first input is high level, the voltage of the second input is low level, and the voltage of the output is low level;

Or the voltage of the first input is low level, the voltage of the second input is low level, and the voltage of the output is low level.

6. The and gate structure of claim 5, wherein the voltage of the first input is high, the voltage of the second input is high, and the voltage of the first input and the voltage of the second input are greater than or equal to the voltage of the power supply.

7. The and gate structure of claim 1, wherein the gate dielectric layer is further between the first gate and the source, the gate dielectric layer is further between the second gate and the drain, and the gate dielectric layer is further between a lower surface of the first gate and a lower surface of the second gate.

8. The and gate structure of claim 7, wherein a thickness of the gate dielectric layer between the first gate and the source is equal to a thickness of the gate dielectric layer between the second gate and the drain.

9. The and gate structure of claim 1, wherein a thickness of the first gate is equal to a thickness of the second gate in a direction perpendicular to the upper surface of the substrate; and the width of the first grid electrode is equal to the width of the second grid electrode in the arrangement direction of the first grid electrode and the second grid electrode.

10. The and gate structure of claim 1, wherein a depth of the source within the substrate is equal to a depth of the drain within the substrate.

11. The and gate structure of claim 10, wherein a ratio of a thickness of the first gate to a depth of the source within the substrate in a direction perpendicular to the upper surface of the substrate is 2:1 to 10:1; the ratio of the thickness of the second grid electrode to the depth of the drain electrode in the substrate is 2:1-10:1.

12. The and gate structure of claim 1, wherein a thickness of the gate dielectric layer between the first gate and the second gate is 1nm to 3nm.

13. A method of manufacturing an and gate structure, comprising:

Providing a substrate, and forming a source electrode and a drain electrode which are mutually separated in the substrate;

forming a trench within the substrate, the trench further located between the source and the drain;

Forming a gate dielectric layer, a first gate and a second gate which are filled in the groove;

The first grid electrode and the second grid electrode are arranged at intervals, and the first grid electrode is positioned between the second grid electrode and the source electrode;

The gate dielectric layer is positioned on the side wall and the bottom of the groove and is also positioned between the first gate and the second gate.

14. The method of manufacturing an and gate structure according to claim 13, further comprising: and forming a resistance structure connected with the drain electrode, wherein the resistance of the resistance structure is 2-100 times greater than the sum of the resistances of the source electrode, the conductive channel and the drain electrode.

15. The method of manufacturing an and gate structure according to claim 13, wherein the step of forming a gate dielectric layer, a first gate and a second gate filling the trench comprises:

forming an initial gate dielectric layer filled in the groove;

Forming a first groove and a second groove which are arranged at intervals in the initial gate dielectric layer, wherein the first groove is positioned between the source electrode and the second groove; the remaining initial gate dielectric layer is used as the gate dielectric layer;

forming the first grid electrode filling the first groove and forming the second grid electrode filling the second groove.