CN115188761A - Semiconductor structure - Google Patents

Abstract

A semiconductor structure, comprising: the substrate comprises a plurality of mutually-separated active regions, the active regions are arranged along a first direction and are parallel to a second direction, and the first direction is vertical to the second direction; the first grooves are arranged along the second direction and penetrate through the active regions along the first direction; the word line gate structure is positioned in the first groove and comprises a first side area and a second side area which are opposite, and the second side area is adjacent to the active area; the first isolation structure is positioned in the first groove, is adjacent to the first side region of the word line grid structure, is positioned between the word line grid structure and the active region, and is also positioned in part of the active region; a plurality of capacitor structures located on the first side of each active region; and the bit line structures are arranged along the first direction and are parallel to the second direction. The performance of the semiconductor structure is improved.

Description

semiconductor structure

technical field

The present invention relates to the field of semiconductors, and in particular, to a semiconductor structure.

Background technique

Dynamic Random Access Memory (DRAM for short) is a semiconductor memory whose main function is to use the amount of stored charge in a capacitor to represent whether a binary bit (bit) is 1 or 0.

The basic memory cell of dynamic random access memory (DRAM) consists of a transistor and a storage capacitor, while the memory array consists of multiple memory cells. Therefore, the size of the memory chip area depends on the area size of the basic memory cell.

Existing dynamic random access memory has yet to be improved.

SUMMARY OF THE INVENTION

The technical problem solved by the present invention is to provide a semiconductor structure to improve the performance of dynamic random access memory.

In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, comprising: a substrate, the substrate includes a first surface and a second surface opposite to each other, the substrate includes a plurality of mutually separated active regions, a plurality of The active regions are arranged along the first direction, and a plurality of the active regions are parallel to the second direction, and the first direction and the second direction are perpendicular to each other; a plurality of first grooves located in the substrate, so The first groove extends from the first surface to the second surface, a plurality of the first grooves are arranged along the second direction, and the first grooves pass through a plurality of the active regions along the first direction; located in the first groove A word line gate structure in a trench, the word line gate structure includes an opposite first side region and a second side region, the second side region is adjacent to the active region; located in the first recess The first isolation structure is adjacent to the first side region of the word line gate structure, the first isolation structure is located between the word line gate structure and the active region, and the first isolation structure is also a number of capacitor structures located on the first surface of each of the active regions; a number of bit line structures located on the second surface of the substrate, the number of the bit line structures are arranged along the first direction, and Several of the bit line structures are parallel to the second direction.

Optionally, the word line gate structure includes a gate dielectric layer on the sidewall surface and the bottom surface of the first groove and a gate layer on the surface of the gate dielectric layer.

Optionally, a bottom plane of the first isolation structure in a direction toward the second surface of the substrate is lower than half of the height of the gate layer.

Optionally, the material of the gate layer includes polysilicon or metal, and the metal includes tungsten.

Optionally, the gate layer includes a first subsection located at the bottom of the first groove and a second subsection located on the first subsection, and the materials of the first subsection and the second subsection are different.

Optionally, the ratio of the height of the second subsection to the height of the first subsection ranges from 1:4 to 4:1.

Optionally, the material of the first subsection includes metal, the metal includes tungsten, and the material of the second subsection includes polysilicon; the bottom of the first isolation structure in the direction toward the second surface of the substrate The plane is lower than the bottom plane of the second subsection in a direction towards the second face of the substrate.

Optionally, the material of the first subsection includes polysilicon, the material of the second subsection includes metal, and the metal includes tungsten; the bottom of the first isolation structure in the direction toward the second surface of the substrate The plane is lower than the bottom plane of the first subsection in a direction towards the second side of the substrate.

Optionally, the active region also exposes the bottom surface of the gate dielectric layer.

Optionally, the method further includes: a first doped region located on the first surface of the active region; each capacitor structure is electrically connected to one of the first doped regions respectively.

Optionally, the projection of the capacitor structure on the first surface of the active region at least coincides with a part of the first doped region.

Optionally, it further includes: a capacitor plug located between the capacitor structure and the first doped region, the capacitor plug electrically connecting the capacitor structure and the first doped region.

Optionally, the method further includes: a top surface of the word line gate structure facing the first side of the substrate is lower than a bottom surface of the first doped region facing the second side of the substrate.

Optionally, it further includes: a second doped region located on the second surface of the active region; each bit line structure is electrically connected to the second doped region in one active region, respectively.

Optionally, the method further includes: a bit line plug located between the bit line structure and the second doping region, the bit line plug electrically connecting the bit line structure and the second doping region.

Optionally, there is a second isolation structure between adjacent active regions; the second isolation structure is exposed on the second surface of the substrate.

Optionally, it further includes: a first dielectric layer located on the second surface of the active region and on the second isolation structure, wherein the first dielectric layer has a third groove, and the third groove exposes the active the second surface of the region; the bit line structure is located in the third groove.

Optionally, the bit line structure includes a barrier layer on the sidewall surface and the bottom surface of the third groove, and a bit line layer on the barrier layer.

Optionally, the material of the second isolation structure includes a dielectric material, and the dielectric material includes silicon oxide.

Optionally, the material of the first isolation structure includes a dielectric material, and the dielectric material includes silicon oxide.

Optionally, the method further includes: a second dielectric layer located on the first isolation structure and the first surface of the active region; the capacitor structure is located in the second dielectric layer.

Optionally, the capacitor structure includes: a first electrode layer, a second electrode layer, and a dielectric layer between the first electrode layer and the second electrode layer.

Optionally, the shape of the dielectric layer includes: planar or "U" shape.

Optionally, each of the capacitor structures is located on an active region adjacent to the second side region.

Compared with the prior art, the technical scheme of the present invention has the following beneficial effects:

In the semiconductor structure of the present invention, on the one hand, the bit line structure is located on the second side of the substrate, and the capacitor structure is located on the first side of the substrate, thereby greatly simplifying the difficulty and cost of the manufacturing process; on the other hand, the word line gate The pole structure is located in the substrate, so that the space in the direction perpendicular to the surface of the substrate can be saved, and the density of the memory array unit can be increased; on the other hand, there is a first isolation structure between the word line gate structure and the active region, The second side region of the word line gate structure is adjacent to the active region, and the first side region of the word line gate structure is adjacent to the first isolation structure, so that the first isolation structure can isolate the word line gate The first side region and the active region of the polar structure avoid the situation that the word line gate structure is in contact with the active regions on both adjacent sides at the same time to generate two channels to form parasitic devices, so that the transistor is not easily turned off. Therefore, the leakage current can be reduced, and the performance of the semiconductor structure can be improved.

Further, the material of the gate layer includes polysilicon or tungsten, and the bottom plane of the first isolation structure in the direction toward the second surface of the substrate is lower than half of the height of the gate layer, so as to ensure that The channel of the first side region of the word line gate structure can be completely turned off.

Further, the gate layer includes a first subsection and a second subsection located on the first subsection, the material of the first subsection includes metal, the metal includes tungsten, and the material of the second subsection Polysilicon is included; a bottom plane of the first isolation structure in a direction toward the second side of the substrate is lower than a bottom plane of the second subsection in a direction toward the second side of the substrate. Therefore, the bottom plane of the first isolation structure only needs to be lower than the bottom plane of the second sub-portion, so as to achieve the effect of turning off the channel of the first side region of the word line gate structure.

Further, it also includes: a capacitor plug located between the capacitor structure and the first doped region on the first surface of the active region, the capacitor structure and the first doped region are electrically connected through the capacitor plug, thereby forming The process window for capacitive structures and capacitive plugs can be increased.

Further, the active region also exposes the bottom surface of the gate dielectric layer. . The second surface of the active region is separated from each other, so that after the bit line structure is formed on the second surface of the active region, the generated capacitance is reduced.

Further, the top surface of the word line gate structure facing the first side of the substrate is lower than the bottom surface of the first doped region facing the second side of the substrate. Therefore, the channel formed in the active region of the subsequent word line gate structure will not overlap with the first doping region, so that the performance of the first doping region is prevented from being affected.

Description of drawings

1 is a schematic structural diagram of a semiconductor structure in an embodiment;

2 to 5 are schematic structural diagrams of a semiconductor structure according to an embodiment of the present invention;

6 is a schematic structural diagram of a semiconductor structure in another embodiment of the present invention;

7 is a schematic structural diagram of a semiconductor structure in another embodiment of the present invention;

8 is a schematic structural diagram of a semiconductor structure in another embodiment of the present invention;

9 is a schematic structural diagram of a semiconductor structure in another embodiment of the present invention;

FIG. 10 is a schematic structural diagram of a semiconductor structure in another embodiment of the present invention.

Detailed ways

As mentioned in the background art, the existing dynamic random access memory still needs to be improved. The analysis and description will now be carried out in conjunction with specific embodiments.

FIG. 1 is a schematic structural diagram of a semiconductor structure in an embodiment.

Please refer to FIG. 1 , which includes: a substrate 100 ; a word line gate structure 101 located in the substrate 100 ; a source doped region 103 and a drain doped region 102 located in the substrate 100 on both sides of the word line gate structure 101 ; The bit line structure 105 is electrically connected to the source doped region 103 through the source plug 104 ; the capacitor structure 107 is electrically connected to the drain doped region 102 through the capacitor plug 106 .

The formation process of the semiconductor structure is as follows: firstly, the source doped region 103 and the drain doped region 102 are formed, then the word line gate structure 101 is formed in the substrate 100 , then the source plug 104 and the bit line structure 105 are formed, and then the word line gate structure 101 is formed in the substrate 100 . The capacitor plug 106 is formed, and finally the capacitor structure 107 is formed. The channel of the semiconductor structure is U-shaped, and the source doped region 103 and the drain doped region 102 are on horizontal sides of the word line gate structure 101 . The bit line structure 105 and the capacitor structure 107 are on the same side of the transistor, and both are located above the substrate in the process. The capacitor plug 106 of the capacitor structure 107 needs to pass through the bit line structure 105 , which makes the overall process complexity relatively high, and has extremely high requirements on the photolithography process and alignment.

In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure. On the one hand, the bit line structure is located on the second side of the substrate, and the capacitor structure is located on the first side of the substrate, thereby greatly simplifying the difficulty and cost of the manufacturing process; On the other hand, the word line gate structure is located in the substrate, so that the space in the direction perpendicular to the surface of the substrate can be saved, and the density of the memory array unit can be improved; on the other hand, the word line gate structure and the active There is a first isolation structure between the regions, the second side region of the word line gate structure is adjacent to the active region, and the first side region of the word line gate structure is adjacent to the first isolation structure, so that the first side region of the word line gate structure is adjacent to the first isolation structure. The isolation structure can isolate the first side region and the active region of the word line gate structure, so as to prevent the word line gate structure from being in contact with the active regions on both adjacent sides at the same time to generate two channels to form parasitic devices, so that parasitic devices are formed. A case where the transistor does not easily turn off. Therefore, the leakage current can be reduced, and the performance of the semiconductor structure can be improved.

In order to make the above objects, features and beneficial effects of the present invention more clearly understood, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

2 to 5 are schematic structural diagrams of a semiconductor structure according to an embodiment of the present invention.

Please refer to FIGS. 2 to 5 . FIG. 4 is a top view of the second side 400 of the substrate of FIGS. 2 and 3 , FIG. 5 is a top view of the first side 300 of the substrate of FIGS. 2 and 3 , and FIG. 2 is a section line of FIG. 4 A schematic diagram of a cross-sectional structure in the direction of MM1, FIG. 3 is a schematic diagram of a cross-sectional structure of FIG. 4 along the direction of the section line NN1, the semiconductor structure includes: a substrate, and the substrate includes a first surface 300 and a second surface 400 opposite to each other, the The substrate includes a plurality of discrete active regions 201, a plurality of the active regions 201 are arranged along a first direction X, and a plurality of the active regions 201 are parallel to a second direction Y, the first direction X and the second direction The directions Y are perpendicular to each other.

In this embodiment, the material of the substrate is silicon.

In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of Group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

In this embodiment, a second isolation structure 202 is provided between adjacent active regions 201 , and the second isolation structure 202 is exposed from the second surface 400 of the substrate.

The material of the second isolation structure 202 includes dielectric materials including silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon nitride carbide and nitrogen A combination of one or more of silicon oxycarbide.

In this embodiment, the material of the second isolation structure 202 includes silicon oxide.

Please continue to refer to FIG. 2 to FIG. 5 , the semiconductor structure further includes: a plurality of first grooves (not shown) in the substrate, the first grooves extend from the first surface 300 to the second surface 400 extending, a plurality of the first grooves are arranged along the second direction Y, and the first grooves pass through a plurality of the active regions 201 along the first direction X; the word line gate structure located in the first groove, The word line gate structure includes a first side region (not shown) and a second side region (not shown) opposite to each other, and the second side region is adjacent to the active region 201 .

The word line gate structure includes a gate dielectric layer 208 located on the sidewall surface and the bottom surface of the first groove, and a gate dielectric layer 209 located on the surface of the gate dielectric layer 208 . The word line gate structure is located in the substrate, so that the space in the direction perpendicular to the surface of the substrate can be saved, and the density of the memory array unit can be increased.

In this embodiment, the material of the gate dielectric layer 208 includes silicon oxide or a low-K (K less than 3.9) material; the material of the gate layer 209 includes polysilicon.

In another embodiment, the material of the gate dielectric layer includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; The material of the gate layer includes metal, and the metal includes tungsten.

In another embodiment, the word line gate structure further includes a work function layer located between the gate dielectric layer and the gate layer. The material of the work function layer includes an N-type work function material or a P-type work function material, the N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.

In other embodiments, the gate layer includes a first subsection located at the bottom of the first groove and a second subsection located on the first subsection, and the materials of the first subsection and the second subsection are different .

Please continue to refer to FIG. 2 to FIG. 5 , the semiconductor structure further includes: a first isolation structure 210 located in the first groove, the first isolation structure 210 is adjacent to the first side region of the word line gate structure, the The first isolation structure 210 is located between the word line gate structure and the active region 201 , and the first isolation structure 210 is also located in a part of the active region 201 .

In this embodiment, the first isolation structure 210 is also located on the top surface of the word line gate structure.

The first isolation structure 210 is located between the word line gate structure and the active region 201, and the second side region of the word line gate structure is adjacent to the active region 201, so that the first isolation structure 210 can isolate The first side region and the active region 201 of the word line gate structure prevent the word line gate structure from being in contact with the active regions 201 on both adjacent sides at the same time to generate two channels to form parasitic devices, making it difficult for transistors turn-off condition, thereby reducing leakage current.

The material of the first isolation structure 210 includes dielectric materials including silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon nitride carbide and nitrogen A combination of one or more of silicon oxycarbide.

In this embodiment, the material of the first isolation structure 210 includes silicon oxide.

In this embodiment, the bottom plane of the first isolation structure 210 in the direction toward the second surface 400 of the substrate is lower than half of the height of the gate layer 209 . Therefore, the isolation function of the first isolation structure 210 enables the channel of the first side region of the word line gate structure to be completely turned off, thereby reducing leakage current.

Please continue to refer to FIG. 2 to FIG. 5 , the semiconductor structure further includes: a plurality of capacitor structures 212 located on the first surface 300 of each of the active regions 201 ; a number of bit line structures 215 located on the second surface 400 of the substrate , a number of the bit line structures 215 are arranged along the first direction X, and a number of the bit line structures 215 are parallel to the second direction Y.

In this embodiment, the semiconductor structure further includes: a first doped region 206 located on the first surface 300 of the active region 201 ; each capacitor structure 212 is electrically connected to one of the first doped regions 206 respectively.

The first doping region 206 has doping ions, and the doping ions are N-type or P-type; the N-type ions include phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions ions, boron fluoride ions or indium ions.

In this embodiment, the top surface of the word line gate structure facing the first side 300 of the substrate is lower than the bottom plane of the first doped region 206 facing the second side 400 of the substrate. Therefore, the channel formed in the active region 201 by the subsequent word line gate structure will not overlap with the first doping region 206 , so that the performance of the first doping region 206 is prevented from being affected.

Each of the capacitor structures 212 is located on the active region 201 adjacent to the second side region, and the projection of the capacitor structure 212 on the first surface 300 of the active region 201 is at least part of the first doped region 206 coincident.

The capacitor structure 212 includes: a first electrode layer (not shown), a second electrode layer (not shown), and a dielectric layer (not shown) located between the first electrode layer and the second electrode layer.

The shape of the dielectric layer includes: planar or "U" shape.

When the shape of the dielectric layer is planar, the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.

When the shape of the dielectric layer is a "U" shape, the surface of the first electrode layer is an uneven surface, and the surface of the second electrode layer is an uneven surface; or, the first electrode The surface of the layer is flat, and the surface of the second electrode layer is flat.

The material of the first electrode layer includes: metal or metal nitride; the material of the second electrode layer includes: metal or metal nitride; the metal includes: copper, aluminum, tungsten, cobalt, nickel and tantalum A combination of one or more; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

In this embodiment, a capacitor plug 211 is further provided between the capacitor structure 212 and the first doped region 206 , and the capacitor plug 211 is electrically connected to the capacitor structure 212 and the first doped region 206 .

The material of the capacitor plug 211 includes: metal or metal nitride; the metal includes: one or a combination of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes nitride A combination of one or more of tantalum and titanium nitride.

In another embodiment, the capacitive plug may not be included, and the capacitive structure is electrically connected in direct contact with the first doped region.

In this embodiment, the semiconductor structure further includes: a second dielectric layer (not shown) located on the first isolation structure 202 and the first surface of the active region 201; the capacitor structure 212 is located on the second dielectric layer Inside.

In this embodiment, the semiconductor structure further includes: a second doped region 213 located on the second surface 400 of the active region 201 ; each bit line structure 215 and a second doped region 213 in one active region 201 respectively electrical connection.

The second doping region 213 has doping ions, and the doping ions are N-type or P-type; the N-type ions include phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions ions, boron fluoride ions or indium ions.

In this embodiment, the conductivity type of the dopant ions in the second doping region 213 is the same as the conductivity type of the dopant ions in the first doping region 206 .

In this embodiment, the semiconductor structure further includes: a first dielectric layer 214 located on the second surface 400 of the active region 201 and on the second isolation structure 202 , and the first dielectric layer 214 has a third groove therein (not shown), the third groove exposes the surface of the second surface 400 of the active region 201; the bit line structure 215 is located in the third groove.

The bit line structure 215 includes a barrier layer (not shown) on the sidewall surface and the bottom surface of the third groove, and a bit line layer (not shown) on the barrier layer.

The material of the barrier layer includes metal nitride; the material of the bit line layer includes metal or metal nitride; the metal includes: one or a combination of copper, aluminum, tungsten, cobalt, nickel and tantalum ; The metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

In another embodiment, a bit line plug is further provided between the bit line structure and the second doping region, and the bit line plug electrically connects the bit line structure and the second doping region.

For the semiconductor structure, on the one hand, the capacitor structure 212 is located on the first side 300 of the substrate, and the bit line structure 215 is located on the second side 400 of the substrate, thereby greatly simplifying the difficulty and cost of the manufacturing process; on the other hand, the The word line gate structure is located in the substrate, so that the space in the direction perpendicular to the surface of the substrate can be saved, and the density of the memory array unit can be increased; An isolation structure 210, the second side region of the word line gate structure is adjacent to the active region 201, and the first side region of the word line gate structure is adjacent to the first isolation structure 210, so that the first isolation structure 210 can isolate the first side region of the word line gate structure and the active region 201, so as to prevent the word line gate structure from being in contact with the active regions 201 on both adjacent sides at the same time to generate two channels to form parasitic devices, The situation that makes the transistor difficult to turn off. Therefore, the leakage current can be reduced, and the performance of the semiconductor structure can be improved.

FIG. 6 is a schematic structural diagram of a semiconductor structure in another embodiment of the present invention.

Please refer to FIG. 6 . The view direction of FIG. 6 is the same as that of FIG. 2 . The difference between FIG. 6 and FIG. 2 is that the second surface 400 of the active region exposes the surface of the gate dielectric layer 208 .

In this embodiment, it further includes: a fifth groove (not shown) located in the active region 201 at the bottom of the word line gate structure, the fifth groove extending from the second surface 400 of the substrate to the first surface 300 extends, and the fifth groove exposes the surface of the gate dielectric layer 208, the first isolation structure 214 is also located in the fifth groove; a plurality of second doping regions located in the second surface 400 of the active region 201 313 , a plurality of the second doping regions 313 are separated from each other, and the fifth recess is located between adjacent second doping regions 313 .

The second sides 400 of the active region 201 are separated from each other, so that after the bit line structure 215 is formed on the second doped region 313, the resulting capacitance is reduced.

FIG. 7 is a schematic structural diagram of a semiconductor structure in another embodiment of the present invention.

The view direction of FIG. 7 is the same as that of FIG. 2 . The difference between FIG. 7 and FIG. 2 is that the gate layer includes a first subsection 405 located at the bottom of the first groove and a second subsection located on the first subsection 405 406, the materials of the first subsection 405 and the second subsection 406 are different.

In this embodiment, the material of the first subsection 405 includes metal, the metal includes tungsten, and the material of the second subsection 406 includes polysilicon.

In this embodiment, the bottom plane of the first isolation structure 410 in the direction toward the second surface 400 of the substrate is lower than the bottom plane of the second subsection 406 in the direction toward the second surface 400 of the substrate .

Therefore, the bottom plane of the first isolation structure 410 only needs to be lower than the bottom plane of the second sub-portion 406 to achieve the effect of turning off the channel of the first side region of the word line gate structure.

The ratio of the height of the second subsection 406 to the height of the first subsection 405 ranges from 1:4 to 4:1. Therefore, it can be ensured that the effects of reducing the resistance and reducing the leakage current of the formed word line gate structure can be balanced.

FIG. 8 is a schematic structural diagram of a semiconductor structure in another embodiment of the present invention.

The view direction of FIG. 8 is the same as that of FIG. 2 . The difference between FIG. 8 and FIG. 2 is that the gate layer includes a first subsection 505 located at the bottom of the first groove and a second subsection located on the first subsection 505 506, the materials of the first subsection 505 and the second subsection 506 are different.

In this embodiment, the material of the first subsection 505 includes polysilicon, and the material of the second subsection 506 includes metal, and the metal includes tungsten.

In this embodiment, the bottom plane of the first isolation structure 510 in the direction toward the second surface 400 of the substrate is lower than the bottom plane of the first subsection 505 in the direction toward the second surface 400 of the substrate . Therefore, it is ensured that the first isolation structure 510 can completely isolate the first side region of the word line gate structure and the active region 201, and the effect of turning off the channel of the first side region of the word line gate structure can be achieved.

FIG. 9 is a schematic structural diagram of a semiconductor structure in another embodiment of the present invention.

The view direction of FIG. 9 is the same as that of FIG. 7 . The difference between FIG. 9 and FIG. 7 is that the second surface 400 of the active region exposes the surface of the gate dielectric layer 208 .

In this embodiment, it further includes: a fifth groove (not shown) located in the active region 201 at the bottom of the word line gate structure, the fifth groove extending from the second surface 400 of the substrate to the first surface 300 extends, and the fifth groove exposes the surface of the gate dielectric layer 208, the first isolation structure 214 is also located in the fifth groove; a plurality of second doping regions located in the second surface 400 of the active region 201 613 , a plurality of the second doping regions 613 are separated from each other, and the fifth recess is located between adjacent second doping regions 613 .

The second sides 400 of the active region 201 are separated from each other, so that after the bit line structure 215 is formed on the second doped region 613, the resulting capacitance is reduced.

FIG. 10 is a schematic structural diagram of a semiconductor structure in another embodiment of the present invention.

The view direction of FIG. 10 is the same as that of FIG. 8 . The difference between FIG. 10 and FIG. 8 is that the second surface 400 of the active region exposes the surface of the gate dielectric layer 208 .

In this embodiment, it further includes: a fifth groove (not shown) located in the active region 201 at the bottom of the word line gate structure, the fifth groove extending from the second surface 400 of the substrate to the first surface 300 extends, and the fifth groove exposes the surface of the gate dielectric layer 208, the first isolation structure 214 is also located in the fifth groove; a plurality of second doping regions located in the second surface 400 of the active region 201 713 , a plurality of the second doping regions 713 are separated from each other, and the fifth recess is located between adjacent second doping regions 713 .

The second sides 400 of the active region 201 are separated from each other, so that after the bit line structure 215 is formed on the second doped region 713, the resulting capacitance is reduced.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (24)

1. a semiconductor structure, is characterized in that, comprises: a substrate, the substrate includes a first face and a second face opposite, the substrate includes a plurality of mutually discrete active regions, a plurality of the active regions are arranged along a first direction, and a plurality of the active regions parallel to the second direction, the first direction and the second direction are perpendicular to each other; A plurality of first grooves located in the substrate, the first grooves extend from the first surface to the second surface, a plurality of the first grooves are arranged along the second direction, and the first grooves are along the second surface. A direction runs through several of the active regions; a word line gate structure located in the first recess, the word line gate structure includes an opposite first side region and a second side region, and the second side region is adjacent to the active region; A first isolation structure located in the first groove, the first isolation structure is adjacent to the first side region of the word line gate structure, and the first isolation structure is located between the word line gate structure and the active region, so The first isolation structure is also located in part of the active area; a plurality of capacitor structures located on the first surface of each of the active regions; A plurality of bit line structures located on the second surface of the substrate, the plurality of bit line structures are arranged along the first direction, and the plurality of the bit line structures are parallel to the second direction. 2 . The semiconductor structure of claim 1 , wherein the word line gate structure comprises a gate dielectric layer on the sidewall surface and bottom surface of the first groove and a gate layer on the surface of the gate dielectric layer. 3 . 3 . The semiconductor structure of claim 2 , wherein a bottom plane of the first isolation structure in a direction toward the second side of the substrate is lower than half the height of the gate layer. 4 . 4. The semiconductor structure of claim 2, wherein a material of the gate layer comprises polysilicon or a metal, and the metal comprises tungsten. 5. The semiconductor structure of claim 2, wherein the gate layer comprises a first subsection located at the bottom of the first groove and a second subsection located on the first subsection, the first subsection The material of the division and the second division are different. 6 . The semiconductor structure of claim 5 , wherein the ratio of the height of the second subsection to the height of the first subsection ranges from 1:4 to 4:1. 7 . 7. The semiconductor structure of claim 6, wherein the material of the first subsection comprises metal, the metal comprises tungsten, the material of the second subsection comprises polysilicon; the first isolation structure The bottom plane in the direction toward the second side of the substrate is lower than the bottom plane of the second subsection in the direction toward the second side of the substrate. 8. The semiconductor structure of claim 6, wherein the material of the first subsection comprises polysilicon, the material of the second subsection comprises metal, and the metal comprises tungsten; the first isolation structure The bottom plane in the direction toward the second side of the substrate is lower than the bottom plane of the first subsection in the direction toward the second side of the substrate. 9. The semiconductor structure of claim 2, wherein the active region further exposes a bottom surface of the gate dielectric layer. 10 . The semiconductor structure of claim 1 , further comprising: a first doped region on the first surface of the active region; each capacitor structure is electrically connected to one of the first doped regions, respectively. 11 . 11. The semiconductor structure of claim 10, wherein the projection of the capacitor structure on the first surface of the active region at least coincides with a portion of the first doped region. 12. The semiconductor structure of claim 10, further comprising: a capacitor plug located between the capacitor structure and the first doped region, the capacitor plug electrically connecting the capacitor structure and the first doped region Miscellaneous area. 13. The semiconductor structure of claim 10, further comprising: a top surface of the word line gate structure facing the first side of the substrate is lower than the first doped region facing the second side of the substrate bottom surface. 14. The semiconductor structure of claim 1, further comprising: a second doped region located on the second surface of the active region; the bit line structure is respectively associated with a second doped region in one active region electrical connection. 15. The semiconductor structure of claim 14, further comprising: a bit line plug located between the bit line structure and the second doped region, the bit line plug electrically connecting the bit line line structure and the second doped region. 16 . The semiconductor structure of claim 1 , wherein a second isolation structure is provided between adjacent active regions; the second isolation structure is exposed from the second surface of the substrate. 17 . 17. The semiconductor structure of claim 16, further comprising: a first dielectric layer on the second surface of the active region and on the second isolation structure, the first dielectric layer having a third recess in the first dielectric layer a groove, the third groove exposes the second surface of the active region; the bit line structure is located in the third groove. 18. The semiconductor structure of claim 17, wherein the bit line structure comprises a barrier layer on sidewall surfaces and a bottom surface of the third recess, and a bit line layer on the barrier layer. 19. The semiconductor structure of claim 16, wherein the material of the second isolation structure comprises a dielectric material, the dielectric material comprising silicon oxide. 20. The semiconductor structure of claim 1, wherein the material of the first isolation structure comprises a dielectric material, the dielectric material comprising silicon oxide. 21. The semiconductor structure of claim 1, further comprising: a second dielectric layer on the first isolation structure and on the first surface of the active region; the capacitor structure is located in the second dielectric layer. 22. The semiconductor structure of claim 1, wherein the capacitor structure comprises: a first electrode layer, a second electrode layer, and a dielectric layer between the first electrode layer and the second electrode layer. 23. The semiconductor structure of claim 22, wherein the shape of the dielectric layer comprises a planar shape or a "U" shape. 24. The semiconductor structure of claim 1, wherein each of the capacitor structures is located on an active region adjacent to the second side region.

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